From 7d927cbe73d7caa66b671a468fd3fc5b0247d009 Mon Sep 17 00:00:00 2001 From: Colin Date: Sun, 6 Apr 2025 17:41:26 +0800 Subject: [PATCH] delete unused file in example_soc/fpga --- example_soc/fpga/fpga_icebreaker.f | 6 -- example_soc/fpga/fpga_icebreaker.v | 104 ---------------------- example_soc/fpga/fpga_orangecrab_25f.f | 10 --- example_soc/fpga/fpga_orangecrab_25f.v | 98 -------------------- example_soc/fpga/fpga_ulx3s.f | 12 --- example_soc/fpga/fpga_ulx3s.v | 75 ---------------- example_soc/fpga/pll_25_40.v | 46 ---------- example_soc/fpga/pll_25_50.v | 46 ---------- example_soc/icebreaker-openocd.cfg | 30 ------- example_soc/project_paths.mk | 2 - example_soc/soc/example_soc.v | 77 +++++----------- example_soc/synth/.gitignore | 10 --- example_soc/synth/Icebreaker.mk | 14 --- example_soc/synth/Makefile | 1 - example_soc/synth/ULX3S.mk | 19 ---- example_soc/synth/fpga_icebreaker.pcf | 43 --------- example_soc/synth/fpga_orangecrab_25f.lpf | 44 --------- example_soc/synth/fpga_ulx3s.lpf | 32 ------- example_soc/synth/orangecrab-25f.mk | 23 ----- example_soc/ulx3s-openocd.cfg | 41 --------- 20 files changed, 23 insertions(+), 710 deletions(-) delete mode 100644 example_soc/fpga/fpga_icebreaker.f delete mode 100644 example_soc/fpga/fpga_icebreaker.v delete mode 100644 example_soc/fpga/fpga_orangecrab_25f.f delete mode 100644 example_soc/fpga/fpga_orangecrab_25f.v delete mode 100644 example_soc/fpga/fpga_ulx3s.f delete mode 100644 example_soc/fpga/fpga_ulx3s.v delete mode 100644 example_soc/fpga/pll_25_40.v delete mode 100644 example_soc/fpga/pll_25_50.v delete mode 100644 example_soc/icebreaker-openocd.cfg delete mode 100644 example_soc/project_paths.mk delete mode 100644 example_soc/synth/.gitignore delete mode 100644 example_soc/synth/Icebreaker.mk delete mode 100644 example_soc/synth/Makefile delete mode 100644 example_soc/synth/ULX3S.mk delete mode 100644 example_soc/synth/fpga_icebreaker.pcf delete mode 100644 example_soc/synth/fpga_orangecrab_25f.lpf delete mode 100644 example_soc/synth/fpga_ulx3s.lpf delete mode 100644 example_soc/synth/orangecrab-25f.mk delete mode 100644 example_soc/ulx3s-openocd.cfg diff --git a/example_soc/fpga/fpga_icebreaker.f b/example_soc/fpga/fpga_icebreaker.f deleted file mode 100644 index 256f5c9..0000000 --- a/example_soc/fpga/fpga_icebreaker.f +++ /dev/null @@ -1,6 +0,0 @@ -file fpga_icebreaker.v -file ../libfpga/common/reset_sync.v -file ../libfpga/common/fpga_reset.v -list ../libfpga/common/activity_led.f - -list ../soc/soc.f diff --git a/example_soc/fpga/fpga_icebreaker.v b/example_soc/fpga/fpga_icebreaker.v deleted file mode 100644 index dfb548f..0000000 --- a/example_soc/fpga/fpga_icebreaker.v +++ /dev/null @@ -1,104 +0,0 @@ -/*****************************************************************************\ -| Copyright (C) 2021 Luke Wren | -| SPDX-License-Identifier: Apache-2.0 | -\*****************************************************************************/ - -// FPGA toplevel for ../soc/example_soc.v on an iCEBreaker dev board - -`default_nettype none - -module fpga_icebreaker ( - input wire clk_osc, - - // No external trst_n as iCEBreaker can't easily drive it from FTDI, so we - // generate a pulse internally from FPGA PoR. - input wire tck, - input wire tms, - input wire tdi, - output wire tdo, - - output wire led, - - output wire mirror_tck, - output wire mirror_tms, - output wire mirror_tdi, - output wire mirror_tdo, - - output wire uart_tx, - input wire uart_rx -); - -assign mirror_tck = tck; -assign mirror_tms = tms; -assign mirror_tdi = tdi; -assign mirror_tdo = tdo; - -wire clk_sys = clk_osc; -wire rst_n_sys; -wire trst_n; - -fpga_reset #( - .SHIFT (3) -) rstgen ( - .clk (clk_sys), - .force_rst_n (1'b1), - .rst_n (rst_n_sys) -); - -reset_sync trst_sync_u ( - .clk (tck), - .rst_n_in (rst_n_sys), - .rst_n_out (trst_n) -); - -activity_led #( - .WIDTH (1 << 8), - .ACTIVE_LEVEL (1'b0) -) tck_led_u ( - .clk (clk_sys), - .rst_n (rst_n_sys), - .i (tck), - .o (led) -); - -example_soc #( - .CLK_MHZ (12), - .EXTENSION_A (1), - .EXTENSION_C (0), - .EXTENSION_M (1), - .EXTENSION_ZBA (0), - .EXTENSION_ZBB (0), - .EXTENSION_ZBC (0), - .EXTENSION_ZBS (0), - .EXTENSION_ZBKB (0), - .EXTENSION_ZIFENCEI (0), - .EXTENSION_XH3BEXTM (0), - .EXTENSION_XH3PMPM (0), - .EXTENSION_XH3POWER (0), - .CSR_COUNTER (0), - .U_MODE (0), - .PMP_REGIONS (0), - .BREAKPOINT_TRIGGERS (0), - .IRQ_PRIORITY_BITS (0), - .REDUCED_BYPASS (0), - .MULDIV_UNROLL (1), - .MUL_FAST (0), - .MUL_FASTER (0), - .MULH_FAST (0), - .FAST_BRANCHCMP (1), - .BRANCH_PREDICTOR (0) -) soc_u ( - .clk (clk_sys), - .rst_n (rst_n_sys), - - .tck (tck), - .trst_n (trst_n), - .tms (tms), - .tdi (tdi), - .tdo (tdo), - - .uart_tx (uart_tx), - .uart_rx (uart_rx) -); - -endmodule diff --git a/example_soc/fpga/fpga_orangecrab_25f.f b/example_soc/fpga/fpga_orangecrab_25f.f deleted file mode 100644 index 664fa45..0000000 --- a/example_soc/fpga/fpga_orangecrab_25f.f +++ /dev/null @@ -1,10 +0,0 @@ -file fpga_orangecrab_25f.v -file ../libfpga/common/reset_sync.v -file ../libfpga/common/fpga_reset.v - -list ../soc/soc.f - -# ECP5 DTM is not in main SoC list because the JTAGG primitive doesn't exist -# on most platforms -list ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.f - diff --git a/example_soc/fpga/fpga_orangecrab_25f.v b/example_soc/fpga/fpga_orangecrab_25f.v deleted file mode 100644 index f4cdd6f..0000000 --- a/example_soc/fpga/fpga_orangecrab_25f.v +++ /dev/null @@ -1,98 +0,0 @@ -/*****************************************************************************\ -| Copyright (C) 2021 Luke Wren | -| SPDX-License-Identifier: Apache-2.0 | -\*****************************************************************************/ - -`default_nettype none - -module fpga_orangecrab_25f ( - input wire clk_osc, - output wire [7:0] dbg, - - output wire uart_tx, - input wire uart_rx, - - output rgb_led0_r, - output rgb_led0_g, - output rgb_led0_b, - - output rst_n, - input usr_btn -); - -wire clk_sys = clk_osc; -wire rst_n_sys; -wire trst_n; - -fpga_reset #( - .SHIFT (3) -) rstgen ( - .clk (clk_sys), - .force_rst_n (1'b1), - .rst_n (rst_n_sys) -); - -example_soc #( - .DTM_TYPE ("ECP5"), - .SRAM_DEPTH (1 << 14), - .CLK_MHZ (48), - - .EXTENSION_M (1), - .EXTENSION_A (1), - .EXTENSION_C (0), - .EXTENSION_ZBA (0), - .EXTENSION_ZBB (0), - .EXTENSION_ZBC (0), - .EXTENSION_ZBS (0), - .EXTENSION_ZBKB (0), - .EXTENSION_ZIFENCEI (1), - .EXTENSION_XH3BEXTM (0), - .EXTENSION_XH3PMPM (0), - .EXTENSION_XH3POWER (0), - .CSR_COUNTER (1), - .MUL_FAST (1), - .MUL_FASTER (0), - .MULH_FAST (0), - .MULDIV_UNROLL (1), - .FAST_BRANCHCMP (1), - .BRANCH_PREDICTOR (1) -) soc_u ( - .clk (clk_sys), - .rst_n (rst_n_sys), - - // JTAG connections provided internally by ECP5 JTAGG primitive - .tck (1'b0), - .trst_n (1'b0), - .tms (1'b0), - .tdi (1'b0), - .tdo (/* unused */), - - .uart_tx (uart_tx), - .uart_rx (uart_rx) -); - - // Create a 27 bit register - reg [26:0] counter = 0; - - // Every positive edge increment register by 1 - always @(posedge clk_sys) begin - counter <= counter + 1; - end - - // Output inverted values of counter onto LEDs - assign rgb_led0_r = ~counter[24]; - assign rgb_led0_g = ~counter[25]; - assign rgb_led0_b = 0; - - assign dbg = 8'hff; - - // Reset logic on button press. - // this will enter the bootloader - reg reset_sr = 1'b1; - always @(posedge clk_sys) begin - reset_sr <= {usr_btn}; - end - assign rst_n = reset_sr; - - -endmodule diff --git a/example_soc/fpga/fpga_ulx3s.f b/example_soc/fpga/fpga_ulx3s.f deleted file mode 100644 index 5e48959..0000000 --- a/example_soc/fpga/fpga_ulx3s.f +++ /dev/null @@ -1,12 +0,0 @@ -file fpga_ulx3s.v -file pll_25_50.v -file pll_25_40.v -file ../libfpga/common/reset_sync.v -file ../libfpga/common/fpga_reset.v - -list ../soc/soc.f - -# ECP5 DTM is not in main SoC list because the JTAGG primitive doesn't exist -# on most platforms -list ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.f - diff --git a/example_soc/fpga/fpga_ulx3s.v b/example_soc/fpga/fpga_ulx3s.v deleted file mode 100644 index 2873182..0000000 --- a/example_soc/fpga/fpga_ulx3s.v +++ /dev/null @@ -1,75 +0,0 @@ -/*****************************************************************************\ -| Copyright (C) 2021 Luke Wren | -| SPDX-License-Identifier: Apache-2.0 | -\*****************************************************************************/ - -`default_nettype none - -module fpga_ulx3s ( - input wire clk_osc, - output wire [7:0] dbg, - - output wire uart_tx, - input wire uart_rx -); - -wire clk_sys; -wire pll_sys_locked; -wire rst_n_sys; - -pll_25_50 pll_sys ( - .clkin (clk_osc), - .clkout0 (clk_sys), - .locked (pll_sys_locked) -); - -fpga_reset #( - .SHIFT (3) -) rstgen ( - .clk (clk_sys), - .force_rst_n (pll_sys_locked), - .rst_n (rst_n_sys) -); - -example_soc #( - .DTM_TYPE ("ECP5"), - .SRAM_DEPTH (1 << 15), - .CLK_MHZ (50), - - .EXTENSION_M (1), - .EXTENSION_A (1), - .EXTENSION_C (0), - .EXTENSION_ZBA (0), - .EXTENSION_ZBB (0), - .EXTENSION_ZBC (0), - .EXTENSION_ZBS (0), - .EXTENSION_ZBKB (0), - .EXTENSION_ZIFENCEI (1), - .EXTENSION_XH3BEXTM (0), - .EXTENSION_XH3PMPM (0), - .EXTENSION_XH3POWER (0), - .CSR_COUNTER (1), - .MUL_FAST (1), - .MUL_FASTER (0), - .MULH_FAST (0), - .MULDIV_UNROLL (1), - .FAST_BRANCHCMP (1), - .BRANCH_PREDICTOR (1) -) soc_u ( - .clk (clk_sys), - .rst_n (rst_n_sys), - - // JTAG connections provided internally by ECP5 JTAGG primitive - .tck (1'b0), - .trst_n (1'b0), - .tms (1'b0), - .tdi (1'b0), - .tdo (/* unused */), - - .uart_tx (uart_tx), - .uart_rx (uart_rx) -); - -assign dbg = 8'h00; - -endmodule diff --git a/example_soc/fpga/pll_25_40.v b/example_soc/fpga/pll_25_40.v deleted file mode 100644 index 67c86a2..0000000 --- a/example_soc/fpga/pll_25_40.v +++ /dev/null @@ -1,46 +0,0 @@ -// diamond 3.7 accepts this PLL -// diamond 3.8-3.9 is untested -// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal -// cause of this could be from wrong CPHASE/FPHASE parameters -module pll_25_40 -( - input clkin, // 25 MHz, 0 deg - output clkout0, // 40 MHz, 0 deg - output locked -); -(* FREQUENCY_PIN_CLKI="25" *) -(* FREQUENCY_PIN_CLKOP="40" *) -(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) -EHXPLLL #( - .PLLRST_ENA("DISABLED"), - .INTFB_WAKE("DISABLED"), - .STDBY_ENABLE("DISABLED"), - .DPHASE_SOURCE("DISABLED"), - .OUTDIVIDER_MUXA("DIVA"), - .OUTDIVIDER_MUXB("DIVB"), - .OUTDIVIDER_MUXC("DIVC"), - .OUTDIVIDER_MUXD("DIVD"), - .CLKI_DIV(5), - .CLKOP_ENABLE("ENABLED"), - .CLKOP_DIV(15), - .CLKOP_CPHASE(7), - .CLKOP_FPHASE(0), - .FEEDBK_PATH("CLKOP"), - .CLKFB_DIV(8) - ) pll_i ( - .RST(1'b0), - .STDBY(1'b0), - .CLKI(clkin), - .CLKOP(clkout0), - .CLKFB(clkout0), - .CLKINTFB(), - .PHASESEL0(1'b0), - .PHASESEL1(1'b0), - .PHASEDIR(1'b1), - .PHASESTEP(1'b1), - .PHASELOADREG(1'b1), - .PLLWAKESYNC(1'b0), - .ENCLKOP(1'b0), - .LOCK(locked) - ); -endmodule diff --git a/example_soc/fpga/pll_25_50.v b/example_soc/fpga/pll_25_50.v deleted file mode 100644 index e30ff3d..0000000 --- a/example_soc/fpga/pll_25_50.v +++ /dev/null @@ -1,46 +0,0 @@ -// diamond 3.7 accepts this PLL -// diamond 3.8-3.9 is untested -// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal -// cause of this could be from wrong CPHASE/FPHASE parameters -module pll_25_50 -( - input clkin, // 25 MHz, 0 deg - output clkout0, // 50 MHz, 0 deg - output locked -); -(* FREQUENCY_PIN_CLKI="25" *) -(* FREQUENCY_PIN_CLKOP="50" *) -(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *) -EHXPLLL #( - .PLLRST_ENA("DISABLED"), - .INTFB_WAKE("DISABLED"), - .STDBY_ENABLE("DISABLED"), - .DPHASE_SOURCE("DISABLED"), - .OUTDIVIDER_MUXA("DIVA"), - .OUTDIVIDER_MUXB("DIVB"), - .OUTDIVIDER_MUXC("DIVC"), - .OUTDIVIDER_MUXD("DIVD"), - .CLKI_DIV(1), - .CLKOP_ENABLE("ENABLED"), - .CLKOP_DIV(12), - .CLKOP_CPHASE(5), - .CLKOP_FPHASE(0), - .FEEDBK_PATH("CLKOP"), - .CLKFB_DIV(2) - ) pll_i ( - .RST(1'b0), - .STDBY(1'b0), - .CLKI(clkin), - .CLKOP(clkout0), - .CLKFB(clkout0), - .CLKINTFB(), - .PHASESEL0(1'b0), - .PHASESEL1(1'b0), - .PHASEDIR(1'b1), - .PHASESTEP(1'b1), - .PHASELOADREG(1'b1), - .PLLWAKESYNC(1'b0), - .ENCLKOP(1'b0), - .LOCK(locked) - ); -endmodule diff --git a/example_soc/icebreaker-openocd.cfg b/example_soc/icebreaker-openocd.cfg deleted file mode 100644 index 9b46db0..0000000 --- a/example_soc/icebreaker-openocd.cfg +++ /dev/null @@ -1,30 +0,0 @@ -adapter driver ftdi - -# 30 MHz -- a bit exciting but it seems reliable -adapter speed 30000 -ftdi_tdo_sample_edge falling - -# JTAG is on FTDI B channel so it doesn't inadvertently assert flash CS pin -# (usually UART would be on the B channel). - -# Note TDO/TMS require two of the solder jumpers on the back of the board to -# be bridged. On the v1.0e board these are jumpers J3/J4. To find these, look -# for the box of 5 x 2 jumpers (with a few others hanging off the side) and -# they are the two in the central column. They line up with the space in -# between "Jump" and "for" in the silk text "Jump for FTDI FIFO". - -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 -# Use BDBUS0-3 on iCEBreaker to avoid toggling flash chip select -ftdi_channel 1 - -ftdi_layout_init 0x0000 0xffff - -set _CHIPNAME hazard3 -jtag newtap $_CHIPNAME cpu -irlen 5 -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME - -gdb_report_data_abort enable -init -halt diff --git a/example_soc/project_paths.mk b/example_soc/project_paths.mk deleted file mode 100644 index 934f996..0000000 --- a/example_soc/project_paths.mk +++ /dev/null @@ -1,2 +0,0 @@ -# Link up to project root -include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../project_paths.mk diff --git a/example_soc/soc/example_soc.v b/example_soc/soc/example_soc.v index 100b3f7..29f8b49 100644 --- a/example_soc/soc/example_soc.v +++ b/example_soc/soc/example_soc.v @@ -9,7 +9,6 @@ `default_nettype none module example_soc #( - parameter DTM_TYPE = "JTAG", // Can be "JTAG" or "ECP5" parameter SRAM_DEPTH = 1 << 14, // Default 16 kwords -> 64 kB parameter CLK_MHZ = 12, // For timer timebase @@ -77,64 +76,34 @@ reset_sync dmi_reset_sync_u ( .rst_n_out (rst_n_dmi) ); -generate -if (DTM_TYPE == "JTAG") begin - // Standard RISC-V JTAG-DTM connected to external IOs. - // JTAG-DTM IDCODE should be a JEP106-compliant ID: - localparam IDCODE = 32'hdeadbeef; +// Standard RISC-V JTAG-DTM connected to external IOs. +// JTAG-DTM IDCODE should be a JEP106-compliant ID: +localparam IDCODE = 32'hdeadbeef; - hazard3_jtag_dtm #( - .IDCODE (IDCODE) - ) dtm_u ( - .tck (tck), - .trst_n (trst_n), - .tms (tms), - .tdi (tdi), - .tdo (tdo), +hazard3_jtag_dtm #( + .IDCODE (IDCODE) +) dtm_u ( + .tck (tck), + .trst_n (trst_n), + .tms (tms), + .tdi (tdi), + .tdo (tdo), - .dmihardreset_req (dmihardreset_req), + .dmihardreset_req (dmihardreset_req), - .clk_dmi (clk), - .rst_n_dmi (rst_n_dmi), + .clk_dmi (clk), + .rst_n_dmi (rst_n_dmi), - .dmi_psel (dmi_psel), - .dmi_penable (dmi_penable), - .dmi_pwrite (dmi_pwrite), - .dmi_paddr (dmi_paddr), - .dmi_pwdata (dmi_pwdata), - .dmi_prdata (dmi_prdata), - .dmi_pready (dmi_pready), - .dmi_pslverr (dmi_pslverr) - ); - -end else if (DTM_TYPE == "ECP5") begin - - // Attach RISC-V DTM's DTMCS/DMI registers to ECP5 ER1/ER2 registers. This - // allows the processor to be debugged through the ECP5 chip TAP, using - // regular upstream OpenOCD. - - // Connects to ECP5 TAP internally by instantiating a JTAGG primitive. - assign tdo = 1'b0; - - hazard3_ecp5_jtag_dtm dtm_u ( - .dmihardreset_req (dmihardreset_req), - - .clk_dmi (clk), - .rst_n_dmi (rst_n_dmi), - - .dmi_psel (dmi_psel), - .dmi_penable (dmi_penable), - .dmi_pwrite (dmi_pwrite), - .dmi_paddr (dmi_paddr), - .dmi_pwdata (dmi_pwdata), - .dmi_prdata (dmi_prdata), - .dmi_pready (dmi_pready), - .dmi_pslverr (dmi_pslverr) - ); - -end -endgenerate + .dmi_psel (dmi_psel), + .dmi_penable (dmi_penable), + .dmi_pwrite (dmi_pwrite), + .dmi_paddr (dmi_paddr), + .dmi_pwdata (dmi_pwdata), + .dmi_prdata (dmi_prdata), + .dmi_pready (dmi_pready), + .dmi_pslverr (dmi_pslverr) +); localparam N_HARTS = 1; diff --git a/example_soc/synth/.gitignore b/example_soc/synth/.gitignore deleted file mode 100644 index df5a45d..0000000 --- a/example_soc/synth/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -srcs.mk -*.blif -*.asc -*.hex -*.bin -*.json -*.log -*.config -*.svf -*.bit diff --git a/example_soc/synth/Icebreaker.mk b/example_soc/synth/Icebreaker.mk deleted file mode 100644 index 7efec6b..0000000 --- a/example_soc/synth/Icebreaker.mk +++ /dev/null @@ -1,14 +0,0 @@ -include ../project_paths.mk - -CHIPNAME=fpga_icebreaker -DOTF=../fpga/fpga_icebreaker.f -SYNTH_OPT=-dsp -PNR_OPT=--timing-allow-fail --detailed-timing-report - -DEVICE=up5k -PACKAGE=sg48 - -include $(SCRIPTS)/synth_ice40.mk - -prog: bit - iceprog $(CHIPNAME).bin diff --git a/example_soc/synth/Makefile b/example_soc/synth/Makefile deleted file mode 100644 index 747d79e..0000000 --- a/example_soc/synth/Makefile +++ /dev/null @@ -1 +0,0 @@ -include Icebreaker.mk diff --git a/example_soc/synth/ULX3S.mk b/example_soc/synth/ULX3S.mk deleted file mode 100644 index df5651c..0000000 --- a/example_soc/synth/ULX3S.mk +++ /dev/null @@ -1,19 +0,0 @@ -include ../project_paths.mk - -CHIPNAME=fpga_ulx3s -TOP=fpga_ulx3s -DOTF=../fpga/fpga_ulx3s.f - -SYNTH_OPT=-abc9 -PNR_OPT=--timing-allow-fail - -DEVICE=um5g-85k -PACKAGE=CABGA381 - -include $(SCRIPTS)/synth_ecp5.mk - -prog: bit - ujprog $(CHIPNAME).bit - -flash: bit - ujprog -j flash $(CHIPNAME).bit diff --git a/example_soc/synth/fpga_icebreaker.pcf b/example_soc/synth/fpga_icebreaker.pcf deleted file mode 100644 index 7f3fd3f..0000000 --- a/example_soc/synth/fpga_icebreaker.pcf +++ /dev/null @@ -1,43 +0,0 @@ -# 12 MHz oscillator -set_io clk_osc 35 - -# JTAG is on FTDI B channel so it doesn't inadvertently assert flash CS pin -# (usually UART would be on the B channel). - -# Note TDO/TMS require two of the solder jumpers on the back of the board to -# be bridged. On the v1.0e board these are jumpers J3/J4. To find these, look -# for the box of 5 x 2 jumpers (with a few others hanging off the side) and -# they are the two in the central column. They line up with the space in -# between "Jump" and "for" in the silk text "Jump for FTDI FIFO". - -set_io tck 6 # FTDI BDBUS0 -set_io tdi 9 # FTDI BDBUS1 -set_io tdo 18 # FTDI BDBUS2 -set_io tms 19 # FTDI BDBUS3 - -# UART is moved over to FTDI A channel -- this means flash is inaccessible -# (and stays in a quiescent state since CSn is disconnected and pulled high) -set_io uart_rx 15 # FTDI ADBUS0, flash SCK, iCE SCK -set_io uart_tx 14 # FTDI ADBUS1, flash MOSI, iCE SO (if jumper J15 connected) - -set_io led 37 # Green on main board - -# # Buttons -# set_io dpad_u 20 # Snapoff top -# set_io dpad_d 18 # Snapoff bottom -# set_io dpad_l 10 # Main board -# set_io dpad_r 19 # Snapoff middle - -set_io mirror_tck 27 # Left on snapoff (L2) -set_io mirror_tms 25 # Right on snapoff (L3) -set_io mirror_tdi 23 # Top on snapoff (L4) -set_io mirror_tdo 21 # Bottom on snapoff (L5) - -# # LEDs -# set_io led[0] 37 # Green on main board -# set_io led[1] 11 # Red on main board -# set_io led[2] 26 # Middle on snapoff (L1) -# set_io led[3] 27 # Left on snapoff (L2) -# set_io led[4] 25 # Right on snapoff (L3) -# set_io led[5] 23 # Top on snapoff (L4) -# set_io led[6] 21 # Bottom on snapoff (L5) diff --git a/example_soc/synth/fpga_orangecrab_25f.lpf b/example_soc/synth/fpga_orangecrab_25f.lpf deleted file mode 100644 index 7dd583f..0000000 --- a/example_soc/synth/fpga_orangecrab_25f.lpf +++ /dev/null @@ -1,44 +0,0 @@ -# Reference: https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf - -LOCATE COMP "clk_osc" SITE "A9"; -IOBUF PORT "clk_osc" PULLMODE=NONE IO_TYPE=LVCMOS33; -FREQUENCY PORT "clk_osc" 48 MHZ; - -# UART TX/RX (from FPGA's point of view, i.e. TX is an output) - -LOCATE COMP "uart_tx" SITE "N17"; # FPGA transmits to ftdi -LOCATE COMP "uart_rx" SITE "M18"; # FPGA receives from ftdi -IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33; - -# 8 pins on an IO header for bringing signals out to a logic analyser - -LOCATE COMP "dbg[0]" SITE "H2"; # PCLK # "gn[0]" -LOCATE COMP "dbg[1]" SITE "A8"; # PCLK # "gn[1]" -LOCATE COMP "dbg[2]" SITE "B8"; # GR_PCLK # "gn[2]" -LOCATE COMP "dbg[3]" SITE "C8"; # "gn[3]" -LOCATE COMP "dbg[4]" SITE "B9"; # PCLK # "gp[0]" -LOCATE COMP "dbg[5]" SITE "B10"; # PCLK # "gp[1]" -LOCATE COMP "dbg[6]" SITE "L4"; # GR_PCLK # "gp[2]" -LOCATE COMP "dbg[7]" SITE "N3"; # "gp[3]" - -IOBUF PORT "dbg[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; - -LOCATE COMP "rgb_led0_r" SITE "K4"; -IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33; -LOCATE COMP "rgb_led0_g" SITE "M3"; -IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33; -LOCATE COMP "rgb_led0_b" SITE "J3"; -IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33; - -LOCATE COMP "usr_btn" SITE "J17"; -IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I; -LOCATE COMP "rst_n" SITE "V17"; -IOBUF PORT "rst_n" IO_TYPE=LVCMOS33; diff --git a/example_soc/synth/fpga_ulx3s.lpf b/example_soc/synth/fpga_ulx3s.lpf deleted file mode 100644 index 0003f8e..0000000 --- a/example_soc/synth/fpga_ulx3s.lpf +++ /dev/null @@ -1,32 +0,0 @@ -# Reference: https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf - -LOCATE COMP "clk_osc" SITE "G2"; -IOBUF PORT "clk_osc" PULLMODE=NONE IO_TYPE=LVCMOS33; -FREQUENCY PORT "clk_osc" 25 MHZ; - -# UART TX/RX (from FPGA's point of view, i.e. TX is an output) - -LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi -LOCATE COMP "uart_rx" SITE "M1"; # FPGA receives from ftdi -IOBUF PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33; - -# 8 pins on an IO header for bringing signals out to a logic analyser - -LOCATE COMP "dbg[0]" SITE "C11"; # PCLK # "gn[0]" -LOCATE COMP "dbg[1]" SITE "A11"; # PCLK # "gn[1]" -LOCATE COMP "dbg[2]" SITE "B10"; # GR_PCLK # "gn[2]" -LOCATE COMP "dbg[3]" SITE "C10"; # "gn[3]" -LOCATE COMP "dbg[4]" SITE "B11"; # PCLK # "gp[0]" -LOCATE COMP "dbg[5]" SITE "A10"; # PCLK # "gp[1]" -LOCATE COMP "dbg[6]" SITE "A9"; # GR_PCLK # "gp[2]" -LOCATE COMP "dbg[7]" SITE "B9"; # "gp[3]" - -IOBUF PORT "dbg[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; -IOBUF PORT "dbg[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4; diff --git a/example_soc/synth/orangecrab-25f.mk b/example_soc/synth/orangecrab-25f.mk deleted file mode 100644 index 957ce94..0000000 --- a/example_soc/synth/orangecrab-25f.mk +++ /dev/null @@ -1,23 +0,0 @@ -CHIPNAME=fpga_orangecrab_25f -TOP=fpga_orangecrab_25f -DOTF=../fpga/fpga_orangecrab_25f.f - -SYNTH_OPT=-abc9 -PNR_OPT=--timing-allow-fail - -DEVICE=25k -PACKAGE=CSFBGA285 - -DEVICE_IDCODE=0x41111043 - -include $(SCRIPTS)/synth_ecp5.mk - -$(CHIPNAME).dfu: bit - cp $(CHIPNAME).bit $@ - dfu-suffix -v 1209 -p 5af0 -a $@ - -prog: bit - ujprog $(CHIPNAME).bit - -flash: $(CHIPNAME).dfu - dfu-util -d 1209:5af0 -D $< diff --git a/example_soc/ulx3s-openocd.cfg b/example_soc/ulx3s-openocd.cfg deleted file mode 100644 index 5fd4bd1..0000000 --- a/example_soc/ulx3s-openocd.cfg +++ /dev/null @@ -1,41 +0,0 @@ -# Probe config specific to ULX3S. - -adapter driver ft232r -ft232r_vid_pid 0x0403 0x6015 - -# Note adapter_khz doesn't do anything because this is bitbanged JTAG on aux -# UART pins, but... it's mandatory - -adapter speed 1000 - -ft232r_tck_num DSR -ft232r_tms_num DCD -ft232r_tdi_num RI -ft232r_tdo_num CTS -# trst/srst are not used but must have different values than above -ft232r_trst_num RTS -ft232r_srst_num DTR - -# This is the ID for the *FPGA's* chip TAP. (note this ID is for 85F version -# of ULX3S -- if you have a different ECP5 size you can either enter the -# correct ID for your ECP5, or remove the -expected-id part). We are going to -# expose processor debug through a pair of custom DRs on this TAP. - -set _CHIPNAME lfe5u85 -jtag newtap lfe5u85 hazard3 -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5 - -# We expose the DTMCS/DMI DRs you would find on a normal RISC-V JTAG-DTM via -# the ECP5 TAP's ER1/ER2 private instructions. As long as you use the correct -# IR length for the ECP5 TAP, and use the new instructions, the ECP5 TAP -# looks a lot like a JTAG-DTM. - -set _TARGETNAME $_CHIPNAME.hazard3 -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -riscv set_ir dtmcs 0x32 -riscv set_ir dmi 0x38 - -# That's it, it's a normal RISC-V processor now :) - -gdb_report_data_abort enable -init -halt