openocd tb: report AHB error response when processor accesses outside of RAM/IO
This commit is contained in:
Luke Wren
parent
5deff12f95
commit
8014239d47
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@ -17,6 +17,7 @@ static const unsigned int MEM_SIZE = 16 * 1024 * 1024;
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uint8_t mem[MEM_SIZE];
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static const unsigned int IO_BASE = 0x80000000;
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static const unsigned int IO_MASK = 0xffffff00;
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enum {
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IO_PRINT_CHAR = 0,
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IO_PRINT_U32 = 4,
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@ -219,11 +220,15 @@ int main(int argc, char **argv) {
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}
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}
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// Handle current data phase, then move current address phase to data phase
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if (top.p_d__hready.get<bool>()) {
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// Clear bus error by default
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top.p_d__hresp.set<bool>(false);
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// Handle current data phase
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uint32_t rdata = 0;
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bool bus_err = false;
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if (bus_trans && bus_write) {
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uint32_t wdata = top.p_d__hwdata.get<uint32_t>();
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if (bus_addr <= MEM_SIZE) {
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if (bus_addr <= MEM_SIZE - 4u) {
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unsigned int n_bytes = 1u << bus_size;
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// Note we are relying on hazard3's byte lane replication
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for (unsigned int i = 0; i < n_bytes; ++i) {
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@ -241,6 +246,9 @@ int main(int argc, char **argv) {
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printf("Ran for %ld cycles\n", cycle + 1);
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break;
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}
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else {
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bus_err = true;
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}
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}
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else if (bus_trans && !bus_write) {
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if (bus_addr <= MEM_SIZE) {
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@ -251,10 +259,34 @@ int main(int argc, char **argv) {
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mem[bus_addr + 2] << 16 |
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mem[bus_addr + 3] << 24;
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}
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else {
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bus_err = true;
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}
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}
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if (bus_err) {
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// Phase 1 of error response
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top.p_d__hready.set<bool>(false);
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top.p_d__hresp.set<bool>(true);
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}
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top.p_d__hrdata.set<uint32_t>(rdata);
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// Progress current address phase to data phase
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bus_trans = top.p_d__htrans.get<uint8_t>() >> 1;
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bus_write = top.p_d__hwrite.get<bool>();
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bus_size = top.p_d__hsize.get<uint8_t>();
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bus_addr = top.p_d__haddr.get<uint32_t>();
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}
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else {
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// hready=0. Currently this only happens when we're in the first
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// phase of an error response, so go to phase 2.
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top.p_d__hready.set<bool>(true);
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}
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if (top.p_i__hready.get<bool>()) {
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top.p_i__hresp.set<bool>(false);
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if (bus_trans_i) {
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bus_addr_i &= ~0x3u;
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if (bus_addr_i <= MEM_SIZE - 4u) {
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top.p_i__hrdata.set<uint32_t>(
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(uint32_t)mem[bus_addr_i] |
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mem[bus_addr_i + 1] << 8 |
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@ -262,13 +294,17 @@ int main(int argc, char **argv) {
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mem[bus_addr_i + 3] << 24
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);
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}
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bus_trans = top.p_d__htrans.get<uint8_t>() >> 1;
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bus_write = top.p_d__hwrite.get<bool>();
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bus_size = top.p_d__hsize.get<uint8_t>();
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bus_addr = top.p_d__haddr.get<uint32_t>();
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else {
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top.p_i__hready.set<bool>(false);
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top.p_i__hresp.set<bool>(true);
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}
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}
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bus_trans_i = top.p_i__htrans.get<uint8_t>() >> 1;
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bus_addr_i = top.p_i__haddr.get<uint32_t>();
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}
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else {
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top.p_i__hready.set<bool>(true);
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}
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if (dump_waves) {
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// The extra step() is just here to get the bus responses to line up nicely
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@ -1,15 +1,17 @@
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[*]
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[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
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[*] Mon Jul 12 17:15:59 2021
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[*] Sat Jul 17 18:13:53 2021
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[*]
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[dumpfile] "/home/luke/proj/hazard3/test/sim/debug_openocd_bitbang/waves.vcd"
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[dumpfile_mtime] "Mon Jul 12 17:11:32 2021"
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[dumpfile_size] 2961061
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[savefile] "/home/luke/proj/hazard3/test/sim/debug_openocd_bitbang/waves.gtkw"
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[timestart] 0
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[dumpfile] "/home/luke/proj/hazard3/test/sim/openocd/waves.vcd"
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[dumpfile_mtime] "Sat Jul 17 18:07:33 2021"
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[dumpfile_size] 6782392
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[savefile] "/home/luke/proj/hazard3/test/sim/openocd/waves.gtkw"
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[timestart] 140588
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[size] 1920 1043
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[pos] -1 -1
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*-13.000000 18597 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-3.000000 140615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] cpu.
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[treeopen] cpu.core.
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[treeopen] inst_hazard3_jtag_dtm.
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[sst_width] 233
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[signals_width] 222
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@ -21,7 +23,6 @@ trst_n
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rst_n_dmi
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@200
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-
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@201
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-DTM
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@28
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tck
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@ -63,5 +64,32 @@ cpu.dbg_halted
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cpu.dbg_running
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@200
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-
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-Trap stuff
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@22
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cpu.core.inst_hazard3_csr.trap_addr[31:0]
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@28
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cpu.core.inst_hazard3_csr.trap_enter_rdy
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cpu.core.inst_hazard3_csr.trap_enter_vld
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cpu.core.inst_hazard3_csr.trap_is_irq
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@22
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cpu.core.inst_hazard3_csr.except[3:0]
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@28
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cpu.core.m_stall
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@29
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cpu.core.bus_dph_err_d
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@200
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-
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-D Bus
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@22
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d_haddr[31:0]
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@28
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d_htrans[1:0]
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d_hwrite
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d_hsize[2:0]
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d_hready
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d_hresp
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@22
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d_hwdata[31:0]
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d_hrdata[31:0]
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[pattern_trace] 1
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[pattern_trace] 0
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