diff --git a/hdl/Makefile b/hdl/Makefile
index 3d4b744..41ed439 100644
--- a/hdl/Makefile
+++ b/hdl/Makefile
@@ -1,4 +1,4 @@
-DOTF=hazard5.f
-TOP=hazard5_alu
+DOTF=hazard3.f
+TOP=hazard3_alu
 
 include $(SCRIPTS)/formal.mk
diff --git a/hdl/arith/hazard5_alu.v b/hdl/arith/hazard3_alu.v
similarity index 98%
rename from hdl/arith/hazard5_alu.v
rename to hdl/arith/hazard3_alu.v
index a82525a..ebf523c 100644
--- a/hdl/arith/hazard5_alu.v
+++ b/hdl/arith/hazard3_alu.v
@@ -15,7 +15,7 @@
  *                                                                    *
  *********************************************************************/
 
-module hazard5_alu #(
+module hazard3_alu #(
 	parameter W_DATA = 32
 ) (
 	input  wire [3:0]        aluop,
@@ -26,7 +26,7 @@ module hazard5_alu #(
 	output wire              cmp
 );
 
-`include "hazard5_ops.vh"
+`include "hazard3_ops.vh"
 
 function msb;
 input [W_DATA-1:0] x;
@@ -51,7 +51,7 @@ wire [W_DATA-1:0] shift_dout;
 reg shift_right_nleft;
 reg shift_arith;
 
-hazard5_shift_barrel #(
+hazard3_shift_barrel #(
 	.W_DATA(W_DATA),
 	.W_SHAMT(5)
 ) shifter (
diff --git a/hdl/arith/hazard5_mul_fast.v b/hdl/arith/hazard3_mul_fast.v
similarity index 98%
rename from hdl/arith/hazard5_mul_fast.v
rename to hdl/arith/hazard3_mul_fast.v
index ea88594..4391042 100644
--- a/hdl/arith/hazard5_mul_fast.v
+++ b/hdl/arith/hazard3_mul_fast.v
@@ -15,7 +15,7 @@
  *                                                                    *
  *********************************************************************/
 
-module hazard5_mul_fast #(
+module hazard3_mul_fast #(
 	parameter XLEN = 32
 ) (
 	input  wire              clk,
diff --git a/hdl/arith/hazard5_muldiv_seq.v b/hdl/arith/hazard3_muldiv_seq.v
similarity index 99%
rename from hdl/arith/hazard5_muldiv_seq.v
rename to hdl/arith/hazard3_muldiv_seq.v
index d21cc0e..897172a 100644
--- a/hdl/arith/hazard5_muldiv_seq.v
+++ b/hdl/arith/hazard3_muldiv_seq.v
@@ -27,11 +27,11 @@
 // The actual multiply/divide hardware is unsigned. We handle signedness at
 // input/output.
 
-module hazard5_muldiv_seq #(
+module hazard3_muldiv_seq #(
 	parameter XLEN = 32,
 	parameter UNROLL = 1,
 	parameter W_CTR = $clog2(XLEN + 1), // do not modify
-`include "hazard5_width_const.vh"
+`include "hazard3_width_const.vh"
 ) (
 	input  wire               clk,
 	input  wire               rst_n,
@@ -47,7 +47,7 @@ module hazard5_muldiv_seq #(
 	output wire               result_vld
 );
 
-`include "hazard5_ops.vh"
+`include "hazard3_ops.vh"
 
 //synthesis translate_off
 generate if (UNROLL & (UNROLL - 1) || ~|UNROLL)
diff --git a/hdl/arith/hazard5_priority_encode.v b/hdl/arith/hazard3_priority_encode.v
similarity index 95%
rename from hdl/arith/hazard5_priority_encode.v
rename to hdl/arith/hazard3_priority_encode.v
index 8c8177e..1aa0dc0 100644
--- a/hdl/arith/hazard5_priority_encode.v
+++ b/hdl/arith/hazard3_priority_encode.v
@@ -16,9 +16,9 @@
  *****************************************************************************/
 
 // Really something like this should be in a utility library (or the language!),
-// but Hazard5 is supposed to be self-contained
+// but Hazard3 is supposed to be self-contained
 
-module hazard5_priority_encode #(
+module hazard3_priority_encode #(
 	parameter W_REQ = 16,
 	parameter W_GNT = $clog2(W_REQ) // do not modify
 ) (
@@ -54,4 +54,4 @@ end
 
 assign gnt = gnt_accum;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hdl/arith/hazard5_shift_barrel.v b/hdl/arith/hazard3_shift_barrel.v
similarity index 98%
rename from hdl/arith/hazard5_shift_barrel.v
rename to hdl/arith/hazard3_shift_barrel.v
index 6813cbe..ef8bd7c 100644
--- a/hdl/arith/hazard5_shift_barrel.v
+++ b/hdl/arith/hazard3_shift_barrel.v
@@ -19,7 +19,7 @@
 // using a single log-type barrel shifter. Around 240 LUTs for 32 bits.
 // (7 layers of 32 2-input muxes, some extra LUTs and LUT inputs used for arith)
 
-module hazard5_shift_barrel #(
+module hazard3_shift_barrel #(
 	parameter W_DATA = 32,
 	parameter W_SHAMT = 5
 ) (
diff --git a/hdl/hazard3.f b/hdl/hazard3.f
new file mode 100644
index 0000000..762b93b
--- /dev/null
+++ b/hdl/hazard3.f
@@ -0,0 +1,14 @@
+file arith/hazard3_alu.v
+file arith/hazard3_shift_barrel.v
+file arith/hazard3_priority_encode.v
+file arith/hazard3_muldiv_seq.v
+file arith/hazard3_mul_fast.v
+file hazard3_frontend.v
+file hazard3_instr_decompress.v
+file hazard3_decode.v
+file hazard3_csr.v
+file hazard3_regfile_1w2r.v
+file hazard3_core.v
+file hazard3_cpu_1port.v
+file hazard3_cpu_2port.v
+include .
diff --git a/hdl/hazard5_config.vh b/hdl/hazard3_config.vh
similarity index 93%
rename from hdl/hazard5_config.vh
rename to hdl/hazard3_config.vh
index 4c7f989..7518e60 100644
--- a/hdl/hazard5_config.vh
+++ b/hdl/hazard3_config.vh
@@ -1,8 +1,8 @@
-// Hazard5 CPU configuration parameters
+// Hazard3 CPU configuration parameters
 
-// To configure Hazard5 you can either edit this file, or set parameters on
+// To configure Hazard3 you can either edit this file, or set parameters on
 // your top-level instantiation, it's up to you. These parameters are all
-// plumbed through Hazard5's internal hierarchy to the appropriate places.
+// plumbed through Hazard3's internal hierarchy to the appropriate places.
 
 // ----------------------------------------------------------------------------
 // Reset state configuration
diff --git a/hdl/hazard5_config_inst.vh b/hdl/hazard3_config_inst.vh
similarity index 89%
rename from hdl/hazard5_config_inst.vh
rename to hdl/hazard3_config_inst.vh
index 0d87c09..e290834 100644
--- a/hdl/hazard5_config_inst.vh
+++ b/hdl/hazard3_config_inst.vh
@@ -1,4 +1,4 @@
-// Pass-through of parameters defined in hazard5_config.vh, so that these can
+// Pass-through of parameters defined in hazard3_config.vh, so that these can
 // be set at instantiation rather than editing the config file, and will flow
 // correctly down through the hierarchy.
 
diff --git a/hdl/hazard5_core.v b/hdl/hazard3_core.v
similarity index 97%
rename from hdl/hazard5_core.v
rename to hdl/hazard3_core.v
index bc49722..9653ab9 100644
--- a/hdl/hazard5_core.v
+++ b/hdl/hazard3_core.v
@@ -15,10 +15,10 @@
  *                                                                    *
  *********************************************************************/
 
-module hazard5_core #(
-`include "hazard5_config.vh"
+module hazard3_core #(
+`include "hazard3_config.vh"
 ,
-`include "hazard5_width_const.vh"
+`include "hazard3_width_const.vh"
 ) (
 	// Global signals
 	input wire               clk,
@@ -55,7 +55,7 @@ module hazard5_core #(
 	input wire [15:0]        irq
 );
 
-`include "hazard5_ops.vh"
+`include "hazard3_ops.vh"
 
 `ifdef FORMAL
 // Only yosys-smtbmc seems to support immediate assertions
@@ -108,9 +108,9 @@ assign bus_aph_panic_i = m_jump_req;
 wire f_mem_size;
 assign bus_hsize_i = f_mem_size ? HSIZE_WORD : HSIZE_HWORD;
 
-hazard5_frontend #(
+hazard3_frontend #(
 	.FIFO_DEPTH(2),
-`include "hazard5_config_inst.vh"
+`include "hazard3_config_inst.vh"
 ) frontend (
 	.clk             (clk),
 	.rst_n           (rst_n),
@@ -183,9 +183,9 @@ wire                 dx_csr_wen;
 wire [1:0]           dx_csr_wtype;
 wire                 dx_csr_w_imm;
 
-hazard5_decode #(
-`include "hazard5_config_inst.vh"
-) inst_hazard5_decode (
+hazard3_decode #(
+`include "hazard3_config_inst.vh"
+) inst_hazard3_decode (
 	.clk                   (clk),
 	.rst_n                 (rst_n),
 
@@ -385,10 +385,10 @@ wire [W_DATA-1:0] x_csr_wdata = dx_csr_w_imm ?
 
 wire [W_DATA-1:0] x_csr_rdata;
 
-hazard5_csr #(
+hazard3_csr #(
 	.XLEN            (W_DATA),
-`include "hazard5_config_inst.vh"
-) inst_hazard5_csr (
+`include "hazard3_config_inst.vh"
+) inst_hazard3_csr (
 	.clk                     (clk),
 	.rst_n                   (rst_n),
 	// CSR access port
@@ -452,7 +452,7 @@ if (EXTENSION_M) begin: has_muldiv
 	assign x_muldiv_op_vld = (dx_aluop == ALUOP_MULDIV && !x_use_fast_mul)
 		&& !(x_muldiv_posted || x_stall_raw || x_muldiv_kill);
 
-	hazard5_muldiv_seq #(
+	hazard3_muldiv_seq #(
 		.XLEN   (W_DATA),
 		.UNROLL (MULDIV_UNROLL)
 	) muldiv (
@@ -484,9 +484,9 @@ if (EXTENSION_M) begin: has_muldiv
 
 		wire x_issue_fast_mul = x_use_fast_mul && |dx_rd && !(x_stall || flush_d_x);
 
-		hazard5_mul_fast #(
+		hazard3_mul_fast #(
 			.XLEN(W_DATA)
-		) inst_hazard5_mul_fast (
+		) inst_hazard3_mul_fast (
 			.clk        (clk),
 			.rst_n      (rst_n),
 
@@ -566,7 +566,7 @@ always @ (posedge clk)
 		xm_jump_target <= x_jump_target;
 	end
 
-hazard5_alu alu (
+hazard3_alu alu (
 	.aluop      (dx_aluop),
 	.op_a       (x_op_a),
 	.op_b       (x_op_b),
@@ -672,7 +672,7 @@ always @ (posedge clk) begin
 end
 //synthesis translate_on
 
-hazard5_regfile_1w2r #(
+hazard3_regfile_1w2r #(
 	.FAKE_DUALPORT(0),
 `ifdef SIM
 	.RESET_REGS(1),
@@ -699,12 +699,12 @@ hazard5_regfile_1w2r #(
 );
 
 `ifdef RISCV_FORMAL
-`include "hazard5_rvfi_monitor.vh"
+`include "hazard3_rvfi_monitor.vh"
 `endif
 
-`ifdef HAZARD5_FORMAL_REGRESSION
+`ifdef HAZARD3_FORMAL_REGRESSION
 // Each formal regression provides its own file with the below name:
-`include "hazard5_formal_regression.vh"
+`include "hazard3_formal_regression.vh"
 `endif
 
 endmodule
diff --git a/hdl/hazard5_cpu_1port.v b/hdl/hazard3_cpu_1port.v
similarity index 96%
rename from hdl/hazard5_cpu_1port.v
rename to hdl/hazard3_cpu_1port.v
index f07aed4..510840d 100644
--- a/hdl/hazard5_cpu_1port.v
+++ b/hdl/hazard3_cpu_1port.v
@@ -15,12 +15,12 @@
  *                                                                    *
  *********************************************************************/
 
-// Single-ported top level file for Hazard5 CPU. This file instantiates the
-// Hazard5 core, and arbitrates its instruction fetch and load/store signals
+// Single-ported top level file for Hazard3 CPU. This file instantiates the
+// Hazard3 core, and arbitrates its instruction fetch and load/store signals
 // down to a single AHB-Lite master port.
 
-module hazard5_cpu_1port #(
-`include "hazard5_config.vh"
+module hazard3_cpu_1port #(
+`include "hazard3_config.vh"
 ) (
 	// Global signals
 	input wire               clk,
@@ -75,8 +75,8 @@ wire [W_DATA-1:0] core_wdata_d;
 wire [W_DATA-1:0] core_rdata_d;
 
 
-hazard5_core #(
-`include "hazard5_config_inst.vh"
+hazard3_core #(
+`include "hazard3_config_inst.vh"
 ) core (
 	.clk             (clk),
 	.rst_n           (rst_n),
diff --git a/hdl/hazard5_cpu_2port.v b/hdl/hazard3_cpu_2port.v
similarity index 95%
rename from hdl/hazard5_cpu_2port.v
rename to hdl/hazard3_cpu_2port.v
index ac4e8c7..790b641 100644
--- a/hdl/hazard5_cpu_2port.v
+++ b/hdl/hazard3_cpu_2port.v
@@ -15,12 +15,12 @@
  *                                                                    *
  *********************************************************************/
 
-// Dual-ported top level file for Hazard5 CPU. This file instantiates the
-// Hazard5 core, and interfaces its instruction fetch and load/store signals
+// Dual-ported top level file for Hazard3 CPU. This file instantiates the
+// Hazard3 core, and interfaces its instruction fetch and load/store signals
 // to a pair of AHB-Lite master ports.
 
-module hazard5_cpu_2port #(
-`include "hazard5_config.vh"
+module hazard3_cpu_2port #(
+`include "hazard3_config.vh"
 ) (
 	// Global signals
 	input wire               clk,
@@ -88,8 +88,8 @@ wire [W_DATA-1:0] core_wdata_d;
 wire [W_DATA-1:0] core_rdata_d;
 
 
-hazard5_core #(
-`include "hazard5_config_inst.vh"
+hazard3_core #(
+`include "hazard3_config_inst.vh"
 ) core (
 	.clk             (clk),
 	.rst_n           (rst_n),
diff --git a/hdl/hazard5_csr.v b/hdl/hazard3_csr.v
similarity index 99%
rename from hdl/hazard5_csr.v
rename to hdl/hazard3_csr.v
index fa80bd0..9a6ca2a 100644
--- a/hdl/hazard5_csr.v
+++ b/hdl/hazard3_csr.v
@@ -19,12 +19,12 @@
 // Also includes CSR-related logic like interrupt enable/masking,
 // trap vector calculation.
 
-module hazard5_csr #(
+module hazard3_csr #(
 	parameter XLEN            = 32,   // Must be 32
 	parameter W_COUNTER       = 64,   // This *should* be 64, but can be reduced to save gates.
 	                                  // The full 64 bits is writeable, so high-word increment can
 	                                  // be implemented in software, and a narrower hw counter used
-`include "hazard5_config.vh"
+`include "hazard3_config.vh"
 ) (
 	input  wire            clk,
 	input  wire            rst_n,
@@ -88,7 +88,7 @@ module hazard5_csr #(
 
 // TODO block CSR access when entering trap?
 
-`include "hazard5_ops.vh"
+`include "hazard3_ops.vh"
 
 localparam X0 = {XLEN{1'b0}};
 
@@ -694,7 +694,7 @@ wire [15:0] exception_req = {
 wire exception_req_any = |exception_req && !in_trap;
 wire [3:0] exception_req_num;
 
-hazard5_priority_encode #(
+hazard3_priority_encode #(
 	.W_REQ(16)
 ) except_priority (
 	.req (exception_req),
@@ -727,7 +727,7 @@ wire [31:0] mip_no_global = mip & 32'hffff_f7ff;
 wire        irq_any = |(mip_no_global & {{16{mie_meie}}, {16{1'b1}}}) && mstatus_mie;
 wire [4:0]  irq_num;
 
-hazard5_priority_encode #(
+hazard3_priority_encode #(
 	.W_REQ(32)
 ) irq_priority (
 	.req (mip_no_global),
diff --git a/hdl/hazard5_decode.v b/hdl/hazard3_decode.v
similarity index 99%
rename from hdl/hazard5_decode.v
rename to hdl/hazard3_decode.v
index 60094a1..8cc2cbe 100644
--- a/hdl/hazard5_decode.v
+++ b/hdl/hazard3_decode.v
@@ -15,10 +15,10 @@
  *                                                                            *
  *****************************************************************************/
 
-module hazard5_decode #(
-`include "hazard5_config.vh"
+module hazard3_decode #(
+`include "hazard3_config.vh"
 ,
-`include "hazard5_width_const.vh"
+`include "hazard3_width_const.vh"
 ) (
 	input wire clk,
 	input wire rst_n,
@@ -64,7 +64,7 @@ module hazard5_decode #(
 );
 
 `include "rv_opcodes.vh"
-`include "hazard5_ops.vh"
+`include "hazard3_ops.vh"
 
 localparam HAVE_CSR = CSR_M_MANDATORY || CSR_M_TRAP || CSR_COUNTER;
 
@@ -77,7 +77,7 @@ wire        d_invalid_16bit;
 reg         d_invalid_32bit;
 wire        d_invalid = d_invalid_16bit || d_invalid_32bit;
 
-hazard5_instr_decompress #(
+hazard3_instr_decompress #(
 	.PASSTHROUGH(!EXTENSION_C)
 ) decomp (
 	.instr_in       (fd_cir),
diff --git a/hdl/hazard5_frontend.v b/hdl/hazard3_frontend.v
similarity index 95%
rename from hdl/hazard5_frontend.v
rename to hdl/hazard3_frontend.v
index 459dd37..bf8fc5d 100644
--- a/hdl/hazard5_frontend.v
+++ b/hdl/hazard3_frontend.v
@@ -1,6 +1,6 @@
-module hazard5_frontend #(
+module hazard3_frontend #(
 	parameter FIFO_DEPTH = 2,  // power of 2, >= 1
-`include "hazard5_config.vh"
+`include "hazard3_config.vh"
 ) (
 	input wire clk,
 	input wire rst_n,
@@ -44,8 +44,8 @@ module hazard5_frontend #(
 );
 
 `undef ASSERT
-`ifdef HAZARD5_FRONTEND_ASSERTIONS
-`define ASSERT(x) assert(x)
+`ifdef HAZARD3_FRONTEND_ASSERTIONS
+`define ASSERT(x) assert(x);
 `else
 `define ASSERT(x)
 `endif
@@ -126,10 +126,10 @@ always @ (posedge clk or negedge rst_n) begin
 		pending_fetches <= 2'h0;
 		ctr_flush_pending <= 2'h0;
 	end else begin
-		`ASSERT(ctr_flush_pending <= pending_fetches);
-		`ASSERT(pending_fetches < 2'd3);
-		`ASSERT(!(mem_data_vld && !pending_fetches));
-		// `ASSERT(!($past(mem_addr_hold) && $past(mem_addr_vld) && !$stable(mem_addr)));
+		`ASSERT(ctr_flush_pending <= pending_fetches)
+		`ASSERT(pending_fetches < 2'd3)
+		`ASSERT(!(mem_data_vld && !pending_fetches))
+		// `ASSERT(!($past(mem_addr_hold) && $past(mem_addr_vld) && !$stable(mem_addr)))
 		mem_addr_hold <= mem_addr_vld && !mem_addr_rdy;
 		pending_fetches <= pending_fetches_next;
 		if (jump_now) begin
@@ -177,9 +177,9 @@ always @ (posedge clk or negedge rst_n) begin
 		unaligned_jump_aph <= 1'b0;
 		unaligned_jump_dph <= 1'b0;
 	end else if (EXTENSION_C) begin
-		`ASSERT(!(unaligned_jump_aph && !unaligned_jump_dph));
-		`ASSERT(!($past(jump_now && !jump_target[1]) && unaligned_jump_aph));
-		`ASSERT(!($past(jump_now && !jump_target[1]) && unaligned_jump_dph));
+		`ASSERT(!(unaligned_jump_aph && !unaligned_jump_dph))
+		`ASSERT(!($past(jump_now && !jump_target[1]) && unaligned_jump_aph))
+		`ASSERT(!($past(jump_now && !jump_target[1]) && unaligned_jump_dph))
 		if (mem_addr_rdy || (jump_now && !unaligned_jump_now)) begin
 			unaligned_jump_aph <= 1'b0;
 		end
@@ -281,10 +281,10 @@ always @ (posedge clk or negedge rst_n) begin
 		hwbuf_vld <= 1'b0;
 		cir_vld <= 2'h0;
 	end else begin
-		`ASSERT(cir_vld <= 2);
-		`ASSERT(cir_use <= 2);
-		`ASSERT(cir_use <= cir_vld);
-		`ASSERT(cir_vld <= buf_level || $past(cir_lock));
+		`ASSERT(cir_vld <= 2)
+		`ASSERT(cir_use <= 2)
+		`ASSERT(cir_use <= cir_vld)
+		`ASSERT(cir_vld <= buf_level || $past(cir_lock))
 		// Update CIR flags
 		buf_level <= buf_level_next;
 		hwbuf_vld <= &buf_level_next;
diff --git a/hdl/hazard5_instr_decompress.v b/hdl/hazard3_instr_decompress.v
similarity index 99%
rename from hdl/hazard5_instr_decompress.v
rename to hdl/hazard3_instr_decompress.v
index 4567ef5..24a1cb2 100644
--- a/hdl/hazard5_instr_decompress.v
+++ b/hdl/hazard3_instr_decompress.v
@@ -1,4 +1,4 @@
-module hazard5_instr_decompress #(
+module hazard3_instr_decompress #(
 	parameter PASSTHROUGH = 0
 ) (
 	input wire [31:0] instr_in,
@@ -111,4 +111,4 @@ end else begin
 end
 endgenerate
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hdl/hazard5_ops.vh b/hdl/hazard3_ops.vh
similarity index 100%
rename from hdl/hazard5_ops.vh
rename to hdl/hazard3_ops.vh
diff --git a/hdl/hazard5_regfile_1w2r.v b/hdl/hazard3_regfile_1w2r.v
similarity index 98%
rename from hdl/hazard5_regfile_1w2r.v
rename to hdl/hazard3_regfile_1w2r.v
index 2eb03eb..986064e 100644
--- a/hdl/hazard5_regfile_1w2r.v
+++ b/hdl/hazard3_regfile_1w2r.v
@@ -23,7 +23,7 @@
 // This allows BRAM inference on FPGAs with single-read-port BRAMs.
 // (Looking at you iCE40)
 
-module hazard5_regfile_1w2r #(
+module hazard3_regfile_1w2r #(
 	parameter FAKE_DUALPORT = 0,
 	parameter RESET_REGS = 0,	// Unsupported for FAKE_DUALPORT
 	parameter N_REGS = 16,
@@ -92,4 +92,4 @@ end else begin: real_dualport_noreset
 end
 endgenerate
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/hdl/hazard5_rvfi_monitor.vh b/hdl/hazard3_rvfi_monitor.vh
similarity index 98%
rename from hdl/hazard5_rvfi_monitor.vh
rename to hdl/hazard3_rvfi_monitor.vh
index 0613acc..50d11b5 100644
--- a/hdl/hazard5_rvfi_monitor.vh
+++ b/hdl/hazard3_rvfi_monitor.vh
@@ -1,7 +1,7 @@
 // ----------------------------------------------------------------------------
 // RVFI Instrumentation
 // ----------------------------------------------------------------------------
-// To be included into hazard5_cpu.v for use with riscv-formal.
+// To be included into hazard3_cpu.v for use with riscv-formal.
 // Contains some state modelling to diagnose exactly what the core is doing,
 // and report this in a way RVFI understands.
 // We consider instructions to "retire" as they cross the M/W pipe register.
@@ -77,7 +77,7 @@ always @ (posedge clk or negedge rst_n) begin
 	end
 end
 
-// Hazard5 is an in-order core:
+// Hazard3 is an in-order core:
 reg [63:0] rvfm_retire_ctr;
 assign rvfi_order = rvfm_retire_ctr;
 always @ (posedge clk or negedge rst_n)
diff --git a/hdl/hazard5_rvfi_wrapper.v b/hdl/hazard3_rvfi_wrapper.v
similarity index 99%
rename from hdl/hazard5_rvfi_wrapper.v
rename to hdl/hazard3_rvfi_wrapper.v
index 849f41b..0691b91 100644
--- a/hdl/hazard5_rvfi_wrapper.v
+++ b/hdl/hazard3_rvfi_wrapper.v
@@ -50,7 +50,7 @@ end
 // Device Under Test
 // ----------------------------------------------------------------------------
 
-hazard5_cpu #(
+hazard3_cpu #(
 	.RESET_VECTOR (0),
 	.EXTENSION_C  (1),
 	.EXTENSION_M  (1)
diff --git a/hdl/hazard5_width_const.vh b/hdl/hazard3_width_const.vh
similarity index 100%
rename from hdl/hazard5_width_const.vh
rename to hdl/hazard3_width_const.vh
diff --git a/hdl/hazard5.f b/hdl/hazard5.f
deleted file mode 100644
index 10cb99f..0000000
--- a/hdl/hazard5.f
+++ /dev/null
@@ -1,14 +0,0 @@
-file arith/hazard5_alu.v
-file arith/hazard5_shift_barrel.v
-file arith/hazard5_priority_encode.v
-file arith/hazard5_muldiv_seq.v
-file arith/hazard5_mul_fast.v
-file hazard5_frontend.v
-file hazard5_instr_decompress.v
-file hazard5_decode.v
-file hazard5_csr.v
-file hazard5_regfile_1w2r.v
-file hazard5_core.v
-file hazard5_cpu_1port.v
-file hazard5_cpu_2port.v
-include .
diff --git a/test/tb_cxxrtl/Makefile b/test/tb_cxxrtl/Makefile
index 59a8e2f..e730ff8 100644
--- a/test/tb_cxxrtl/Makefile
+++ b/test/tb_cxxrtl/Makefile
@@ -1,4 +1,4 @@
-TOP              := hazard5_cpu_2port
+TOP              := hazard3_cpu_2port
 CDEFINES         := DUAL_PORT
 
 CPU_RESET_VECTOR := 32'hc0
@@ -12,7 +12,7 @@ REDUCED_BYPASS   := 0
 
 all: tb
 
-SYNTH_CMD += read_verilog -I ../../hdl $(shell listfiles ../../hdl/hazard5.f);
+SYNTH_CMD += read_verilog -I ../../hdl $(shell listfiles ../../hdl/hazard3.f);
 SYNTH_CMD += chparam -set EXTENSION_C $(EXTENSION_C) $(TOP);
 SYNTH_CMD += chparam -set EXTENSION_M $(EXTENSION_M) $(TOP);
 SYNTH_CMD += chparam -set CSR_COUNTER 1 $(TOP);
diff --git a/test/tb_cxxrtl/tb.cpp b/test/tb_cxxrtl/tb.cpp
index 4d16060..efb2fd6 100644
--- a/test/tb_cxxrtl/tb.cpp
+++ b/test/tb_cxxrtl/tb.cpp
@@ -73,9 +73,9 @@ int main(int argc, char **argv) {
 	}
 
 #ifdef DUAL_PORT
-	cxxrtl_design::p_hazard5__cpu__2port top;
+	cxxrtl_design::p_hazard3__cpu__2port top;
 #else
-	cxxrtl_design::p_hazard5__cpu__1port top;
+	cxxrtl_design::p_hazard3__cpu__1port top;
 #endif
 
 	std::fill(std::begin(mem), std::end(mem), 0);
@@ -140,7 +140,7 @@ int main(int argc, char **argv) {
 #endif
 			if (bus_addr <= MEM_SIZE) {
 				unsigned int n_bytes = 1u << bus_size;
-				// Note we are relying on hazard5's byte lane replication
+				// Note we are relying on hazard3's byte lane replication
 				for (unsigned int i = 0; i < n_bytes; ++i) {
 					mem[bus_addr + i] = wdata >> (8 * i) & 0xffu;
 				}