diff --git a/hdl/hazard3_config.vh b/hdl/hazard3_config.vh index c102971..17da5b4 100644 --- a/hdl/hazard3_config.vh +++ b/hdl/hazard3_config.vh @@ -17,21 +17,18 @@ // Reset state configuration // RESET_VECTOR: Address of first instruction executed. -parameter RESET_VECTOR = 32'h0, +parameter RESET_VECTOR = 32'h00000000, // MTVEC_INIT: Initial value of trap vector base. Bits clear in MTVEC_WMASK // will never change from this initial value. Bits set in MTVEC_WMASK can be // written/set/cleared as normal. // -// Note that, if CSR_M_TRAP is set, MTVEC_INIT should probably have a -// different value from RESET_VECTOR. -// // Note that mtvec bits 1:0 do not affect the trap base (as per RISC-V spec). // Bit 1 is don't care, bit 0 selects the vectoring mode: unvectored if == 0 // (all traps go to mtvec), vectored if == 1 (exceptions go to mtvec, IRQs to // mtvec + mcause * 4). This means MTVEC_INIT also sets the initial vectoring // mode. -parameter MTVEC_INIT = 32'h00000000, +parameter MTVEC_INIT = 32'h00000000, // ---------------------------------------------------------------------------- // Standard RISC-V ISA support diff --git a/test/sim/tb_cxxrtl/Makefile b/test/sim/tb_cxxrtl/Makefile index 5106dd9..299564a 100644 --- a/test/sim/tb_cxxrtl/Makefile +++ b/test/sim/tb_cxxrtl/Makefile @@ -1,67 +1,17 @@ -TOP := tb -DOTF := tb.f - -CPU_RESET_VECTOR := 32'h40 - -EXTENSION_C := 1 -EXTENSION_M := 1 -EXTENSION_ZBA := 1 -EXTENSION_ZBB := 1 -EXTENSION_ZBC := 1 -EXTENSION_ZBS := 1 - -DEBUG_SUPPORT := 1 -BREAKPOINT_TRIGGERS := 4 -U_MODE := 1 -PMP_REGIONS := 4 - -NUM_IRQS := 32 -IRQ_PRIORITY_BITS := 4 - -MULDIV_UNROLL := 2 -MUL_FAST := 1 -MUL_FASTER := 1 -MULH_FAST := 1 -FAST_BRANCHCMP := 1 -REDUCED_BYPASS := 0 - -MVENDORID_VAL := 32'hdeadbeef -MIMPID_VAL := 32'h12345678 -MCONFIGPTR_VAL := 32'h9abcdef0 +TOP := tb +DOTF := tb.f +CONFIG := default .PHONY: clean all all: tb -SYNTH_CMD += read_verilog -I ../../../hdl $(shell listfiles $(DOTF)); -SYNTH_CMD += chparam -set EXTENSION_C $(EXTENSION_C) $(TOP); -SYNTH_CMD += chparam -set EXTENSION_M $(EXTENSION_M) $(TOP); -SYNTH_CMD += chparam -set EXTENSION_ZBA $(EXTENSION_ZBA) $(TOP); -SYNTH_CMD += chparam -set EXTENSION_ZBB $(EXTENSION_ZBB) $(TOP); -SYNTH_CMD += chparam -set EXTENSION_ZBC $(EXTENSION_ZBC) $(TOP); -SYNTH_CMD += chparam -set EXTENSION_ZBS $(EXTENSION_ZBS) $(TOP); -SYNTH_CMD += chparam -set DEBUG_SUPPORT $(DEBUG_SUPPORT) $(TOP); -SYNTH_CMD += chparam -set BREAKPOINT_TRIGGERS $(BREAKPOINT_TRIGGERS) $(TOP); -SYNTH_CMD += chparam -set U_MODE $(U_MODE) $(TOP); -SYNTH_CMD += chparam -set PMP_REGIONS $(PMP_REGIONS) $(TOP); -SYNTH_CMD += chparam -set NUM_IRQS $(NUM_IRQS) $(TOP); -SYNTH_CMD += chparam -set IRQ_PRIORITY_BITS $(IRQ_PRIORITY_BITS) $(TOP); -SYNTH_CMD += chparam -set CSR_COUNTER 1 $(TOP); -SYNTH_CMD += chparam -set RESET_VECTOR $(CPU_RESET_VECTOR) $(TOP); -SYNTH_CMD += chparam -set REDUCED_BYPASS $(REDUCED_BYPASS) $(TOP); -SYNTH_CMD += chparam -set MULDIV_UNROLL $(MULDIV_UNROLL) $(TOP); -SYNTH_CMD += chparam -set MUL_FAST $(MUL_FAST) $(TOP); -SYNTH_CMD += chparam -set MUL_FASTER $(MUL_FASTER) $(TOP); -SYNTH_CMD += chparam -set MULH_FAST $(MULH_FAST) $(TOP); -SYNTH_CMD += chparam -set FAST_BRANCHCMP $(FAST_BRANCHCMP) $(TOP); -SYNTH_CMD += chparam -set MVENDORID_VAL $(MVENDORID_VAL) $(TOP); -SYNTH_CMD += chparam -set MIMPID_VAL $(MIMPID_VAL) $(TOP); -SYNTH_CMD += chparam -set MCONFIGPTR_VAL $(MCONFIGPTR_VAL) $(TOP); +SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(shell listfiles $(DOTF)); SYNTH_CMD += hierarchy -top $(TOP); SYNTH_CMD += write_cxxrtl dut.cpp dut.cpp: $(shell listfiles $(DOTF)) - yosys -p "$(SYNTH_CMD)" 2>&1 > cxxrtl.log + yosys -p '$(SYNTH_CMD)' 2>&1 > cxxrtl.log clean:: rm -f dut.cpp cxxrtl.log tb diff --git a/test/sim/tb_cxxrtl/config_default.vh b/test/sim/tb_cxxrtl/config_default.vh new file mode 100644 index 0000000..ef1283e --- /dev/null +++ b/test/sim/tb_cxxrtl/config_default.vh @@ -0,0 +1,44 @@ +// Default Hazard3 config for testbench: all ISA features + +localparam RESET_VECTOR = 32'h40; +localparam MTVEC_INIT = 32'h0; +localparam EXTENSION_A = 1; +localparam EXTENSION_C = 1; +localparam EXTENSION_M = 1; +localparam EXTENSION_ZBA = 1; +localparam EXTENSION_ZBB = 1; +localparam EXTENSION_ZBC = 1; +localparam EXTENSION_ZBS = 1; +localparam EXTENSION_ZBKB = 1; +localparam EXTENSION_ZIFENCEI = 1; +localparam EXTENSION_XH3BEXTM = 1; +localparam EXTENSION_XH3IRQ = 1; +localparam EXTENSION_XH3PMPM = 1; +localparam EXTENSION_XH3POWER = 1; +localparam CSR_M_MANDATORY = 1; +localparam CSR_M_TRAP = 1; +localparam CSR_COUNTER = 1; +localparam U_MODE = 1; +localparam PMP_REGIONS = 4; +localparam PMP_GRAIN = 0; +localparam PMP_HARDWIRED = {PMP_REGIONS{1'b0}}; +localparam PMP_HARDWIRED_ADDR = {PMP_REGIONS{32'h0}}; +localparam PMP_HARDWIRED_CFG = {PMP_REGIONS{8'h00}}; +localparam DEBUG_SUPPORT = 1; +localparam BREAKPOINT_TRIGGERS = 4; +localparam NUM_IRQS = 32; +localparam IRQ_PRIORITY_BITS = 4; +localparam IRQ_INPUT_BYPASS = {NUM_IRQS{1'b0}}; +localparam MVENDORID_VAL = 32'hdeadbeef; +localparam MIMPID_VAL = 32'h12345678; +localparam MHARTID_VAL = 32'h9abcdef0; +localparam MCONFIGPTR_VAL = 32'h0; +localparam REDUCED_BYPASS = 0; +localparam MULDIV_UNROLL = 2; +localparam MUL_FAST = 1; +localparam MUL_FASTER = 1; +localparam MULH_FAST = 1; +localparam FAST_BRANCHCMP = 1; +localparam RESET_REGFILE = 1; +localparam BRANCH_PREDICTOR = 1; +localparam MTVEC_WMASK = 32'hfffffffd; diff --git a/test/sim/tb_cxxrtl/config_min.vh b/test/sim/tb_cxxrtl/config_min.vh new file mode 100644 index 0000000..1537bda --- /dev/null +++ b/test/sim/tb_cxxrtl/config_min.vh @@ -0,0 +1,44 @@ +// Minimal Hazard3 config for testbench + +localparam RESET_VECTOR = 32'h40; +localparam MTVEC_INIT = 32'h0; +localparam EXTENSION_A = 0; +localparam EXTENSION_C = 0; +localparam EXTENSION_M = 0; +localparam EXTENSION_ZBA = 0; +localparam EXTENSION_ZBB = 0; +localparam EXTENSION_ZBC = 0; +localparam EXTENSION_ZBS = 0; +localparam EXTENSION_ZBKB = 0; +localparam EXTENSION_ZIFENCEI = 0; +localparam EXTENSION_XH3BEXTM = 0; +localparam EXTENSION_XH3IRQ = 0; +localparam EXTENSION_XH3PMPM = 0; +localparam EXTENSION_XH3POWER = 0; +localparam CSR_M_MANDATORY = 1; +localparam CSR_M_TRAP = 1; +localparam CSR_COUNTER = 0; +localparam U_MODE = 0; +localparam PMP_REGIONS = 0; +localparam PMP_GRAIN = 0; +localparam PMP_HARDWIRED = {PMP_REGIONS{1'b0}}; +localparam PMP_HARDWIRED_ADDR = {PMP_REGIONS{32'h0}}; +localparam PMP_HARDWIRED_CFG = {PMP_REGIONS{8'h00}}; +localparam DEBUG_SUPPORT = 0; +localparam BREAKPOINT_TRIGGERS = 4; +localparam NUM_IRQS = 32; +localparam IRQ_PRIORITY_BITS = 0; +localparam IRQ_INPUT_BYPASS = {NUM_IRQS{1'b0}}; +localparam MVENDORID_VAL = 32'hdeadbeef; +localparam MIMPID_VAL = 32'h12345678; +localparam MHARTID_VAL = 32'h9abcdef0; +localparam MCONFIGPTR_VAL = 32'h0; +localparam REDUCED_BYPASS = 1; +localparam MULDIV_UNROLL = 1; +localparam MUL_FAST = 0; +localparam MUL_FASTER = 0; +localparam MULH_FAST = 0; +localparam FAST_BRANCHCMP = 0; +localparam RESET_REGFILE = 1; +localparam BRANCH_PREDICTOR = 0; +localparam MTVEC_WMASK = 32'hfffffffd; diff --git a/test/sim/tb_cxxrtl/tb.v b/test/sim/tb_cxxrtl/tb.v index 70b6e57..872fb12 100644 --- a/test/sim/tb_cxxrtl/tb.v +++ b/test/sim/tb_cxxrtl/tb.v @@ -4,7 +4,8 @@ `default_nettype none module tb #( -`include "hazard3_config.vh" + parameter W_DATA = 32, // do not modify + parameter W_ADDR = 32 // do not modify ) ( // Global signals input wire clk, @@ -231,6 +232,11 @@ end // clk_gated = clk; // end +`ifndef CONFIG_HEADER +`define CONFIG_HEADER "config_default.vh" +`endif +`include `CONFIG_HEADER + hazard3_cpu_2port #( `include "hazard3_config_inst.vh" ) cpu ( diff --git a/test/sim/tb_cxxrtl/tb_multicore.v b/test/sim/tb_cxxrtl/tb_multicore.v index 49aefb1..38ba370 100644 --- a/test/sim/tb_cxxrtl/tb_multicore.v +++ b/test/sim/tb_cxxrtl/tb_multicore.v @@ -4,7 +4,8 @@ `default_nettype none module tb #( -`include "hazard3_config.vh" + parameter W_ADDR = 32, // do not modify + parameter W_DATA = 32 // do not modify ) ( // Global signals input wire clk, @@ -209,6 +210,11 @@ hazard3_reset_sync cpu1_reset_sync ( assign sys_reset_done = rst_n_cpu0 && rst_n_cpu1; assign hart_reset_done = {rst_n_cpu1, rst_n_cpu0}; +`ifndef CONFIG_HEADER +`define CONFIG_HEADER "config_default.vh" +`endif +`include `CONFIG_HEADER + hazard3_cpu_1port #( .MHARTID_VAL (32'h0000_0000), `define HAZARD3_CONFIG_INST_NO_MHARTID