Make mcycle/minstret inhibited by default

doc/sections/csr.adoc

@@ -310,8 +310,8 @@ Counter inhibit. Read-write. The table below lists the fields which are _not_ ha
 [cols="10h,20h,~", options="header"]
 |===
 | Bits | Name | Description
-| 2 | `ir` | When 1, inhibit counting of `minstret`/`minstreth`
-| 0 | `cy` | When 1, inhibit counting of `mcycle`/`mcycleh`
+| 2 | `ir` | When 1, inhibit counting of `minstret`/`minstreth`. Resets to 1.
+| 0 | `cy` | When 1, inhibit counting of `mcycle`/`mcycleh`. Resets to 1.
 |===
 
 ==== mhpmevent3...31

hdl/hazard3_csr.v

@@ -440,8 +440,8 @@ always @ (posedge clk or negedge rst_n) begin
 		minstreth <= X0;
 		minstret <= X0;
 		// Counters inhibited by default to save energy
-		mcountinhibit_cy <= 1'b0;
-		mcountinhibit_ir <= 1'b0;
+		mcountinhibit_cy <= 1'b1;
+		mcountinhibit_ir <= 1'b1;
 	end else if (CSR_COUNTER) begin
 		// Optionally hold the top (2 * XLEN - W_COUNTER) bits constant to
 		// save gates (noncompliant if enabled)

test/sim/common/init.S

@@ -54,11 +54,20 @@ j \name
 
 
 .reset_handler:
-	la sp, __stack_top
-	// mtvec LSB enables vectoring
+	// Set counters running, as they are off by default. This may trap if counters
+	// are unimplemented, so catch the trap and continue.
+	la a0, 1f
+	csrw mtvec, a0
+	csrci mcountinhibit, 0x5
+.p2align 2
+1:
+	// Set up trap vector table. mtvec LSB enables vectoring
 	la t0, .vector_table + 1
 	csrw mtvec, t0
 
+	// Set up stack pointer before doing anything else
+	la sp, __stack_top
+
 	// newlib _start expects argc, argv on the stack. Leave stack 16-byte aligned.
 	addi sp, sp, -16
 	li a0, 1