Couple more silly mistakes
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@ -49,9 +49,9 @@ wire sub = !(aluop == ALUOP_ADD || (|EXTENSION_ZBA && (
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aluop == ALUOP_SH1ADD || aluop == ALUOP_SH2ADD || aluop == ALUOP_SH3ADD
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)));
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wire inv_op_b = sub || (|EXTENSION_ZBB && (
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aluop == ALUOP_ANDN || aluop == ALUOP_ORN || aluop == ALUOP_XNOR
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));
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wire inv_op_b = sub && !(
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aluop == ALUOP_AND || aluop == ALUOP_OR || aluop == ALUOP_XOR
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);
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wire [W_DATA-1:0] op_a_shifted =
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|EXTENSION_ZBA && aluop == ALUOP_SH1ADD ? op_a << 1 :
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@ -158,7 +158,7 @@ end
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wire [W_DATA-1:0] zbs_mask = {{W_DATA-1{1'b0}}, 1'b1} << op_b[W_SHAMT-1:0];
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always @ (*) begin
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casez ({|EXTENSION_ZBA, |EXTENSION_ZBB, EXTENSION_ZBC, |EXTENSION_ZBS, aluop})
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casez ({|EXTENSION_ZBA, |EXTENSION_ZBB, |EXTENSION_ZBC, |EXTENSION_ZBS, aluop})
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// Base ISA
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{4'bzzzz, ALUOP_ADD }: result = sum;
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{4'bzzzz, ALUOP_SUB }: result = sum;
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@ -176,9 +176,9 @@ always @ (*) begin
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{4'bz1zz, ALUOP_ANDN }: result = bitwise;
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{4'bz1zz, ALUOP_ORN }: result = bitwise;
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{4'bz1zz, ALUOP_XNOR }: result = bitwise;
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{4'bz1zz, ALUOP_CLZ }: result = ctz_clz;
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{4'bz1zz, ALUOP_CTZ }: result = ctz_clz;
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{4'bz1zz, ALUOP_CPOP }: result = cpop;
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{4'bz1zz, ALUOP_CLZ }: result = {{W_DATA-W_SHAMT-1{1'b0}}, ctz_clz};
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{4'bz1zz, ALUOP_CTZ }: result = {{W_DATA-W_SHAMT-1{1'b0}}, ctz_clz};
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{4'bz1zz, ALUOP_CPOP }: result = {{W_DATA-W_SHAMT-1{1'b0}}, cpop};
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{4'bz1zz, ALUOP_MAX }: result = lt ? op_b : op_a;
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{4'bz1zz, ALUOP_MAXU }: result = lt ? op_b : op_a;
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{4'bz1zz, ALUOP_MIN }: result = lt ? op_a : op_b;
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