rvcpp: fix busted RMW CSR logic, fix ordering of CSR write vs update, csr_mcycle testcase now passes
This commit is contained in:
Luke Wren
parent
55504fa8f3
commit
8cbf5fceee
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@ -18,6 +18,11 @@
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// - M
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// - A
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// - C (also called Zca)
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// - Zba
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// - Zbb
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// - Zbc
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// - Zbs
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// - Zbkb
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// - Zcmp
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// - M-mode traps
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@ -158,7 +163,8 @@ class RVCSR {
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ux_t mepc;
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ux_t mcause;
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std::optional<ux_t> addr_written_this_step;
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std::optional<ux_t> pending_write_addr;
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ux_t pending_write_data;
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public:
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@ -182,7 +188,7 @@ public:
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mscratch = 0;
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mepc = 0;
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mcause = 0;
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addr_written_this_step = {};
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pending_write_addr = {};
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}
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void step() {
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@ -194,19 +200,36 @@ public:
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if (!(mcountinhibit & 0x4u)) {
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++minstret_64;
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}
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if (!(addr_written_this_step && *addr_written_this_step == CSR_MCYCLEH)) {
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if (!(pending_write_addr && *pending_write_addr == CSR_MCYCLEH)) {
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mcycleh = mcycle_64 >> 32;
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}
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if (!(addr_written_this_step && *addr_written_this_step == CSR_MCYCLE)) {
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if (!(pending_write_addr && *pending_write_addr == CSR_MCYCLE)) {
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mcycle = mcycle_64 & 0xffffffffu;
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}
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if (!(addr_written_this_step && *addr_written_this_step == CSR_MINSTRETH)) {
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if (!(pending_write_addr && *pending_write_addr == CSR_MINSTRETH)) {
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minstreth = minstret_64 >> 32;
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}
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if (!(addr_written_this_step && *addr_written_this_step == CSR_MINSTRET)) {
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if (!(pending_write_addr && *pending_write_addr == CSR_MINSTRET)) {
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minstret = minstret_64 & 0xffffffffu;
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}
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addr_written_this_step = {};
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if (pending_write_addr) {
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switch (*pending_write_addr) {
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case CSR_MSTATUS: mstatus = pending_write_data; break;
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case CSR_MIE: mie = pending_write_data; break;
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case CSR_MTVEC: mtvec = pending_write_data & 0xfffffffdu; break;
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case CSR_MSCRATCH: mscratch = pending_write_data; break;
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case CSR_MEPC: mepc = pending_write_data & 0xfffffffeu; break;
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case CSR_MCAUSE: mcause = pending_write_data & 0x8000000fu; break;
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case CSR_MCYCLE: mcycle = pending_write_data; break;
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case CSR_MCYCLEH: mcycleh = pending_write_data; break;
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case CSR_MINSTRET: minstret = pending_write_data; break;
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case CSR_MINSTRETH: minstreth = pending_write_data; break;
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case CSR_MCOUNTINHIBIT: mcountinhibit = pending_write_data & 0x7u; break;
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default: break;
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}
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pending_write_addr = {};
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}
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}
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// Returns None on permission/decode fail
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@ -243,41 +266,43 @@ public:
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// Returns false on permission/decode fail
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bool write(uint16_t addr, ux_t data, uint op=WRITE) {
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addr_written_this_step = addr;
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if (addr >= 1u << 12 || GETBITS(addr, 9, 8) > priv)
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return false;
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if (addr >= 1u << 12)
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if (op == WRITE_CLEAR || op == WRITE_SET) {
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std::optional<ux_t> rdata = read(addr, false);
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if (!rdata)
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return false;
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if (op == WRITE_CLEAR)
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data &= ~*rdata;
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data = *rdata & ~data;
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else
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data |= *rdata;
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data = *rdata | data;
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}
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pending_write_addr = addr;
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pending_write_data = data;
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// Actual write is applied at end of step() -- ordering is important
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// e.g. for mcycle updates. However we validate address for
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// writability immediately.
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switch (addr) {
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case CSR_MISA: break;
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case CSR_MHARTID: break;
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case CSR_MARCHID: break;
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case CSR_MIMPID: break;
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case CSR_MISA: break;
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case CSR_MHARTID: break;
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case CSR_MARCHID: break;
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case CSR_MIMPID: break;
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case CSR_MSTATUS: mstatus = data; break;
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case CSR_MIE: mie = data; break;
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case CSR_MIP: break;
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case CSR_MTVEC: mtvec = data & 0xfffffffdu; break;
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case CSR_MSCRATCH: mscratch = data; break;
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case CSR_MEPC: mepc = data & 0xfffffffeu; break;
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case CSR_MCAUSE: mcause = data & 0x8000000fu; break;
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case CSR_MTVAL: break;
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case CSR_MSTATUS: break;
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case CSR_MIE: break;
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case CSR_MIP: break;
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case CSR_MTVEC: break;
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case CSR_MSCRATCH: break;
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case CSR_MEPC: break;
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case CSR_MCAUSE: break;
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case CSR_MTVAL: break;
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case CSR_MCYCLE: mcycle = data; break;
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case CSR_MCYCLEH: mcycleh = data; break;
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case CSR_MINSTRET: minstret = data; break;
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case CSR_MINSTRETH: minstreth = data; break;
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case CSR_MCOUNTINHIBIT: mcountinhibit = data & 0x7u; break;
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default: return false;
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case CSR_MCYCLE: break;
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case CSR_MCYCLEH: break;
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case CSR_MINSTRET: break;
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case CSR_MINSTRETH: break;
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case CSR_MCOUNTINHIBIT: break;
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default: return false;
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}
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return true;
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}
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@ -45,14 +45,9 @@ int main() {
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asm volatile (
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".p2align 2\n"
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" csrw mcycle, zero\n"
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" j 1f\n" // 2 cycles each
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"1:\n"
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" j 1f\n"
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"1:\n"
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" j 1f\n"
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"1:\n"
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" j 1f\n"
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"1:\n"
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".rept 8\n"
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" nop\n"
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".endr\n"
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" csrr %0, mcycle\n"
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: "=r" (tmp0)
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);
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