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Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends

This commit is contained in:
Luke Wren 2021-07-20 00:12:55 +01:00
parent 7d24f42da9
commit 8cdde82248
2 changed files with 4 additions and 10 deletions
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10
hdl/arith/hazard3_alu.v
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@ -48,8 +48,8 @@ assign result_add = sum;
wire [W_DATA-1:0] shift_dout; wire [W_DATA-1:0] shift_dout;
reg shift_right_nleft; wire shift_right_nleft = aluop == ALUOP_SRL || aluop == ALUOP_SRA;
reg shift_arith; wire shift_arith = aluop == ALUOP_SRA;
hazard3_shift_barrel #( hazard3_shift_barrel #(
.W_DATA(W_DATA), .W_DATA(W_DATA),
@ -76,15 +76,13 @@ always @ (*) begin: bitwise_ops
end end
always @ (*) begin always @ (*) begin
shift_right_nleft = 1'b0;
shift_arith = 1'b0;
case (aluop) case (aluop)
ALUOP_ADD: begin result = sum; end ALUOP_ADD: begin result = sum; end
ALUOP_SUB: begin result = sum; end ALUOP_SUB: begin result = sum; end
ALUOP_LT: begin result = {{W_DATA-1{1'b0}}, lt}; end ALUOP_LT: begin result = {{W_DATA-1{1'b0}}, lt}; end
ALUOP_LTU: begin result = {{W_DATA-1{1'b0}}, lt}; end ALUOP_LTU: begin result = {{W_DATA-1{1'b0}}, lt}; end
ALUOP_SRL: begin shift_right_nleft = 1'b1; result = shift_dout; end ALUOP_SRL: begin result = shift_dout; end
ALUOP_SRA: begin shift_right_nleft = 1'b1; shift_arith = 1'b1; result = shift_dout; end ALUOP_SRA: begin result = shift_dout; end
ALUOP_SLL: begin result = shift_dout; end ALUOP_SLL: begin result = shift_dout; end
default: begin result = bitwise; end default: begin result = bitwise; end
endcase endcase

4
hdl/arith/hazard3_shift_barrel.v
View File

@ -39,9 +39,7 @@ wire sext = arith && din_rev[0]; // haha
always @ (*) begin always @ (*) begin
for (i = 0; i < W_DATA; i = i + 1) for (i = 0; i < W_DATA; i = i + 1)
din_rev[i] = right_nleft ? din[W_DATA - 1 - i] : din[i]; din_rev[i] = right_nleft ? din[W_DATA - 1 - i] : din[i];
end
always @ (*) begin
shift_accum = din_rev; shift_accum = din_rev;
for (i = 0; i < W_SHAMT; i = i + 1) begin for (i = 0; i < W_SHAMT; i = i + 1) begin
if (shamt[i]) begin if (shamt[i]) begin
@ -49,9 +47,7 @@ always @ (*) begin
({W_DATA{sext}} & ~({W_DATA{1'b1}} << (1 << i))); ({W_DATA{sext}} & ~({W_DATA{1'b1}} << (1 << i)));
end end
end end
end
always @ (*) begin
for (i = 0; i < W_DATA; i = i + 1) for (i = 0; i < W_DATA; i = i + 1)
dout[i] = right_nleft ? shift_accum[W_DATA - 1 - i] : shift_accum[i]; dout[i] = right_nleft ? shift_accum[W_DATA - 1 - i] : shift_accum[i];
end end