Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.

Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)

hdl/hazard3_config_inst.vh

@@ -7,6 +7,11 @@
 // be set at instantiation rather than editing the config file, and will flow
 // correctly down through the hierarchy.
 
+// The symbol HAZARD3_CONFIG_INST_NO_MHARTID can be defined to allow reuse of
+// this file in multicore instantiations, where cores share all parameters
+// except for MHARTID_VAL. It must be defined once before each include of
+// this file.
+
 .RESET_VECTOR       (RESET_VECTOR),
 .MTVEC_INIT         (MTVEC_INIT),
 .EXTENSION_A        (EXTENSION_A),
@@ -31,7 +36,9 @@
 .NUM_IRQ            (NUM_IRQ),
 .MVENDORID_VAL      (MVENDORID_VAL),
 .MIMPID_VAL         (MIMPID_VAL),
+`ifndef HAZARD3_CONFIG_INST_NO_MHARTID
 .MHARTID_VAL        (MHARTID_VAL),
+`endif
 .MCONFIGPTR_VAL     (MCONFIGPTR_VAL),
 .REDUCED_BYPASS     (REDUCED_BYPASS),
 .MULDIV_UNROLL      (MULDIV_UNROLL),
@@ -43,3 +50,7 @@
 .RESET_REGFILE      (RESET_REGFILE),
 .W_ADDR             (W_ADDR),
 .W_DATA             (W_DATA)
+
+`ifdef HAZARD3_CONFIG_INST_NO_MHARTID
+`undef HAZARD3_CONFIG_INST_NO_MHARTID
+`endif

test/sim/tb_cxxrtl/tb_multicore.v

@@ -190,30 +190,9 @@ assign sys_reset_done = rst_n_cpu0 && rst_n_cpu1;
 assign hart_reset_done = {rst_n_cpu1, rst_n_cpu0};
 
 hazard3_cpu_1port #(
-	// Have to copy paste hazard3_config_inst.vh just so we can change MHARTID
-	.RESET_VECTOR    (RESET_VECTOR),
-	.MTVEC_INIT      (MTVEC_INIT),
-	.EXTENSION_A     (EXTENSION_A),
-	.EXTENSION_C     (EXTENSION_C),
-	.EXTENSION_M     (EXTENSION_M),
-	.EXTENSION_ZBA   (EXTENSION_ZBA),
-	.EXTENSION_ZBB   (EXTENSION_ZBB),
-	.EXTENSION_ZBC   (EXTENSION_ZBC),
-	.EXTENSION_ZBS   (EXTENSION_ZBS),
-	.CSR_M_MANDATORY (CSR_M_MANDATORY),
-	.CSR_M_TRAP      (CSR_M_TRAP),
-	.CSR_COUNTER     (CSR_COUNTER),
-	.DEBUG_SUPPORT   (DEBUG_SUPPORT),
-	.NUM_IRQ         (NUM_IRQ),
-	.MVENDORID_VAL   (MVENDORID_VAL),
-	.MIMPID_VAL      (MIMPID_VAL),
 	.MHARTID_VAL (32'h0000_0000),
-	.MCONFIGPTR_VAL  (MCONFIGPTR_VAL),
+`define HAZARD3_CONFIG_INST_NO_MHARTID
-	.REDUCED_BYPASS  (REDUCED_BYPASS),
+`include "hazard3_config_inst.vh"
-	.MULDIV_UNROLL   (MULDIV_UNROLL),
-	.MUL_FAST        (MUL_FAST),
-	.MULH_FAST       (MULH_FAST),
-	.MTVEC_WMASK     (MTVEC_WMASK)
 ) cpu0 (
 	.clk                        (clk),
 	.rst_n                      (rst_n_cpu0),
@@ -254,30 +233,9 @@ hazard3_cpu_1port #(
 );
 
 hazard3_cpu_1port #(
-	// Have to copy paste hazard3_config_inst.vh just so we can change MHARTID
-	.RESET_VECTOR    (RESET_VECTOR),
-	.MTVEC_INIT      (MTVEC_INIT),
-	.EXTENSION_A     (EXTENSION_A),
-	.EXTENSION_C     (EXTENSION_C),
-	.EXTENSION_M     (EXTENSION_M),
-	.EXTENSION_ZBA   (EXTENSION_ZBA),
-	.EXTENSION_ZBB   (EXTENSION_ZBB),
-	.EXTENSION_ZBC   (EXTENSION_ZBC),
-	.EXTENSION_ZBS   (EXTENSION_ZBS),
-	.CSR_M_MANDATORY (CSR_M_MANDATORY),
-	.CSR_M_TRAP      (CSR_M_TRAP),
-	.CSR_COUNTER     (CSR_COUNTER),
-	.DEBUG_SUPPORT   (DEBUG_SUPPORT),
-	.NUM_IRQ         (NUM_IRQ),
-	.MVENDORID_VAL   (MVENDORID_VAL),
-	.MIMPID_VAL      (MIMPID_VAL),
 	.MHARTID_VAL (32'h0000_0001),
-	.MCONFIGPTR_VAL  (MCONFIGPTR_VAL),
+`define HAZARD3_CONFIG_INST_NO_MHARTID
-	.REDUCED_BYPASS  (REDUCED_BYPASS),
+`include "hazard3_config_inst.vh"
-	.MULDIV_UNROLL   (MULDIV_UNROLL),
-	.MUL_FAST        (MUL_FAST),
-	.MULH_FAST       (MULH_FAST),
-	.MTVEC_WMASK     (MTVEC_WMASK)
 ) cpu1 (
 	.clk                        (clk),
 	.rst_n                      (rst_n_cpu1),