Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
This commit is contained in:
Luke Wren
parent
e16ae06cb5
commit
9173bcf585
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@ -37,7 +37,13 @@ module fpga_icebreaker (
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output wire mirror_tdo,
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output wire uart_tx,
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input wire uart_rx
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input wire uart_rx,
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output wire spi_cs_n,
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output wire spi_sck,
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output wire spi_mosi,
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input wire spi_miso
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);
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assign mirror_tck = tck;
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@ -64,7 +70,7 @@ reset_sync trst_sync_u (
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);
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activity_led #(
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.WIDTH (1 << 16),
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.WIDTH (1 << 8),
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.ACTIVE_LEVEL (1'b0)
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) tck_led_u (
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.clk (clk_sys),
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@ -75,19 +81,25 @@ activity_led #(
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example_soc #(
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.MUL_FAST (1),
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.EXTENSION_C (0)
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.EXTENSION_C (0),
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.CSR_COUNTER (0)
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) soc_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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.tck (tck),
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.trst_n (trst_n),
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.tms (tms),
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.tdi (tdi),
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.tdo (tdo),
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.tck (tck),
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.trst_n (trst_n),
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.tms (tms),
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.tdi (tdi),
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.tdo (tdo),
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.uart_tx (uart_tx),
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.uart_rx (uart_rx)
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.uart_tx (uart_tx),
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.uart_rx (uart_rx),
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.spi_cs_n (spi_cs_n),
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.spi_sck (spi_sck),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso)
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);
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endmodule
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@ -1 +1 @@
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Subproject commit 0b647a3f8e82d93b4b1e78ec72c33ff487f00d33
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Subproject commit 19279520e7b265f7eb20f0ca7f9ffc7c5d02dc51
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@ -39,7 +39,12 @@ module example_soc #(
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// IO
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output wire uart_tx,
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input wire uart_rx
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input wire uart_rx,
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output wire spi_cs_n,
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output wire spi_sck,
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output wire spi_mosi,
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input wire spi_miso
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);
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localparam W_ADDR = 32;
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@ -227,6 +232,7 @@ wire [W_DATA-1:0] proc_hwdata;
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wire [W_DATA-1:0] proc_hrdata;
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wire uart_irq;
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wire timer_irq;
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hazard3_cpu_1port #(
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// These must have the values given here for you to end up with a useful SoC:
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@ -283,18 +289,19 @@ hazard3_cpu_1port #(
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.irq (uart_irq),
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// Should provide timer and software-controllable IRQ at system level --
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// not implemented in this basic SoC.
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.soft_irq (1'b0),
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.timer_irq (1'b0)
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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// Bus fabric
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// - 128 kB SRAM (using SPRAMs) at 0x0000_0000
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// - UART at 0x4000_0000
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// - 128 kB SRAM at... 0x0000_0000
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// - System timer at.. 0x4000_0000
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// - UART at.......... 0x4000_4000
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// - XIP controls at.. 0x4000_8000
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// - XIP window at.... 0x8000_0000
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// AHBL layer
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@ -324,11 +331,24 @@ wire bridge_hmastlock;
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wire [W_DATA-1:0] bridge_hwdata;
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wire [W_DATA-1:0] bridge_hrdata;
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wire xip_hready_resp;
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wire xip_hready;
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wire xip_hresp;
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wire [W_ADDR-1:0] xip_haddr;
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wire xip_hwrite;
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wire [1:0] xip_htrans;
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wire [2:0] xip_hsize;
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wire [2:0] xip_hburst;
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wire [3:0] xip_hprot;
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wire xip_hmastlock;
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wire [W_DATA-1:0] xip_hwdata;
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wire [W_DATA-1:0] xip_hrdata;
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ahbl_splitter #(
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.N_PORTS (2),
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.ADDR_MAP (64'h40000000_00000000),
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.ADDR_MASK (64'he0000000_e0000000)
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.N_PORTS (3),
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.ADDR_MAP (96'h80000000_40000000_00000000),
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.ADDR_MASK (96'he0000000_e0000000_e0000000)
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) splitter_u (
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.clk (clk),
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.rst_n (rst_n),
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@ -346,22 +366,31 @@ ahbl_splitter #(
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.src_hwdata (proc_hwdata ),
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.src_hrdata (proc_hrdata ),
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.dst_hready_resp ({bridge_hready_resp , sram0_hready_resp}),
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.dst_hready ({bridge_hready , sram0_hready }),
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.dst_hresp ({bridge_hresp , sram0_hresp }),
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.dst_haddr ({bridge_haddr , sram0_haddr }),
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.dst_hwrite ({bridge_hwrite , sram0_hwrite }),
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.dst_htrans ({bridge_htrans , sram0_htrans }),
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.dst_hsize ({bridge_hsize , sram0_hsize }),
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.dst_hburst ({bridge_hburst , sram0_hburst }),
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.dst_hprot ({bridge_hprot , sram0_hprot }),
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.dst_hmastlock ({bridge_hmastlock , sram0_hmastlock }),
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.dst_hwdata ({bridge_hwdata , sram0_hwdata }),
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.dst_hrdata ({bridge_hrdata , sram0_hrdata })
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.dst_hready_resp ({xip_hready_resp , bridge_hready_resp , sram0_hready_resp}),
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.dst_hready ({xip_hready , bridge_hready , sram0_hready }),
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.dst_hresp ({xip_hresp , bridge_hresp , sram0_hresp }),
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.dst_haddr ({xip_haddr , bridge_haddr , sram0_haddr }),
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.dst_hwrite ({xip_hwrite , bridge_hwrite , sram0_hwrite }),
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.dst_htrans ({xip_htrans , bridge_htrans , sram0_htrans }),
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.dst_hsize ({xip_hsize , bridge_hsize , sram0_hsize }),
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.dst_hburst ({xip_hburst , bridge_hburst , sram0_hburst }),
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.dst_hprot ({xip_hprot , bridge_hprot , sram0_hprot }),
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.dst_hmastlock ({xip_hmastlock , bridge_hmastlock , sram0_hmastlock }),
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.dst_hwdata ({xip_hwdata , bridge_hwdata , sram0_hwdata }),
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.dst_hrdata ({xip_hrdata , bridge_hrdata , sram0_hrdata })
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);
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// APB layer
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wire bridge_psel;
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wire bridge_penable;
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wire bridge_pwrite;
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wire [15:0] bridge_paddr;
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wire [31:0] bridge_pwdata;
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wire [31:0] bridge_prdata;
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wire bridge_pready;
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wire bridge_pslverr;
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wire uart_psel;
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wire uart_penable;
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wire uart_pwrite;
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@ -371,6 +400,25 @@ wire [31:0] uart_prdata;
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wire uart_pready;
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wire uart_pslverr;
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wire timer_psel;
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wire timer_penable;
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wire timer_pwrite;
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wire [15:0] timer_paddr;
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wire [31:0] timer_pwdata;
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wire [31:0] timer_prdata;
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wire timer_pready;
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wire timer_pslverr;
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wire xip_psel;
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wire xip_penable;
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wire xip_pwrite;
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wire [15:0] xip_paddr;
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wire [31:0] xip_pwdata;
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wire [31:0] xip_prdata;
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wire xip_pready;
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wire xip_pslverr;
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ahbl_to_apb apb_bridge_u (
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.clk (clk),
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.rst_n (rst_n),
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@ -388,14 +436,38 @@ ahbl_to_apb apb_bridge_u (
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.ahbls_hwdata (bridge_hwdata),
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.ahbls_hrdata (bridge_hrdata),
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.apbm_paddr (uart_paddr),
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.apbm_psel (uart_psel),
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.apbm_penable (uart_penable),
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.apbm_pwrite (uart_pwrite),
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.apbm_pwdata (uart_pwdata),
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.apbm_pready (uart_pready),
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.apbm_prdata (uart_prdata),
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.apbm_pslverr (uart_pslverr)
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.apbm_paddr (bridge_paddr),
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.apbm_psel (bridge_psel),
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.apbm_penable (bridge_penable),
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.apbm_pwrite (bridge_pwrite),
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.apbm_pwdata (bridge_pwdata),
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.apbm_pready (bridge_pready),
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.apbm_prdata (bridge_prdata),
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.apbm_pslverr (bridge_pslverr)
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);
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apb_splitter #(
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.N_SLAVES (3),
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.ADDR_MAP (48'h8000_4000_0000),
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.ADDR_MASK (48'hc000_c000_c000)
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) inst_apb_splitter (
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.apbs_paddr (bridge_paddr),
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.apbs_psel (bridge_psel),
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.apbs_penable (bridge_penable),
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.apbs_pwrite (bridge_pwrite),
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.apbs_pwdata (bridge_pwdata),
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.apbs_pready (bridge_pready),
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.apbs_prdata (bridge_prdata),
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.apbs_pslverr (bridge_pslverr),
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.apbm_paddr ({xip_paddr , uart_paddr , timer_paddr }),
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.apbm_psel ({xip_psel , uart_psel , timer_psel }),
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.apbm_penable ({xip_penable , uart_penable , timer_penable}),
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.apbm_pwrite ({xip_pwrite , uart_pwrite , timer_pwrite }),
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.apbm_pwdata ({xip_pwdata , uart_pwdata , timer_pwdata }),
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.apbm_pready ({xip_pready , uart_pready , timer_pready }),
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.apbm_prdata ({xip_prdata , uart_prdata , timer_prdata }),
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.apbm_pslverr ({xip_pslverr , uart_pslverr , timer_pslverr})
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);
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// ----------------------------------------------------------------------------
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@ -446,4 +518,112 @@ uart_mini uart_u (
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.dreq (/* unused */)
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);
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hazard3_riscv_timer timer_u (
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.clk (clk),
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.rst_n (rst_n),
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.psel (timer_psel),
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.penable (timer_penable),
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.pwrite (timer_pwrite),
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.paddr (timer_paddr),
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.pwdata (timer_pwdata),
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.prdata (timer_prdata),
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.pready (timer_pready),
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.pslverr (timer_pslverr),
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.dbg_halt (&hart_halted),
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// Tie high for 64-cycle timebase:
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.tick (1'b1),
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.timer_irq (timer_irq)
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);
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wire xip_uncached_hready_resp;
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wire xip_uncached_hready;
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wire xip_uncached_hresp;
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wire [23:0] xip_uncached_haddr;
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wire xip_uncached_hwrite;
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wire [1:0] xip_uncached_htrans;
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wire [2:0] xip_uncached_hsize;
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wire [2:0] xip_uncached_hburst;
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wire [3:0] xip_uncached_hprot;
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wire xip_uncached_hmastlock;
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wire [W_DATA-1:0] xip_uncached_hwdata;
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wire [W_DATA-1:0] xip_uncached_hrdata;
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ahb_cache_readonly #(
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.N_WAYS (1),
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.W_ADDR (24),
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.W_DATA (32),
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.W_LINE (32),
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.TMEM_PRELOAD (""),
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.DMEM_PRELOAD (""),
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// 4 kB cache, 12 iCE40 BRAMs (1024 x 32 data, 1024 x (12 + 1) (tag + valid))
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.DEPTH (1024)
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) xip_cache_u (
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.clk (clk),
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.rst_n (rst_n),
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.src_hready_resp (xip_hready_resp),
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.src_hready (xip_hready),
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.src_hresp (xip_hresp),
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.src_haddr (xip_haddr[23:0]),
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.src_hwrite (xip_hwrite),
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.src_htrans (xip_htrans),
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.src_hsize (xip_hsize),
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.src_hburst (xip_hburst),
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.src_hprot (xip_hprot),
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.src_hmastlock (xip_hmastlock),
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.src_hwdata (xip_hwdata),
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.src_hrdata (xip_hrdata),
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.dst_hready_resp (xip_uncached_hready_resp),
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.dst_hready (xip_uncached_hready),
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.dst_hresp (xip_uncached_hresp),
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.dst_haddr (xip_uncached_haddr),
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.dst_hwrite (xip_uncached_hwrite),
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.dst_htrans (xip_uncached_htrans),
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.dst_hsize (xip_uncached_hsize),
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.dst_hburst (xip_uncached_hburst),
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.dst_hprot (xip_uncached_hprot),
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.dst_hmastlock (xip_uncached_hmastlock),
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.dst_hwdata (xip_uncached_hwdata),
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.dst_hrdata (xip_uncached_hrdata)
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);
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spi_03h_xip xip_u (
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.clk (clk),
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.rst_n (rst_n),
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.apbs_psel (xip_psel),
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.apbs_penable (xip_penable),
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.apbs_pwrite (xip_pwrite),
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.apbs_paddr (xip_paddr),
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.apbs_pwdata (xip_pwdata),
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.apbs_prdata (xip_prdata),
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.apbs_pready (xip_pready),
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.apbs_pslverr (xip_pslverr),
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.ahbls_hready_resp (xip_uncached_hready_resp),
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.ahbls_hready (xip_uncached_hready),
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.ahbls_hresp (xip_uncached_hresp),
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.ahbls_haddr (xip_uncached_haddr),
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.ahbls_hwrite (xip_uncached_hwrite),
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.ahbls_htrans (xip_uncached_htrans),
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.ahbls_hsize (xip_uncached_hsize),
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.ahbls_hburst (xip_uncached_hburst),
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.ahbls_hprot (xip_uncached_hprot),
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.ahbls_hmastlock (xip_uncached_hmastlock),
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.ahbls_hwdata (xip_uncached_hwdata),
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.ahbls_hrdata (xip_uncached_hrdata),
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.spi_cs_n (spi_cs_n),
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.spi_sck (spi_sck),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso)
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);
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endmodule
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@ -1,14 +1,25 @@
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# SoC integration file
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file example_soc.v
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# CPU + debug components
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list $HDL/hazard3.f
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list $HDL/debug/dtm/hazard3_jtag_dtm.f
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list $HDL/debug/dm/hazard3_dm.f
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list $HDL/peri/hazard3_riscv_timer.f
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# Generic SoC components from libfpga
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file ../libfpga/common/reset_sync.v
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list ../libfpga/peris/uart/uart.f
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list ../libfpga/peris/spi_03h_xip/spi_03h_xip.f
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list ../libfpga/mem/ahb_cache.f
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list ../libfpga/mem/ahb_sync_sram.f
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list ../libfpga/busfabric/ahbl_crossbar.f
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file ../libfpga/busfabric/ahbl_to_apb.v
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file ../libfpga/busfabric/apb_splitter.v
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@ -15,18 +15,22 @@ set_io tdi 9 # FTDI BDBUS1
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set_io tdo 18 # FTDI BDBUS2
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set_io tms 19 # FTDI BDBUS3
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# UART is moved over to FTDI A channel -- this means flash is inaccessible
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# (and stays in a quiescent state since CSn is disconnected and pulled high)
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set_io uart_rx 15 # FTDI ADBUS0, flash SCK, iCE SCK
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set_io uart_tx 14 # FTDI ADBUS1, flash MOSI, iCE SO (if jumper J15 connected)
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# # UART is moved over to FTDI A channel -- this means flash is inaccessible
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# # (and stays in a quiescent state since CSn is disconnected and pulled high)
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# set_io uart_rx 15 # FTDI ADBUS0, flash SCK, iCE SCK
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# set_io uart_tx 14 # FTDI ADBUS1, flash MOSI, iCE SO (if jumper J15 connected)
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# FIXME UART clashes with SPI signals, so punt it onto a header
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set_io uart_rx 4 # P1A1
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set_io uart_tx 2 # P1A2
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set_io led 37 # Green on main board
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# SPI flash
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# set_io flash_mosi 14
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# set_io flash_miso 17
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# set_io flash_sclk 15
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# set_io flash_cs 16
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set_io spi_mosi 14
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set_io spi_miso 17
|
||||
set_io spi_sck 15
|
||||
set_io spi_cs_n 16
|
||||
|
||||
# # Buttons
|
||||
# set_io dpad_u 20 # Snapoff top
|
||||
|
|
|
|||
Loading…
Reference in New Issue