Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)

test/sim/coremark/dist/barebones/core_portme.mak

@@ -24,7 +24,7 @@ LD		= riscv32-unknown-elf-gcc
 AS		= riscv32-unknown-elf-gcc
 # Flag : CFLAGS
 #	Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
-PORT_CFLAGS = -O3 -g -march=rv32imc_zicsr_zba_zbb_zbc_zbs -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4
+PORT_CFLAGS = -O3 -g -march=rv32im_zicsr_zba_zbb_zbc_zbs -fno-common -funroll-loops -finline-functions --param max-inline-insns-auto=20 -falign-functions=4 -falign-jumps=4 -falign-loops=4
 FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
 CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" 
 #Flag : LFLAGS_END

test/sim/embench/embench-iot

@@ -1 +1 @@
-Subproject commit 97bf4b8e15e3bb8654896aaca66399f26db6d657
+Subproject commit cada0c3b4ed3dca9bd3787148acc719273750440

test/sim/riscv-tests/debug.gtkw

@@ -1,21 +1,21 @@
 [*]
 [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
-[*] Sun Jul  3 18:10:08 2022
+[*] Sun Jul  3 23:06:37 2022
 [*]
 [dumpfile] "/home/luke/proj/hazard3/test/sim/riscv-tests/riscv-tests/debug/waves.vcd"
-[dumpfile_mtime] "Sun Jul  3 18:08:00 2022"
-[dumpfile_size] 95825843
+[dumpfile_mtime] "Sun Jul  3 23:06:19 2022"
+[dumpfile_size] 259991106
 [savefile] "/home/luke/proj/hazard3/test/sim/riscv-tests/debug.gtkw"
-[timestart] 519500
-[size] 1920 2096
+[timestart] 740660
+[size] 1620 2096
 [pos] -1 -1
-*-16.000000 771701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-12.000000 759700 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] cpu.
 [treeopen] cpu.core.
 [sst_width] 233
 [signals_width] 182
 [sst_expanded] 1
-[sst_vpaned_height] 665
+[sst_vpaned_height] 664
 @28
 dm.sberror[2:0]
 dm.sbbusy
@@ -46,11 +46,43 @@ dm.sbus_rdata[31:0]
 @200
 -
 -Core Bus Request
+@22
+cpu.core_haddr_d[31:0]
 @28
 cpu.core_aph_req_d
 cpu.core_aph_ready_d
 cpu.core_dph_ready_d
-@201
+@200
 -
+-D Bus
+@22
+cpu.d_haddr[31:0]
+@28
+cpu.d_htrans[1:0]
+cpu.d_hwrite
+cpu.d_hready
+@22
+cpu.d_hwdata[31:0]
+cpu.d_hrdata[31:0]
+@200
+-
+-I Bus
+@22
+cpu.i_haddr[31:0]
+@28
+cpu.i_htrans[1:0]
+cpu.i_hready
+@22
+cpu.i_hrdata[31:0]
+@200
+-
+-Run/Halt
+@28
+cpu.dbg_req_halt
+cpu.dbg_req_resume
+@200
+-
+@29
+cpu.dbg_halted
 [pattern_trace] 1
 [pattern_trace] 0

test/sim/rvpy/rvpy

@@ -110,7 +110,7 @@ class MemWithTBIO(FlatMemory):
 		elif addr == self.TB_IO_PRINT_CHAR:
 			sys.stdout.write(self.io_log_fmt.format(chr(data)))
 		elif addr == self.TB_IO_PRINT_INT:
-			sys.stdout.write(self.io_log_fmt.format(f"{data:08x}"))
+			sys.stdout.write(self.io_log_fmt.format(f"{data:08x}\n"))
 		elif addr == self.TB_IO_EXIT:
 			raise TBExit(data)
 		else:
@@ -514,7 +514,7 @@ def main(argv):
 		for i in range(args.cycles):
 			rv.step(log=not args.quiet)
 	except TBExit as e:
-		print(f"Processor halted simulation with exit code {e}")
+		print(f"CPU requested halt. Exit code {e}")
 	except BrokenPipeError as e:
 		sys.exit(0)
 	print(f"Ran for {i + 1} cycles")

test/sim/tb_cxxrtl/multicore.gtkw

@@ -1,15 +1,15 @@
 [*]
-[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Wed Dec 15 09:37:16 2021
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Sat Jul  2 12:28:35 2022
 [*]
 [dumpfile] "/home/luke/proj/hazard3/test/sim/tb_cxxrtl/waves.vcd"
-[dumpfile_mtime] "Wed Dec 15 09:24:58 2021"
-[dumpfile_size] 9773165
+[dumpfile_mtime] "Sun Jun 26 18:58:42 2022"
+[dumpfile_size] 34958839
 [savefile] "/home/luke/proj/hazard3/test/sim/tb_cxxrtl/multicore.gtkw"
 [timestart] 0
 [size] 2509 1368
 [pos] -1 -1
-*-13.000000 9780 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-16.000000 136300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [sst_width] 233
 [signals_width] 238
 [sst_expanded] 1
@@ -23,12 +23,27 @@ tdo
 tms
 @200
 -
+@22
+dm.dmi_paddr[8:0]
 @28
-dm.hartsel
+dm.dmi_penable
+dm.dmi_pwrite
+@22
+dm.dmi_pwdata[31:0]
+dm.dmi_prdata[31:0]
 @200
 -
+@28
+dm.hartsel
+dm.hasel
+dm.hart_array_mask[1:0]
+dm.hart_array_mask_next[1:0]
+@200
+-
+>-491
 -Core 0 debug
 @28
+>0
 cpu0.dbg_req_halt
 cpu0.dbg_req_resume
 cpu0.dbg_halted