From 924967ee7204b38d98d775fa74ec63244eaca09c Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Sun, 25 Jul 2021 13:29:41 +0100
Subject: [PATCH] Back off ULX3S frequency to 40 MHz -- 50 works fine but fails
 to close after increasing RAM from 4k to 128k

---
 example_soc/fpga/fpga_ulx3s.f |  1 +
 example_soc/fpga/fpga_ulx3s.v |  2 +-
 example_soc/fpga/pll_25_40.v  | 46 +++++++++++++++++++++++++++++++++++
 3 files changed, 48 insertions(+), 1 deletion(-)
 create mode 100644 example_soc/fpga/pll_25_40.v

diff --git a/example_soc/fpga/fpga_ulx3s.f b/example_soc/fpga/fpga_ulx3s.f
index 0d9490b..5e48959 100644
--- a/example_soc/fpga/fpga_ulx3s.f
+++ b/example_soc/fpga/fpga_ulx3s.f
@@ -1,5 +1,6 @@
 file fpga_ulx3s.v
 file pll_25_50.v
+file pll_25_40.v
 file ../libfpga/common/reset_sync.v
 file ../libfpga/common/fpga_reset.v
 
diff --git a/example_soc/fpga/fpga_ulx3s.v b/example_soc/fpga/fpga_ulx3s.v
index 1b95a5a..5277660 100644
--- a/example_soc/fpga/fpga_ulx3s.v
+++ b/example_soc/fpga/fpga_ulx3s.v
@@ -29,7 +29,7 @@ wire clk_sys;
 wire pll_sys_locked;
 wire rst_n_sys;
 
-pll_25_50 pll_sys (
+pll_25_40 pll_sys (
 	.clkin   (clk_osc),
 	.clkout0 (clk_sys),
 	.locked  (pll_sys_locked)
diff --git a/example_soc/fpga/pll_25_40.v b/example_soc/fpga/pll_25_40.v
new file mode 100644
index 0000000..67c86a2
--- /dev/null
+++ b/example_soc/fpga/pll_25_40.v
@@ -0,0 +1,46 @@
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module pll_25_40
+(
+    input clkin, // 25 MHz, 0 deg
+    output clkout0, // 40 MHz, 0 deg
+    output locked
+);
+(* FREQUENCY_PIN_CLKI="25" *)
+(* FREQUENCY_PIN_CLKOP="40" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(5),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(15),
+        .CLKOP_CPHASE(7),
+        .CLKOP_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(8)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clkin),
+        .CLKOP(clkout0),
+        .CLKFB(clkout0),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+endmodule