diff --git a/test/sim/riscv-tests/run-smp-debug-tests.sh b/test/sim/riscv-tests/run-smp-debug-tests.sh
index 330ef08..ca7b494 100755
--- a/test/sim/riscv-tests/run-smp-debug-tests.sh
+++ b/test/sim/riscv-tests/run-smp-debug-tests.sh
@@ -1,7 +1,6 @@
 set -e
 
-make -C ../tb_cxxrtl/ DOTF=tb_multicore.f tb
-# make -C ../tb_cxxrtl/ DOTF=tb_multicore.f clean tb
+make -C ../tb_cxxrtl/ DOTF=tb_multicore.f
 cd riscv-tests/debug
 
 # Clean up old logs and test binaries
@@ -12,8 +11,61 @@ done
 
 # Only applicable tests are included
 ./gdbserver.py \
-	--sim_cmd "../../../tb_cxxrtl/tb --port 9824" \
-	--server_cmd riscv-openocd \
+	--sim_cmd "../../../tb_cxxrtl/tb_multicore --port 9824" \
+	--server_cmd "riscv-openocd" \
 	--gdb riscv32-unknown-elf-gdb \
 	--gcc riscv32-unknown-elf-gcc \
-	targets/luke/hazard3_smp.py
+	targets/luke/hazard3_smp.py \
+CheckMisa \
+MulticoreRegTest \
+MulticoreRtosSwitchActiveHartTest \
+SmpSimultaneousRunHalt \
+CrashLoopOpcode \ 
+DebugBreakpoint \
+DebugChangeString \
+DebugCompareSections \
+DebugExit \
+DebugFunctionCall \
+DebugSymbols \
+DebugTurbostep \
+DisconnectTest \
+DownloadTest \
+EbreakTest \
+Hwbp1 \
+Hwbp2 \
+HwbpManual \
+InfoTest \
+InstantChangePc \
+InstantHaltTest \
+InterruptTest \
+JumpHbreak \
+MemorySampleMixed \
+MemorySampleSingle \
+MemTest16 \
+MemTest32 \
+MemTest64 \
+MemTest8 \
+MemTestBlock0 \
+MemTestBlock1 \
+MemTestBlock2 \
+MemTestReadInvalid \
+PrivChange \
+PrivRw \
+ProgramSwWatchpoint \
+Registers \
+RepeatReadTest \
+Semihosting \
+SemihostingFileio \
+SimpleF18Test \
+SimpleNoExistTest \
+SimpleS0Test \
+SimpleS1Test \
+SimpleT0Test \
+SimpleT1Test \
+SimpleV13Test \
+StepTest \
+TooManyHwbp \
+TriggerExecuteInstant \
+UserInterrupt \
+WriteCsrs \
+WriteGprs