Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
This commit is contained in:
Luke Wren
parent
b352d3878d
commit
954bae5cf1
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@ -11,69 +11,69 @@ module hazard3_core #(
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`include "hazard3_width_const.vh"
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) (
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// Global signals
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input wire clk,
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input wire clk_always_on,
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input wire rst_n,
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input wire clk,
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input wire clk_always_on,
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input wire rst_n,
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// Power control signals
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output wire pwrup_req,
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input wire pwrup_ack,
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output wire clk_en,
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output wire unblock_out,
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input wire unblock_in,
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output wire pwrup_req,
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input wire pwrup_ack,
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output wire clk_en,
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output reg unblock_out,
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input wire unblock_in,
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`ifdef RISCV_FORMAL
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`RVFI_OUTPUTS ,
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`endif
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// Instruction fetch port
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output wire bus_aph_req_i,
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output wire bus_aph_panic_i, // e.g. branch mispredict + flush
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input wire bus_aph_ready_i,
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input wire bus_dph_ready_i,
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input wire bus_dph_err_i,
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output wire bus_aph_req_i,
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output wire bus_aph_panic_i, // e.g. branch mispredict + flush
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input wire bus_aph_ready_i,
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input wire bus_dph_ready_i,
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input wire bus_dph_err_i,
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output wire [W_ADDR-1:0] bus_haddr_i,
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output wire [2:0] bus_hsize_i,
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output wire bus_priv_i,
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input wire [W_DATA-1:0] bus_rdata_i,
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output wire [W_ADDR-1:0] bus_haddr_i,
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output wire [2:0] bus_hsize_i,
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output wire bus_priv_i,
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input wire [W_DATA-1:0] bus_rdata_i,
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// Load/store port
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output reg bus_aph_req_d,
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output wire bus_aph_excl_d,
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input wire bus_aph_ready_d,
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input wire bus_dph_ready_d,
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input wire bus_dph_err_d,
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input wire bus_dph_exokay_d,
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output reg bus_aph_req_d,
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output wire bus_aph_excl_d,
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input wire bus_aph_ready_d,
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input wire bus_dph_ready_d,
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input wire bus_dph_err_d,
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input wire bus_dph_exokay_d,
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output reg [W_ADDR-1:0] bus_haddr_d,
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output reg [2:0] bus_hsize_d,
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output reg bus_priv_d,
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output reg bus_hwrite_d,
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output reg [W_DATA-1:0] bus_wdata_d,
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input wire [W_DATA-1:0] bus_rdata_d,
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output reg [W_ADDR-1:0] bus_haddr_d,
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output reg [2:0] bus_hsize_d,
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output reg bus_priv_d,
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output reg bus_hwrite_d,
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output reg [W_DATA-1:0] bus_wdata_d,
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input wire [W_DATA-1:0] bus_rdata_d,
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// Debugger run/halt control
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input wire dbg_req_halt,
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input wire dbg_req_halt_on_reset,
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input wire dbg_req_resume,
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output wire dbg_halted,
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output wire dbg_running,
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input wire dbg_req_halt,
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input wire dbg_req_halt_on_reset,
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input wire dbg_req_resume,
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output wire dbg_halted,
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output wire dbg_running,
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// Debugger access to data0 CSR
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input wire [W_DATA-1:0] dbg_data0_rdata,
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output wire [W_DATA-1:0] dbg_data0_wdata,
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output wire dbg_data0_wen,
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input wire [W_DATA-1:0] dbg_data0_rdata,
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output wire [W_DATA-1:0] dbg_data0_wdata,
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output wire dbg_data0_wen,
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// Debugger instruction injection
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input wire [W_DATA-1:0] dbg_instr_data,
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input wire dbg_instr_data_vld,
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output wire dbg_instr_data_rdy,
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output wire dbg_instr_caught_exception,
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output wire dbg_instr_caught_ebreak,
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input wire [W_DATA-1:0] dbg_instr_data,
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input wire dbg_instr_data_vld,
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output wire dbg_instr_data_rdy,
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output wire dbg_instr_caught_exception,
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output wire dbg_instr_caught_ebreak,
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// Level-sensitive interrupt sources
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input wire [NUM_IRQS-1:0] irq, // -> mip.meip
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input wire soft_irq, // -> mip.msip
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input wire timer_irq // -> mip.mtip
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input wire [NUM_IRQS-1:0] irq, // -> mip.meip
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input wire soft_irq, // -> mip.msip
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input wire timer_irq // -> mip.mtip
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);
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`include "hazard3_ops.vh"
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@ -222,7 +222,7 @@ wire d_csr_w_imm;
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wire x_jump_not_except;
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wire x_mmode_execution;
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wire x_permit_wfi;
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wire x_trap_wfi;
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hazard3_decode #(
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`include "hazard3_config_inst.vh"
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@ -241,7 +241,7 @@ hazard3_decode #(
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.debug_mode (debug_mode),
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.m_mode (x_mmode_execution),
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.permit_wfi (x_permit_wfi),
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.trap_wfi (x_trap_wfi),
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.d_starved (d_starved),
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.x_stall (x_stall),
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@ -933,11 +933,14 @@ wire x_except_counts_as_retire =
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wire x_instr_ret = |df_cir_use && (x_except == EXCEPT_NONE || x_except_counts_as_retire);
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wire m_dphase_in_flight = xm_memop != MEMOP_NONE && xm_memop != MEMOP_AMO;
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wire m_delay_irq_entry = xm_delay_irq_entry_on_ls_dphase || ((xm_sleep_wfi || xm_sleep_block) && !m_sleep_stall_release);
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// Need to delay IRQ entry on sleep exit because, for deep sleep states, we
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// can't access the bus until the power handshake has completed.
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wire m_delay_irq_entry = xm_delay_irq_entry_on_ls_dphase ||
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((xm_sleep_wfi || xm_sleep_block) && !m_sleep_stall_release);
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wire m_allow_sleep;
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wire m_allow_power_down;
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wire m_allow_sleep_on_block;
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wire m_pwr_allow_sleep;
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wire m_pwr_allow_power_down;
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wire m_pwr_allow_sleep_on_block;
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wire m_wfi_wakeup_req;
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hazard3_csr #(
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@ -984,9 +987,9 @@ hazard3_csr #(
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.loadstore_dphase_pending (m_dphase_in_flight),
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.mepc_in (m_exception_return_addr),
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.pwr_allow_sleep (m_allow_sleep),
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.pwr_allow_power_down (m_allow_power_down),
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.pwr_allow_sleep_on_block (m_allow_sleep_on_block),
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.pwr_allow_sleep (m_pwr_allow_sleep),
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.pwr_allow_power_down (m_pwr_allow_power_down),
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.pwr_allow_sleep_on_block (m_pwr_allow_sleep_on_block),
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.pwr_wfi_wakeup_req (m_wfi_wakeup_req),
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.m_mode_execution (x_mmode_execution),
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@ -1013,7 +1016,7 @@ hazard3_csr #(
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.trig_m_en (x_trig_m_en),
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// Other CSR-specific signalling
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.permit_wfi (x_permit_wfi),
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.trap_wfi (x_trap_wfi),
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.instr_ret (x_instr_ret)
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);
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@ -1026,27 +1029,31 @@ always @ (posedge clk or negedge rst_n) begin
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xm_except_to_d_mode <= 1'b0;
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xm_sleep_wfi <= 1'b0;
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xm_sleep_block <= 1'b0;
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unblock_out <= 1'b0;
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{xm_rs1, xm_rs2, xm_rd} <= {3 * W_REGADDR{1'b0}};
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end else begin
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unblock_out <= 1'b0;
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if (!m_stall) begin
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{xm_rs1, xm_rs2, xm_rd} <= {d_rs1, d_rs2, d_rd};
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// If some X-sourced exception has squashed the address phase, need to squash the data phase too.
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xm_memop <= x_unaligned_addr || x_exec_pmp_fail || x_loadstore_pmp_fail ? MEMOP_NONE : d_memop;
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xm_except <= x_except;
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xm_memop <= x_except != EXCEPT_NONE ? MEMOP_NONE : d_memop;
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xm_except <= x_except;
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xm_except_to_d_mode <= x_trig_break_d_mode;
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xm_sleep_wfi <= d_sleep_wfi && !x_exec_pmp_fail;
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xm_sleep_block <= d_sleep_block && !x_exec_pmp_fail;
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xm_sleep_wfi <= x_except == EXCEPT_NONE && d_sleep_wfi;
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xm_sleep_block <= x_except == EXCEPT_NONE && d_sleep_block;
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unblock_out <= x_except == EXCEPT_NONE && d_sleep_unblock;
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// Note the d_starved term is required because it is possible
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// (e.g. PMP X permission fail) to except when the frontend is
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// starved, and we get a bad mepc if we let this jump ahead:
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if (x_stall || d_starved || m_trap_enter_soon) begin
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// Insert bubble
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xm_rd <= {W_REGADDR{1'b0}};
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xm_memop <= MEMOP_NONE;
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xm_except <= EXCEPT_NONE;
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xm_rd <= {W_REGADDR{1'b0}};
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xm_memop <= MEMOP_NONE;
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xm_except <= EXCEPT_NONE;
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xm_except_to_d_mode <= 1'b0;
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xm_sleep_wfi <= 1'b0;
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xm_sleep_block <= 1'b0;
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xm_sleep_wfi <= 1'b0;
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xm_sleep_block <= 1'b0;
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unblock_out <= 1'b0;
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end
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end else if (bus_dph_err_d) begin
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// First phase of 2-phase AHB5 error response. Pass the exception along on
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@ -1056,6 +1063,7 @@ always @ (posedge clk or negedge rst_n) begin
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assert(xm_memop != MEMOP_NONE);
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assert(!xm_sleep_wfi);
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assert(!xm_sleep_block);
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assert(!unblock_out);
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`endif
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xm_except <=
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|EXTENSION_A && xm_memop == MEMOP_LR_W ? EXCEPT_LOAD_FAULT :
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@ -1142,15 +1150,15 @@ hazard3_power_ctrl power_ctrl (
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.pwrup_ack (pwrup_ack),
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.clk_en (clk_en),
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.allow_sleep (m_allow_sleep),
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.allow_power_down (m_allow_power_down),
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.allow_sleep_on_block (m_allow_sleep_on_block),
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.allow_sleep (m_pwr_allow_sleep),
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.allow_power_down (m_pwr_allow_power_down),
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.allow_sleep_on_block (m_pwr_allow_sleep_on_block),
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.frontend_pwrdown_ok (f_frontend_pwrdown_ok),
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.sleeping_on_wfi (xm_sleep_wfi),
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.wfi_wakeup_req (m_wfi_wakeup_req),
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.sleeping_on_block (xm_sleep_wfi),
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.sleeping_on_block (xm_sleep_block),
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.block_wakeup_req_pulse (unblock_in),
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.stall_release (m_sleep_stall_release)
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);
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@ -117,7 +117,8 @@ module hazard3_csr #(
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output wire trig_m_en,
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// Other CSR-specific signalling
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output wire permit_wfi,
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output wire trap_wfi,
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output wire wfi_is_nop,
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input wire instr_ret
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);
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@ -226,8 +227,11 @@ always @ (posedge clk or negedge rst_n) begin
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end
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end
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// Simply trap all U-mode WFIs if timeout bit is set
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assign permit_wfi = m_mode || !mstatus_tw;
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// Trap all U-mode WFIs if timeout bit is set. Note that the debug spec
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// says "The `wfi` instruction acts as a `nop`" during program buffer
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// execution, and nops do not trap, so in debug mode we uncondi allow WFIs but we inhibit their sleep signal.
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assign trap_wfi = mstatus_tw && !(debug_mode || m_mode);
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assign wfi_is_nop = debug_mode;
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reg [XLEN-1:0] mscratch;
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@ -23,7 +23,7 @@ module hazard3_decode #(
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input wire debug_mode,
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input wire m_mode,
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input wire permit_wfi,
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input wire trap_wfi,
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output wire d_starved,
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input wire x_stall,
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@ -233,7 +233,6 @@ always @ (*) begin
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`RVOPC_ADD: begin d_aluop = ALUOP_ADD; end
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`RVOPC_SUB: begin d_aluop = ALUOP_SUB; end
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`RVOPC_SLL: begin d_aluop = ALUOP_SLL; end
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`RVOPC_SLT: begin d_aluop = ALUOP_LT; end
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`RVOPC_SLTU: begin d_aluop = ALUOP_LTU; end
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`RVOPC_XOR: begin d_aluop = ALUOP_XOR; end
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`RVOPC_SRL: begin d_aluop = ALUOP_SRL; end
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@ -249,6 +248,21 @@ always @ (*) begin
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`RVOPC_SH: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SH; d_rd = X0; end
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`RVOPC_SW: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SW; d_rd = X0; end
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`RVOPC_SLT: begin
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d_aluop = ALUOP_LT;
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if (|EXTENSION_XH3POWER && ~|d_rd && ~|d_rs1) begin
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if (d_rs2 == 5'h00) begin
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// h3.block (power management hint)
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d_invalid_32bit = trap_wfi;
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d_sleep_block = !trap_wfi;
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end else if (d_rs2 == 5'h01) begin
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// h3.unblock (power management hint)
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d_invalid_32bit = trap_wfi;
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d_sleep_unblock = !trap_wfi;
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end
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end
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end
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`RVOPC_MUL: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MUL; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_MULH: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULH; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_MULHSU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHSU; end else begin d_invalid_32bit = 1'b1; end
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@ -318,31 +332,33 @@ always @ (*) begin
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`RVOPC_H3_BEXTMI: if (EXTENSION_XH3BEXTM) begin d_aluop = ALUOP_BEXTM; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_FENCE: begin d_rs2 = X0; end // NOP, note rs1/rd are zero in instruction
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`RVOPC_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_fence_i = 1'b1; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction
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`RVOPC_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_CSRRWI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_CSRRSI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_CSRRCI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_ECALL: if (HAVE_CSR) begin d_except = m_mode || !U_MODE ? EXCEPT_ECALL_M : EXCEPT_ECALL_U; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_EBREAK: if (HAVE_CSR) begin d_except = EXCEPT_EBREAK; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_MRET: if (HAVE_CSR && m_mode) begin d_except = EXCEPT_MRET; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_WFI: if (HAVE_CSR && permit_wfi) begin d_sleep_wfi = 1'b1; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_fence_i = 1'b1; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction
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`RVOPC_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end
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`RVOPC_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_CSRRWI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_CSRRSI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_CSRRCI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_ECALL: if (HAVE_CSR) begin d_except = m_mode || !U_MODE ? EXCEPT_ECALL_M : EXCEPT_ECALL_U; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_EBREAK: if (HAVE_CSR) begin d_except = EXCEPT_EBREAK; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_MRET: if (HAVE_CSR && m_mode) begin d_except = EXCEPT_MRET; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
|
||||
`RVOPC_WFI: if (HAVE_CSR && !trap_wfi) begin d_sleep_wfi = 1'b1; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end
|
||||
|
||||
default: begin d_invalid_32bit = 1'b1; end
|
||||
endcase
|
||||
|
||||
if (d_invalid || d_starved || d_except_instr_bus_fault || partial_predicted_branch) begin
|
||||
d_rs1 = {W_REGADDR{1'b0}};
|
||||
d_rs2 = {W_REGADDR{1'b0}};
|
||||
d_rd = {W_REGADDR{1'b0}};
|
||||
d_memop = MEMOP_NONE;
|
||||
d_branchcond = BCOND_NEVER;
|
||||
d_csr_ren = 1'b0;
|
||||
d_csr_wen = 1'b0;
|
||||
d_except = EXCEPT_NONE;
|
||||
d_sleep_wfi = 1'b0;
|
||||
d_rs1 = {W_REGADDR{1'b0}};
|
||||
d_rs2 = {W_REGADDR{1'b0}};
|
||||
d_rd = {W_REGADDR{1'b0}};
|
||||
d_memop = MEMOP_NONE;
|
||||
d_branchcond = BCOND_NEVER;
|
||||
d_csr_ren = 1'b0;
|
||||
d_csr_wen = 1'b0;
|
||||
d_except = EXCEPT_NONE;
|
||||
d_sleep_wfi = 1'b0;
|
||||
d_sleep_block = 1'b0;
|
||||
d_sleep_unblock = 1'b0;
|
||||
if (EXTENSION_M)
|
||||
d_aluop = ALUOP_ADD;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
#ifndef _HAZARD3_INSTR_H
|
||||
#define _HAZARD3_INSTR_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
// C macros for Hazard3 custom instructions
|
||||
|
||||
// nbits must be a constant expression
|
||||
#define __hazard3_bextm(nbits, rs1, rs2) ({\
|
||||
uint32_t __h3_bextm_rd; \
|
||||
asm (".insn r 0x0b, 0, %3, %0, %1, %2"\
|
||||
: "=r" (__h3_bextm_rd) \
|
||||
: "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\
|
||||
); \
|
||||
__h3_bextm_rd; \
|
||||
})
|
||||
|
||||
// nbits and shamt must be constant expressions
|
||||
#define __hazard3_bextmi(nbits, rs1, shamt) ({\
|
||||
uint32_t __h3_bextmi_rd; \
|
||||
asm (".insn i 0x0b, 0x4, %0, %1, %2"\
|
||||
: "=r" (__h3_bextmi_rd) \
|
||||
: "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \
|
||||
); \
|
||||
__h3_bextmi_rd; \
|
||||
})
|
||||
|
||||
#define __hazard3_block() asm ("slt x0, x0, x0" : : : "memory")
|
||||
|
||||
#define __hazard3_unblock() asm ("slt x0, x0, x1" : : : "memory")
|
||||
|
||||
#endif
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
#include "tb_cxxrtl_io.h"
|
||||
#include "hazard3_instr.h"
|
||||
|
||||
// Smoke test for instructions in the Xh3b extension (Hazard3 custom
|
||||
// bitmanip). Currently these are:
|
||||
|
|
@ -6,27 +7,6 @@
|
|||
// - h3_bextm: multiple bit version of the bext instruction from Zbs (1 to 8 bits)
|
||||
// - h3_bextmi: immediate version of the above (as bexti is to bext)
|
||||
|
||||
// nbits must be a constant expression
|
||||
#define __hazard3_bextm(nbits, rs1, rs2) ({\
|
||||
uint32_t __h3_bextm_rd; \
|
||||
asm (".insn r 0x0b, 0, %3, %0, %1, %2"\
|
||||
: "=r" (__h3_bextm_rd) \
|
||||
: "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\
|
||||
); \
|
||||
__h3_bextm_rd; \
|
||||
})
|
||||
|
||||
// nbits and shamt must be constant expressions
|
||||
#define __hazard3_bextmi(nbits, rs1, shamt) ({\
|
||||
uint32_t __h3_bextmi_rd; \
|
||||
asm (".insn i 0x0b, 0x4, %0, %1, %2"\
|
||||
: "=r" (__h3_bextmi_rd) \
|
||||
: "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \
|
||||
); \
|
||||
__h3_bextmi_rd; \
|
||||
})
|
||||
|
||||
|
||||
// The instruction is just supposed to take a single static size...
|
||||
__attribute__((noinline)) uint32_t bextm_dynamic_width(uint nbits, uint32_t rs1, uint32_t rs2) {
|
||||
switch (nbits) {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,70 @@
|
|||
#include "tb_cxxrtl_io.h"
|
||||
#include "hazard3_instr.h"
|
||||
#include "hazard3_csr.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
// In the single core testbench, the unblock_out signal is just looped back to
|
||||
// unblock_in. Use this to confirm that the unblock is latching, i.e. an
|
||||
// earlier unblock will cause the next block to fall through immediately.
|
||||
//
|
||||
// Also check that a block *without* an earlier unblock will timeout. Testing
|
||||
// of unblock-while-blocked needs two processors.
|
||||
|
||||
/*EXPECTED-OUTPUT***************************************************************
|
||||
|
||||
Test 1: block without prior unblock
|
||||
Timed out
|
||||
Test 2: block with prior unblock
|
||||
Unblocked
|
||||
Test 3: block without prior unblock, again
|
||||
Timed out
|
||||
Test 4: unblock, wfi, block
|
||||
Unblocked
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
void set_timer_wfi_timeout(unsigned int t) {
|
||||
// Use the machine timer to wake if the block instruction gets stuck. This
|
||||
// relies on the fact that WFI wake respects the individual IRQ enables
|
||||
// in mie, but ignores mstatus.mie, so we can use the timer to wake
|
||||
// without getting an interrupt.
|
||||
clear_csr(mstatus, 0x8);
|
||||
set_csr(mie, 0x80);
|
||||
|
||||
// Set timer in future, and ensure the pending bit has cleared (may not be immediate)
|
||||
mm_timer->mtimecmp = mm_timer->mtime + 1000;
|
||||
while (read_csr(mip) & 0x80)
|
||||
;
|
||||
}
|
||||
|
||||
bool block_with_timeout() {
|
||||
set_timer_wfi_timeout(1000);
|
||||
__hazard3_block();
|
||||
bool timed_out = !!(read_csr(mip) & 0x80);
|
||||
clear_csr(mie, 0x80);
|
||||
return timed_out;
|
||||
}
|
||||
|
||||
int main() {
|
||||
tb_puts("Test 1: block without prior unblock\n");
|
||||
tb_puts(block_with_timeout() ? "Timed out\n" : "Unblocked\n");
|
||||
|
||||
// Make sure the unblock latch sets.
|
||||
tb_puts("Test 2: block with prior unblock\n");
|
||||
__hazard3_unblock();
|
||||
tb_puts(block_with_timeout() ? "Timed out\n" : "Unblocked\n");
|
||||
|
||||
// Make sure the unblock latch clears
|
||||
tb_puts("Test 3: block without prior unblock, again\n");
|
||||
tb_puts(block_with_timeout() ? "Timed out\n" : "Unblocked\n");
|
||||
|
||||
// Make sure a WFI does not clear the latch
|
||||
tb_puts("Test 4: unblock, wfi, block\n");
|
||||
__hazard3_unblock();
|
||||
set_timer_wfi_timeout(1000);
|
||||
asm ("wfi");
|
||||
clear_csr(mie, 0x80);
|
||||
tb_puts(block_with_timeout() ? "Timed out\n" : "Unblocked\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue