From 96a9ee18e1d36d40babbcfb05d4fcba812c94065 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Mon, 23 May 2022 12:47:48 +0100 Subject: [PATCH] Add IALIGN exception to non-RVC implementations --- hdl/hazard3_core.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hdl/hazard3_core.v b/hdl/hazard3_core.v index d6c8e26..4662bf3 100644 --- a/hdl/hazard3_core.v +++ b/hdl/hazard3_core.v @@ -708,12 +708,13 @@ end wire [W_ADDR-1:0] m_exception_return_addr; wire [W_EXCEPT-1:0] x_except = - x_csr_illegal_access ? EXCEPT_INSTR_ILLEGAL : - |EXTENSION_A && x_unaligned_addr && d_memop_is_amo ? EXCEPT_STORE_ALIGN : - |EXTENSION_A && x_amo_phase == 3'h4 && x_unaligned_addr? EXCEPT_STORE_ALIGN : - |EXTENSION_A && x_amo_phase == 3'h4 ? EXCEPT_STORE_FAULT : - x_unaligned_addr && x_memop_write ? EXCEPT_STORE_ALIGN : - x_unaligned_addr && !x_memop_write ? EXCEPT_LOAD_ALIGN : d_except; + ~|EXTENSION_C && d_pc[1] ? EXCEPT_INSTR_MISALIGN : + x_csr_illegal_access ? EXCEPT_INSTR_ILLEGAL : + |EXTENSION_A && x_unaligned_addr && d_memop_is_amo ? EXCEPT_STORE_ALIGN : + |EXTENSION_A && x_amo_phase == 3'h4 && x_unaligned_addr? EXCEPT_STORE_ALIGN : + |EXTENSION_A && x_amo_phase == 3'h4 ? EXCEPT_STORE_FAULT : + x_unaligned_addr && x_memop_write ? EXCEPT_STORE_ALIGN : + x_unaligned_addr && !x_memop_write ? EXCEPT_LOAD_ALIGN : d_except; // If an instruction causes an exceptional condition we do not consider it to have retired. wire x_except_counts_as_retire = x_except == EXCEPT_EBREAK || x_except == EXCEPT_MRET || x_except == EXCEPT_ECALL;