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Cut in->out paths on debug halt/resume request 

Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
This commit is contained in:
Luke Wren 2022-03-01 21:14:49 +00:00
parent 5aca1381ac
commit 96c69d0bb0
1 changed files with 15 additions and 5 deletions
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16
hdl/hazard3_csr.v
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@ -837,21 +837,31 @@ assign illegal = (wen_soon || ren_soon) && !decode_match;
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
// Debug run/halt // Debug run/halt
// req_resume_prev is to cut an in->out path from request to trap addr.
reg have_just_reset; reg have_just_reset;
reg step_halt_req; reg step_halt_req;
reg dbg_req_resume_prev;
reg dbg_req_halt_prev;
reg pending_dbg_resume_prev; reg pending_dbg_resume_prev;
wire pending_dbg_resume = (pending_dbg_resume_prev || dbg_req_resume) && debug_mode; wire pending_dbg_resume = (pending_dbg_resume_prev || dbg_req_resume_prev) && debug_mode;
always @ (posedge clk or negedge rst_n) begin always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
have_just_reset <= |DEBUG_SUPPORT; have_just_reset <= |DEBUG_SUPPORT;
step_halt_req <= 1'b0; step_halt_req <= 1'b0;
dbg_req_resume_prev <= 1'b0;
dbg_req_halt_prev <= 1'b0;
pending_dbg_resume_prev <= 1'b0; pending_dbg_resume_prev <= 1'b0;
end else if (DEBUG_SUPPORT) begin end else if (DEBUG_SUPPORT) begin
if (instr_ret) if (instr_ret)
have_just_reset <= 1'b0; have_just_reset <= 1'b0;
// Just a delayed version of the request from outside of the core.
// Delay is fine because the DM awaits ack before deasserting.
dbg_req_resume_prev <= dbg_req_resume;
dbg_req_halt_prev <= dbg_req_halt;
if (debug_mode) begin if (debug_mode) begin
step_halt_req <= 1'b0; step_halt_req <= 1'b0;
end else if (dcsr_step && (instr_ret || (trap_enter_vld && trap_enter_rdy))) begin end else if (dcsr_step && (instr_ret || (trap_enter_vld && trap_enter_rdy))) begin
@ -898,7 +908,7 @@ wire want_halt_except = DEBUG_SUPPORT && !debug_mode && (
// load/store address phase) because at that point we can't suppress the bus // load/store address phase) because at that point we can't suppress the bus
// access.. // access..
wire want_halt_irq_if_no_exception = DEBUG_SUPPORT && !debug_mode && !want_halt_except && ( wire want_halt_irq_if_no_exception = DEBUG_SUPPORT && !debug_mode && !want_halt_except && (
(dbg_req_halt && !delay_irq_entry) || (dbg_req_halt_prev && !delay_irq_entry) ||
(dbg_req_halt_on_reset && have_just_reset) || (dbg_req_halt_on_reset && have_just_reset) ||
step_halt_req step_halt_req
); );
@ -912,7 +922,7 @@ wire want_halt_irq = want_halt_irq_if_no_exception && !halt_delayed_by_exception
assign dcause_next = assign dcause_next =
// Trigger would be highest priority if implemented // Trigger would be highest priority if implemented
except == EXCEPT_EBREAK ? 3'h1 : // ebreak (priority 3) except == EXCEPT_EBREAK ? 3'h1 : // ebreak (priority 3)
dbg_req_halt || (dbg_req_halt_on_reset && have_just_reset) ? 3'h3 : // halt or reset-halt (priority 1, 2) dbg_req_halt_prev || (dbg_req_halt_on_reset && have_just_reset) ? 3'h3 : // halt or reset-halt (priority 1, 2)
3'h4; // single-step (priority 0) 3'h4; // single-step (priority 0)
assign enter_debug_mode = !debug_mode && (want_halt_irq || want_halt_except) && trap_enter_rdy; assign enter_debug_mode = !debug_mode && (want_halt_irq || want_halt_except) && trap_enter_rdy;