diff --git a/hdl/hazard3_decode.v b/hdl/hazard3_decode.v index 8851b4e..39c6dcd 100644 --- a/hdl/hazard3_decode.v +++ b/hdl/hazard3_decode.v @@ -207,124 +207,124 @@ always @ (*) begin d_funct7_32b = fd_cir[31:25]; casez (d_instr) - RV_BEQ: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_ZERO; end - RV_BNE: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_NZERO; end - RV_BLT: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_NZERO; end - RV_BGE: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_ZERO; end - RV_BLTU: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_NZERO; end - RV_BGEU: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_ZERO; end - RV_JALR: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_aluop = ALUOP_ADD; d_alusrc_a = ALUSRCA_PC; d_alusrc_b = ALUSRCB_IMM; d_imm = d_instr_is_32bit ? 32'h4 : 32'h2; end - RV_JAL: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_rs1 = X0; d_rs2 = X0; d_aluop = ALUOP_ADD; d_alusrc_a = ALUSRCA_PC; d_alusrc_b = ALUSRCB_IMM; d_imm = d_instr_is_32bit ? 32'h4 : 32'h2; end - RV_LUI: begin d_aluop = ALUOP_RS2; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_rs1 = X0; end - RV_AUIPC: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_aluop = ALUOP_ADD; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_alusrc_a = ALUSRCA_PC; d_rs1 = X0; end - RV_ADDI: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_SLLI: begin d_aluop = ALUOP_SLL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_SLTI: begin d_aluop = ALUOP_LT; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_SLTIU: begin d_aluop = ALUOP_LTU; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_XORI: begin d_aluop = ALUOP_XOR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_SRLI: begin d_aluop = ALUOP_SRL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_SRAI: begin d_aluop = ALUOP_SRA; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_ORI: begin d_aluop = ALUOP_OR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_ANDI: begin d_aluop = ALUOP_AND; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end - RV_ADD: begin d_aluop = ALUOP_ADD; end - RV_SUB: begin d_aluop = ALUOP_SUB; end - RV_SLL: begin d_aluop = ALUOP_SLL; end - RV_SLT: begin d_aluop = ALUOP_LT; end - RV_SLTU: begin d_aluop = ALUOP_LTU; end - RV_XOR: begin d_aluop = ALUOP_XOR; end - RV_SRL: begin d_aluop = ALUOP_SRL; end - RV_SRA: begin d_aluop = ALUOP_SRA; end - RV_OR: begin d_aluop = ALUOP_OR; end - RV_AND: begin d_aluop = ALUOP_AND; end - RV_LB: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LB; end - RV_LH: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LH; end - RV_LW: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LW; end - RV_LBU: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LBU; end - RV_LHU: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LHU; end - RV_SB: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SB; d_rd = X0; end - RV_SH: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SH; d_rd = X0; end - RV_SW: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SW; d_rd = X0; end + `RVOPC_BEQ: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_ZERO; end + `RVOPC_BNE: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_SUB; d_branchcond = BCOND_NZERO; end + `RVOPC_BLT: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_NZERO; end + `RVOPC_BGE: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LT; d_branchcond = BCOND_ZERO; end + `RVOPC_BLTU: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_NZERO; end + `RVOPC_BGEU: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_rd = X0; d_aluop = ALUOP_LTU; d_branchcond = BCOND_ZERO; end + `RVOPC_JALR: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_aluop = ALUOP_ADD; d_alusrc_a = ALUSRCA_PC; d_alusrc_b = ALUSRCB_IMM; d_imm = d_instr_is_32bit ? 32'h4 : 32'h2; end + `RVOPC_JAL: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_rs1 = X0; d_rs2 = X0; d_aluop = ALUOP_ADD; d_alusrc_a = ALUSRCA_PC; d_alusrc_b = ALUSRCB_IMM; d_imm = d_instr_is_32bit ? 32'h4 : 32'h2; end + `RVOPC_LUI: begin d_aluop = ALUOP_RS2; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_rs1 = X0; end + `RVOPC_AUIPC: begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_aluop = ALUOP_ADD; d_imm = d_imm_u; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; d_alusrc_a = ALUSRCA_PC; d_rs1 = X0; end + `RVOPC_ADDI: begin d_aluop = ALUOP_ADD; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_SLLI: begin d_aluop = ALUOP_SLL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_SLTI: begin d_aluop = ALUOP_LT; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_SLTIU: begin d_aluop = ALUOP_LTU; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_XORI: begin d_aluop = ALUOP_XOR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_SRLI: begin d_aluop = ALUOP_SRL; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_SRAI: begin d_aluop = ALUOP_SRA; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_ORI: begin d_aluop = ALUOP_OR; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_ANDI: begin d_aluop = ALUOP_AND; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; d_rs2 = X0; end + `RVOPC_ADD: begin d_aluop = ALUOP_ADD; end + `RVOPC_SUB: begin d_aluop = ALUOP_SUB; end + `RVOPC_SLL: begin d_aluop = ALUOP_SLL; end + `RVOPC_SLT: begin d_aluop = ALUOP_LT; end + `RVOPC_SLTU: begin d_aluop = ALUOP_LTU; end + `RVOPC_XOR: begin d_aluop = ALUOP_XOR; end + `RVOPC_SRL: begin d_aluop = ALUOP_SRL; end + `RVOPC_SRA: begin d_aluop = ALUOP_SRA; end + `RVOPC_OR: begin d_aluop = ALUOP_OR; end + `RVOPC_AND: begin d_aluop = ALUOP_AND; end + `RVOPC_LB: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LB; end + `RVOPC_LH: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LH; end + `RVOPC_LW: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LW; end + `RVOPC_LBU: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LBU; end + `RVOPC_LHU: begin d_addr_is_regoffs = 1'b1; d_rs2 = X0; d_memop = MEMOP_LHU; end + `RVOPC_SB: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SB; d_rd = X0; end + `RVOPC_SH: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SH; d_rd = X0; end + `RVOPC_SW: begin d_addr_is_regoffs = 1'b1; d_aluop = ALUOP_RS2; d_memop = MEMOP_SW; d_rd = X0; end - RV_MUL: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MUL; end else begin d_invalid_32bit = 1'b1; end - RV_MULH: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULH; end else begin d_invalid_32bit = 1'b1; end - RV_MULHSU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHSU; end else begin d_invalid_32bit = 1'b1; end - RV_MULHU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHU; end else begin d_invalid_32bit = 1'b1; end - RV_DIV: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIV; end else begin d_invalid_32bit = 1'b1; end - RV_DIVU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIVU; end else begin d_invalid_32bit = 1'b1; end - RV_REM: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REM; end else begin d_invalid_32bit = 1'b1; end - RV_REMU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REMU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MUL: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MUL; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MULH: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULH; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MULHSU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHSU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MULHU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_MULHU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_DIV: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIV; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_DIVU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_DIVU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_REM: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_REMU: if (EXTENSION_M) begin d_aluop = ALUOP_MULDIV; d_mulop = M_OP_REMU; end else begin d_invalid_32bit = 1'b1; end - RV_LR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_LR_W; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_SC_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_SC_W; d_aluop = ALUOP_RS2; end else begin d_invalid_32bit = 1'b1; end - RV_AMOSWAP_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_RS2; end else begin d_invalid_32bit = 1'b1; end - RV_AMOADD_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_ADD; end else begin d_invalid_32bit = 1'b1; end - RV_AMOXOR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_XOR; end else begin d_invalid_32bit = 1'b1; end - RV_AMOAND_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_AND; end else begin d_invalid_32bit = 1'b1; end - RV_AMOOR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_OR; end else begin d_invalid_32bit = 1'b1; end - RV_AMOMIN_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MIN; end else begin d_invalid_32bit = 1'b1; end - RV_AMOMAX_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MAX; end else begin d_invalid_32bit = 1'b1; end - RV_AMOMINU_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MINU; end else begin d_invalid_32bit = 1'b1; end - RV_AMOMAXU_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MAXU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_LR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_LR_W; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_SC_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_SC_W; d_aluop = ALUOP_RS2; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOSWAP_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_RS2; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOADD_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_ADD; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOXOR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_XOR; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOAND_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_AND; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOOR_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_OR; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOMIN_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MIN; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOMAX_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MAX; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOMINU_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MINU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_AMOMAXU_W: if (EXTENSION_A) begin d_addr_is_regoffs = 1'b1; d_memop = MEMOP_AMO; d_aluop = ALUOP_MAXU; end else begin d_invalid_32bit = 1'b1; end - RV_SH1ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SHXADD; end else begin d_invalid_32bit = 1'b1; end - RV_SH2ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SHXADD; end else begin d_invalid_32bit = 1'b1; end - RV_SH3ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SHXADD; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_SH1ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SHXADD; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_SH2ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SHXADD; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_SH3ADD: if (EXTENSION_ZBA) begin d_aluop = ALUOP_SHXADD; end else begin d_invalid_32bit = 1'b1; end - RV_ANDN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ANDN; end else begin d_invalid_32bit = 1'b1; end - RV_CLZ: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CLZ; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_CPOP: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CPOP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_CTZ: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CTZ; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_MAX: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MAX; end else begin d_invalid_32bit = 1'b1; end - RV_MAXU: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MAXU; end else begin d_invalid_32bit = 1'b1; end - RV_MIN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MIN; end else begin d_invalid_32bit = 1'b1; end - RV_MINU: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MINU; end else begin d_invalid_32bit = 1'b1; end - RV_ORC_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ORC_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_ORN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ORN; end else begin d_invalid_32bit = 1'b1; end - RV_REV8: if (EXTENSION_ZBB) begin d_aluop = ALUOP_REV8; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_ROL: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROL; end else begin d_invalid_32bit = 1'b1; end - RV_ROR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROR; end else begin d_invalid_32bit = 1'b1; end - RV_RORI: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROR; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end - RV_SEXT_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_SEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_XNOR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_XNOR; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ANDN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ANDN; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CLZ: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CLZ; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CPOP: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CPOP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CTZ: if (EXTENSION_ZBB) begin d_aluop = ALUOP_CTZ; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MAX: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MAX; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MAXU: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MAXU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MIN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MIN; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MINU: if (EXTENSION_ZBB) begin d_aluop = ALUOP_MINU; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ORC_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ORC_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ORN: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ORN; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_REV8: if (EXTENSION_ZBB) begin d_aluop = ALUOP_REV8; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ROL: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROL; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ROR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROR; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_RORI: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ROR; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_SEXT_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_SEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_XNOR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_XNOR; end else begin d_invalid_32bit = 1'b1; end // Note: ZEXT_H is a subset of PACK from Zbkb. This is fine as long as // this case appears first, since Zbkb implies Zbb on Hazard3. - RV_ZEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ZEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ZEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ZEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_CLMUL: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end - RV_CLMULH: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end - RV_CLMULR: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CLMUL: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CLMULH: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CLMULR: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end - RV_BCLR: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BCLR; end else begin d_invalid_32bit = 1'b1; end - RV_BCLRI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BCLR; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end - RV_BEXT: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BEXT; end else begin d_invalid_32bit = 1'b1; end - RV_BEXTI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BEXT; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end - RV_BINV: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BINV; end else begin d_invalid_32bit = 1'b1; end - RV_BINVI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BINV; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end - RV_BSET: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; end else begin d_invalid_32bit = 1'b1; end - RV_BSETI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BCLR: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BCLR; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BCLRI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BCLR; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BEXT: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BEXT; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BEXTI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BEXT; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BINV: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BINV; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BINVI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BINV; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BSET: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BSETI: if (EXTENSION_ZBS) begin d_aluop = ALUOP_BSET; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end - RV_PACK: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_PACK; end else begin d_invalid_32bit = 1'b1; end - RV_PACKH: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_PACKH; end else begin d_invalid_32bit = 1'b1; end - RV_BREV8: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_BREV8; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_UNZIP: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_UNZIP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_ZIP: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_ZIP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_PACK: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_PACK; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_PACKH: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_PACKH; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_BREV8: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_BREV8; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_UNZIP: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_UNZIP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ZIP: if (EXTENSION_ZBKB) begin d_aluop = ALUOP_ZIP; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end - RV_H3_BEXTM: if (EXTENSION_XH3B) begin d_aluop = ALUOP_BEXTM; end else begin d_invalid_32bit = 1'b1; end - RV_H3_BEXTMI: if (EXTENSION_XH3B) begin d_aluop = ALUOP_BEXTM; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_H3_BEXTM: if (EXTENSION_XH3B) begin d_aluop = ALUOP_BEXTM; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_H3_BEXTMI: if (EXTENSION_XH3B) begin d_aluop = ALUOP_BEXTM; d_rs2 = X0; d_imm = d_imm_i; d_alusrc_b = ALUSRCB_IMM; end else begin d_invalid_32bit = 1'b1; end - RV_FENCE: begin d_rs2 = X0; end // NOP, note rs1/rd are zero in instruction - RV_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_fence_i = 1'b1; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction - RV_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end - RV_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end - RV_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end - RV_CSRRWI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end - RV_CSRRSI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end - RV_CSRRCI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end - RV_ECALL: if (HAVE_CSR) begin d_except = m_mode || !U_MODE ? EXCEPT_ECALL_M : EXCEPT_ECALL_U; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end - RV_EBREAK: if (HAVE_CSR) begin d_except = EXCEPT_EBREAK; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end - RV_MRET: if (HAVE_CSR && m_mode) begin d_except = EXCEPT_MRET; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end - RV_WFI: if (HAVE_CSR && permit_wfi) begin d_wfi = 1'b1; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_FENCE: begin d_rs2 = X0; end // NOP, note rs1/rd are zero in instruction + `RVOPC_FENCE_I: if (EXTENSION_ZIFENCEI) begin d_invalid_32bit = DEBUG_SUPPORT && debug_mode; d_branchcond = BCOND_ALWAYS; d_fence_i = 1'b1; end else begin d_invalid_32bit = 1'b1; end // note rs1/rs2/rd are zero in instruction + `RVOPC_CSRRW: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CSRRS: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CSRRC: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CSRRWI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = 1'b1 ; d_csr_ren = |d_rd; d_csr_wtype = CSR_WTYPE_W; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CSRRSI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_S; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_CSRRCI: if (HAVE_CSR) begin d_imm = d_imm_i; d_csr_wen = |d_rs1; d_csr_ren = 1'b1 ; d_csr_wtype = CSR_WTYPE_C; d_csr_w_imm = 1'b1; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_ECALL: if (HAVE_CSR) begin d_except = m_mode || !U_MODE ? EXCEPT_ECALL_M : EXCEPT_ECALL_U; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_EBREAK: if (HAVE_CSR) begin d_except = EXCEPT_EBREAK; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_MRET: if (HAVE_CSR && m_mode) begin d_except = EXCEPT_MRET; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end + `RVOPC_WFI: if (HAVE_CSR && permit_wfi) begin d_wfi = 1'b1; d_rs2 = X0; d_rs1 = X0; d_rd = X0; end else begin d_invalid_32bit = 1'b1; end default: begin d_invalid_32bit = 1'b1; end endcase diff --git a/hdl/hazard3_frontend.v b/hdl/hazard3_frontend.v index ae1302f..e0faa03 100644 --- a/hdl/hazard3_frontend.v +++ b/hdl/hazard3_frontend.v @@ -559,8 +559,8 @@ always @ (*) begin casez ({|EXTENSION_C, next_instr}) // -> addi rd, x0, imm: - {1'b1, 16'hzzzz, RV_C_LI }: predecode_rs1_fine = 5'd0; - {1'b1, 16'hzzzz, RV_C_MV }: begin + {1'b1, 16'hzzzz, `RVOPC_C_LI}: predecode_rs1_fine = 5'd0; + {1'b1, 16'hzzzz, `RVOPC_C_MV}: begin if (next_instr[6:2] == 5'd0) begin // c.jr has rs1 as normal predecode_rs1_fine = predecode_rs1_coarse; @@ -573,9 +573,9 @@ always @ (*) begin endcase casez ({|EXTENSION_C, next_instr}) - {1'b1, 16'hzzzz, RV_C_BEQZ}: predecode_rs2_fine = 5'd0; // -> beq rs1, x0, label - {1'b1, 16'hzzzz, RV_C_BNEZ}: predecode_rs2_fine = 5'd0; // -> bne rs1, x0, label - default: predecode_rs2_fine = predecode_rs2_coarse; + {1'b1, 16'hzzzz, `RVOPC_C_BEQZ}: predecode_rs2_fine = 5'd0; // -> beq rs1, x0, label + {1'b1, 16'hzzzz, `RVOPC_C_BNEZ}: predecode_rs2_fine = 5'd0; // -> bne rs1, x0, label + default: predecode_rs2_fine = predecode_rs2_coarse; endcase diff --git a/hdl/hazard3_instr_decompress.v b/hdl/hazard3_instr_decompress.v index 255445f..7d8aba6 100644 --- a/hdl/hazard3_instr_decompress.v +++ b/hdl/hazard3_instr_decompress.v @@ -83,60 +83,60 @@ end else begin: instr_decompress invalid = 1'b0; casez (instr_in[15:0]) 16'h0: invalid = 1'b1; - RV_C_ADDI4SPN: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_s) | rfmt_rs1(5'h2) + `RVOPC_C_ADDI4SPN: instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(rd_s) | rfmt_rs1(5'h2) | {2'h0, instr_in[10:7], instr_in[12:11], instr_in[5], instr_in[6], 2'b00, 20'h00000}; - RV_C_LW: instr_out = RV_NOZ_LW | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) + `RVOPC_C_LW: instr_out = `RVOPC_NOZ_LW | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | {5'h00, instr_in[5], instr_in[12:10], instr_in[6], 2'b00, 20'h00000}; - RV_C_SW: instr_out = RV_NOZ_SW | rfmt_rs2(rs2_s) | rfmt_rs1(rs1_s) + `RVOPC_C_SW: instr_out = `RVOPC_NOZ_SW | rfmt_rs2(rs2_s) | rfmt_rs1(rs1_s) | {5'h00, instr_in[5], instr_in[12], 13'h000, instr_in[11:10], instr_in[6], 2'b00, 7'h00}; - RV_C_ADDI: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | imm_ci; - RV_C_JAL: instr_out = RV_NOZ_JAL | rfmt_rd(5'h1) | imm_cj; - RV_C_J: instr_out = RV_NOZ_JAL | rfmt_rd(5'h0) | imm_cj; - RV_C_LI: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_l) | imm_ci; - RV_C_LUI: begin + `RVOPC_C_ADDI: instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | imm_ci; + `RVOPC_C_JAL: instr_out = `RVOPC_NOZ_JAL | rfmt_rd(5'h1) | imm_cj; + `RVOPC_C_J: instr_out = `RVOPC_NOZ_JAL | rfmt_rd(5'h0) | imm_cj; + `RVOPC_C_LI: instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(rd_l) | imm_ci; + `RVOPC_C_LUI: begin if (rd_l == 5'h2) begin // addi16sp - instr_out = RV_NOZ_ADDI | rfmt_rd(5'h2) | rfmt_rs1(5'h2) | + instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(5'h2) | rfmt_rs1(5'h2) | {{3{instr_in[12]}}, instr_in[4:3], instr_in[5], instr_in[2], instr_in[6], 24'h000000}; end else begin - instr_out = RV_NOZ_LUI | rfmt_rd(rd_l) | {{15{instr_in[12]}}, instr_in[6:2], 12'h000}; + instr_out = `RVOPC_NOZ_LUI | rfmt_rd(rd_l) | {{15{instr_in[12]}}, instr_in[6:2], 12'h000}; end invalid = ~|{instr_in[12], instr_in[6:2]}; // RESERVED if imm == 0 end - RV_C_SLLI: instr_out = RV_NOZ_SLLI | rfmt_rd(rs1_l) | rfmt_rs1(rs1_l) | imm_ci; - RV_C_SRAI: instr_out = RV_NOZ_SRAI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci; - RV_C_SRLI: instr_out = RV_NOZ_SRLI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci; - RV_C_ANDI: instr_out = RV_NOZ_ANDI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci; - RV_C_AND: instr_out = RV_NOZ_AND | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); - RV_C_OR: instr_out = RV_NOZ_OR | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); - RV_C_XOR: instr_out = RV_NOZ_XOR | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); - RV_C_SUB: instr_out = RV_NOZ_SUB | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); - RV_C_ADD: begin + `RVOPC_C_SLLI: instr_out = `RVOPC_NOZ_SLLI | rfmt_rd(rs1_l) | rfmt_rs1(rs1_l) | imm_ci; + `RVOPC_C_SRAI: instr_out = `RVOPC_NOZ_SRAI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci; + `RVOPC_C_SRLI: instr_out = `RVOPC_NOZ_SRLI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci; + `RVOPC_C_ANDI: instr_out = `RVOPC_NOZ_ANDI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci; + `RVOPC_C_AND: instr_out = `RVOPC_NOZ_AND | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); + `RVOPC_C_OR: instr_out = `RVOPC_NOZ_OR | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); + `RVOPC_C_XOR: instr_out = `RVOPC_NOZ_XOR | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); + `RVOPC_C_SUB: instr_out = `RVOPC_NOZ_SUB | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s); + `RVOPC_C_ADD: begin if (|rs2_l) begin - instr_out = RV_NOZ_ADD | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | rfmt_rs2(rs2_l); + instr_out = `RVOPC_NOZ_ADD | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | rfmt_rs2(rs2_l); end else if (|rs1_l) begin // jalr - instr_out = RV_NOZ_JALR | rfmt_rd(5'h1) | rfmt_rs1(rs1_l); + instr_out = `RVOPC_NOZ_JALR | rfmt_rd(5'h1) | rfmt_rs1(rs1_l); end else begin // ebreak - instr_out = RV_NOZ_EBREAK; + instr_out = `RVOPC_NOZ_EBREAK; end end - RV_C_MV: begin + `RVOPC_C_MV: begin if (|rs2_l) begin // mv - instr_out = RV_NOZ_ADD | rfmt_rd(rd_l) | rfmt_rs2(rs2_l); + instr_out = `RVOPC_NOZ_ADD | rfmt_rd(rd_l) | rfmt_rs2(rs2_l); end else begin // jr - instr_out = RV_NOZ_JALR | rfmt_rs1(rs1_l); + instr_out = `RVOPC_NOZ_JALR | rfmt_rs1(rs1_l); invalid = ~|rs1_l; // RESERVED end end - RV_C_LWSP: begin - instr_out = RV_NOZ_LW | rfmt_rd(rd_l) | rfmt_rs1(5'h2) | + `RVOPC_C_LWSP: begin + instr_out = `RVOPC_NOZ_LW | rfmt_rd(rd_l) | rfmt_rs1(5'h2) | {4'h0, instr_in[3:2], instr_in[12], instr_in[6:4], 2'b00, 20'h00000}; invalid = ~|rd_l; // RESERVED end - RV_C_SWSP: instr_out = RV_NOZ_SW | rfmt_rs2(rs2_l) | rfmt_rs1(5'h2) + `RVOPC_C_SWSP: instr_out = `RVOPC_NOZ_SW | rfmt_rs2(rs2_l) | rfmt_rs1(5'h2) | {4'h0, instr_in[8:7], instr_in[12], 13'h0000, instr_in[11:9], 2'b00, 7'h00}; - RV_C_BEQZ: instr_out = RV_NOZ_BEQ | rfmt_rs1(rs1_s) | imm_cb; - RV_C_BNEZ: instr_out = RV_NOZ_BNE | rfmt_rs1(rs1_s) | imm_cb; + `RVOPC_C_BEQZ: instr_out = `RVOPC_NOZ_BEQ | rfmt_rs1(rs1_s) | imm_cb; + `RVOPC_C_BNEZ: instr_out = `RVOPC_NOZ_BNE | rfmt_rs1(rs1_s) | imm_cb; default: invalid = 1'b1; endcase end diff --git a/hdl/rv_opcodes.vh b/hdl/rv_opcodes.vh index d2fdb0c..41d08a0 100644 --- a/hdl/rv_opcodes.vh +++ b/hdl/rv_opcodes.vh @@ -1,5 +1,5 @@ /*****************************************************************************\ -| Copyright (C) 2021 Luke Wren | +| Copyright (C) 2021-2022 Luke Wren | | SPDX-License-Identifier: Apache-2.0 | \*****************************************************************************/ @@ -10,216 +10,221 @@ localparam RV_RS2_BITS = 5; localparam RV_RD_LSB = 7; localparam RV_RD_BITS = 5; +// Note: these are preprocessor macros, rather than the usual localparams, +// because it's quite difficult to get a definitive citation from 1364-2005 +// for whether Z values are propagated through a localparam to a casez. +// Multiple tools complain about it, so just this once I'll use macros. + // Base ISA (some of these are Z now) -localparam RV_BEQ = 32'b?????????????????000?????1100011; -localparam RV_BNE = 32'b?????????????????001?????1100011; -localparam RV_BLT = 32'b?????????????????100?????1100011; -localparam RV_BGE = 32'b?????????????????101?????1100011; -localparam RV_BLTU = 32'b?????????????????110?????1100011; -localparam RV_BGEU = 32'b?????????????????111?????1100011; -localparam RV_JALR = 32'b?????????????????000?????1100111; -localparam RV_JAL = 32'b?????????????????????????1101111; -localparam RV_LUI = 32'b?????????????????????????0110111; -localparam RV_AUIPC = 32'b?????????????????????????0010111; -localparam RV_ADDI = 32'b?????????????????000?????0010011; -localparam RV_SLLI = 32'b0000000??????????001?????0010011; -localparam RV_SLTI = 32'b?????????????????010?????0010011; -localparam RV_SLTIU = 32'b?????????????????011?????0010011; -localparam RV_XORI = 32'b?????????????????100?????0010011; -localparam RV_SRLI = 32'b0000000??????????101?????0010011; -localparam RV_SRAI = 32'b0100000??????????101?????0010011; -localparam RV_ORI = 32'b?????????????????110?????0010011; -localparam RV_ANDI = 32'b?????????????????111?????0010011; -localparam RV_ADD = 32'b0000000??????????000?????0110011; -localparam RV_SUB = 32'b0100000??????????000?????0110011; -localparam RV_SLL = 32'b0000000??????????001?????0110011; -localparam RV_SLT = 32'b0000000??????????010?????0110011; -localparam RV_SLTU = 32'b0000000??????????011?????0110011; -localparam RV_XOR = 32'b0000000??????????100?????0110011; -localparam RV_SRL = 32'b0000000??????????101?????0110011; -localparam RV_SRA = 32'b0100000??????????101?????0110011; -localparam RV_OR = 32'b0000000??????????110?????0110011; -localparam RV_AND = 32'b0000000??????????111?????0110011; -localparam RV_LB = 32'b?????????????????000?????0000011; -localparam RV_LH = 32'b?????????????????001?????0000011; -localparam RV_LW = 32'b?????????????????010?????0000011; -localparam RV_LBU = 32'b?????????????????100?????0000011; -localparam RV_LHU = 32'b?????????????????101?????0000011; -localparam RV_SB = 32'b?????????????????000?????0100011; -localparam RV_SH = 32'b?????????????????001?????0100011; -localparam RV_SW = 32'b?????????????????010?????0100011; -localparam RV_FENCE = 32'b????????????00000000000000001111; -localparam RV_FENCE_I = 32'b00000000000000000001000000001111; -localparam RV_ECALL = 32'b00000000000000000000000001110011; -localparam RV_EBREAK = 32'b00000000000100000000000001110011; -localparam RV_CSRRW = 32'b?????????????????001?????1110011; -localparam RV_CSRRS = 32'b?????????????????010?????1110011; -localparam RV_CSRRC = 32'b?????????????????011?????1110011; -localparam RV_CSRRWI = 32'b?????????????????101?????1110011; -localparam RV_CSRRSI = 32'b?????????????????110?????1110011; -localparam RV_CSRRCI = 32'b?????????????????111?????1110011; -localparam RV_MRET = 32'b00110000001000000000000001110011; -localparam RV_SYSTEM = 32'b?????????????????????????1110011; -localparam RV_WFI = 32'b00010000010100000000000001110011; +`define RVOPC_BEQ 32'b?????????????????000?????1100011 +`define RVOPC_BNE 32'b?????????????????001?????1100011 +`define RVOPC_BLT 32'b?????????????????100?????1100011 +`define RVOPC_BGE 32'b?????????????????101?????1100011 +`define RVOPC_BLTU 32'b?????????????????110?????1100011 +`define RVOPC_BGEU 32'b?????????????????111?????1100011 +`define RVOPC_JALR 32'b?????????????????000?????1100111 +`define RVOPC_JAL 32'b?????????????????????????1101111 +`define RVOPC_LUI 32'b?????????????????????????0110111 +`define RVOPC_AUIPC 32'b?????????????????????????0010111 +`define RVOPC_ADDI 32'b?????????????????000?????0010011 +`define RVOPC_SLLI 32'b0000000??????????001?????0010011 +`define RVOPC_SLTI 32'b?????????????????010?????0010011 +`define RVOPC_SLTIU 32'b?????????????????011?????0010011 +`define RVOPC_XORI 32'b?????????????????100?????0010011 +`define RVOPC_SRLI 32'b0000000??????????101?????0010011 +`define RVOPC_SRAI 32'b0100000??????????101?????0010011 +`define RVOPC_ORI 32'b?????????????????110?????0010011 +`define RVOPC_ANDI 32'b?????????????????111?????0010011 +`define RVOPC_ADD 32'b0000000??????????000?????0110011 +`define RVOPC_SUB 32'b0100000??????????000?????0110011 +`define RVOPC_SLL 32'b0000000??????????001?????0110011 +`define RVOPC_SLT 32'b0000000??????????010?????0110011 +`define RVOPC_SLTU 32'b0000000??????????011?????0110011 +`define RVOPC_XOR 32'b0000000??????????100?????0110011 +`define RVOPC_SRL 32'b0000000??????????101?????0110011 +`define RVOPC_SRA 32'b0100000??????????101?????0110011 +`define RVOPC_OR 32'b0000000??????????110?????0110011 +`define RVOPC_AND 32'b0000000??????????111?????0110011 +`define RVOPC_LB 32'b?????????????????000?????0000011 +`define RVOPC_LH 32'b?????????????????001?????0000011 +`define RVOPC_LW 32'b?????????????????010?????0000011 +`define RVOPC_LBU 32'b?????????????????100?????0000011 +`define RVOPC_LHU 32'b?????????????????101?????0000011 +`define RVOPC_SB 32'b?????????????????000?????0100011 +`define RVOPC_SH 32'b?????????????????001?????0100011 +`define RVOPC_SW 32'b?????????????????010?????0100011 +`define RVOPC_FENCE 32'b????????????00000000000000001111 +`define RVOPC_FENCE_I 32'b00000000000000000001000000001111 +`define RVOPC_ECALL 32'b00000000000000000000000001110011 +`define RVOPC_EBREAK 32'b00000000000100000000000001110011 +`define RVOPC_CSRRW 32'b?????????????????001?????1110011 +`define RVOPC_CSRRS 32'b?????????????????010?????1110011 +`define RVOPC_CSRRC 32'b?????????????????011?????1110011 +`define RVOPC_CSRRWI 32'b?????????????????101?????1110011 +`define RVOPC_CSRRSI 32'b?????????????????110?????1110011 +`define RVOPC_CSRRCI 32'b?????????????????111?????1110011 +`define RVOPC_MRET 32'b00110000001000000000000001110011 +`define RVOPC_SYSTEM 32'b?????????????????????????1110011 +`define RVOPC_WFI 32'b00010000010100000000000001110011 // M extension -localparam RV_MUL = 32'b0000001??????????000?????0110011; -localparam RV_MULH = 32'b0000001??????????001?????0110011; -localparam RV_MULHSU = 32'b0000001??????????010?????0110011; -localparam RV_MULHU = 32'b0000001??????????011?????0110011; -localparam RV_DIV = 32'b0000001??????????100?????0110011; -localparam RV_DIVU = 32'b0000001??????????101?????0110011; -localparam RV_REM = 32'b0000001??????????110?????0110011; -localparam RV_REMU = 32'b0000001??????????111?????0110011; +`define RVOPC_MUL 32'b0000001??????????000?????0110011 +`define RVOPC_MULH 32'b0000001??????????001?????0110011 +`define RVOPC_MULHSU 32'b0000001??????????010?????0110011 +`define RVOPC_MULHU 32'b0000001??????????011?????0110011 +`define RVOPC_DIV 32'b0000001??????????100?????0110011 +`define RVOPC_DIVU 32'b0000001??????????101?????0110011 +`define RVOPC_REM 32'b0000001??????????110?????0110011 +`define RVOPC_REMU 32'b0000001??????????111?????0110011 // A extension -localparam RV_LR_W = 32'b00010??00000?????010?????0101111; -localparam RV_SC_W = 32'b00011????????????010?????0101111; -localparam RV_AMOSWAP_W = 32'b00001????????????010?????0101111; -localparam RV_AMOADD_W = 32'b00000????????????010?????0101111; -localparam RV_AMOXOR_W = 32'b00100????????????010?????0101111; -localparam RV_AMOAND_W = 32'b01100????????????010?????0101111; -localparam RV_AMOOR_W = 32'b01000????????????010?????0101111; -localparam RV_AMOMIN_W = 32'b10000????????????010?????0101111; -localparam RV_AMOMAX_W = 32'b10100????????????010?????0101111; -localparam RV_AMOMINU_W = 32'b11000????????????010?????0101111; -localparam RV_AMOMAXU_W = 32'b11100????????????010?????0101111; +`define RVOPC_LR_W 32'b00010??00000?????010?????0101111 +`define RVOPC_SC_W 32'b00011????????????010?????0101111 +`define RVOPC_AMOSWAP_W 32'b00001????????????010?????0101111 +`define RVOPC_AMOADD_W 32'b00000????????????010?????0101111 +`define RVOPC_AMOXOR_W 32'b00100????????????010?????0101111 +`define RVOPC_AMOAND_W 32'b01100????????????010?????0101111 +`define RVOPC_AMOOR_W 32'b01000????????????010?????0101111 +`define RVOPC_AMOMIN_W 32'b10000????????????010?????0101111 +`define RVOPC_AMOMAX_W 32'b10100????????????010?????0101111 +`define RVOPC_AMOMINU_W 32'b11000????????????010?????0101111 +`define RVOPC_AMOMAXU_W 32'b11100????????????010?????0101111 // Zba (address generation) -localparam RV_SH1ADD = 32'b0010000??????????010?????0110011; -localparam RV_SH2ADD = 32'b0010000??????????100?????0110011; -localparam RV_SH3ADD = 32'b0010000??????????110?????0110011; +`define RVOPC_SH1ADD 32'b0010000??????????010?????0110011 +`define RVOPC_SH2ADD 32'b0010000??????????100?????0110011 +`define RVOPC_SH3ADD 32'b0010000??????????110?????0110011 // Zbb (basic bit manipulation) -localparam RV_ANDN = 32'b0100000??????????111?????0110011; -localparam RV_CLZ = 32'b011000000000?????001?????0010011; -localparam RV_CPOP = 32'b011000000010?????001?????0010011; -localparam RV_CTZ = 32'b011000000001?????001?????0010011; -localparam RV_MAX = 32'b0000101??????????110?????0110011; -localparam RV_MAXU = 32'b0000101??????????111?????0110011; -localparam RV_MIN = 32'b0000101??????????100?????0110011; -localparam RV_MINU = 32'b0000101??????????101?????0110011; -localparam RV_ORC_B = 32'b001010000111?????101?????0010011; -localparam RV_ORN = 32'b0100000??????????110?????0110011; -localparam RV_REV8 = 32'b011010011000?????101?????0010011; -localparam RV_ROL = 32'b0110000??????????001?????0110011; -localparam RV_ROR = 32'b0110000??????????101?????0110011; -localparam RV_RORI = 32'b0110000??????????101?????0010011; -localparam RV_SEXT_B = 32'b011000000100?????001?????0010011; -localparam RV_SEXT_H = 32'b011000000101?????001?????0010011; -localparam RV_XNOR = 32'b0100000??????????100?????0110011; -localparam RV_ZEXT_H = 32'b000010000000?????100?????0110011; +`define RVOPC_ANDN 32'b0100000??????????111?????0110011 +`define RVOPC_CLZ 32'b011000000000?????001?????0010011 +`define RVOPC_CPOP 32'b011000000010?????001?????0010011 +`define RVOPC_CTZ 32'b011000000001?????001?????0010011 +`define RVOPC_MAX 32'b0000101??????????110?????0110011 +`define RVOPC_MAXU 32'b0000101??????????111?????0110011 +`define RVOPC_MIN 32'b0000101??????????100?????0110011 +`define RVOPC_MINU 32'b0000101??????????101?????0110011 +`define RVOPC_ORC_B 32'b001010000111?????101?????0010011 +`define RVOPC_ORN 32'b0100000??????????110?????0110011 +`define RVOPC_REV8 32'b011010011000?????101?????0010011 +`define RVOPC_ROL 32'b0110000??????????001?????0110011 +`define RVOPC_ROR 32'b0110000??????????101?????0110011 +`define RVOPC_RORI 32'b0110000??????????101?????0010011 +`define RVOPC_SEXT_B 32'b011000000100?????001?????0010011 +`define RVOPC_SEXT_H 32'b011000000101?????001?????0010011 +`define RVOPC_XNOR 32'b0100000??????????100?????0110011 +`define RVOPC_ZEXT_H 32'b000010000000?????100?????0110011 // Zbc (carry-less multiply) -localparam RV_CLMUL = 32'b0000101??????????001?????0110011; -localparam RV_CLMULH = 32'b0000101??????????011?????0110011; -localparam RV_CLMULR = 32'b0000101??????????010?????0110011; +`define RVOPC_CLMUL 32'b0000101??????????001?????0110011 +`define RVOPC_CLMULH 32'b0000101??????????011?????0110011 +`define RVOPC_CLMULR 32'b0000101??????????010?????0110011 // Zbs (single-bit manipulation) -localparam RV_BCLR = 32'b0100100??????????001?????0110011; -localparam RV_BCLRI = 32'b0100100??????????001?????0010011; -localparam RV_BEXT = 32'b0100100??????????101?????0110011; -localparam RV_BEXTI = 32'b0100100??????????101?????0010011; -localparam RV_BINV = 32'b0110100??????????001?????0110011; -localparam RV_BINVI = 32'b0110100??????????001?????0010011; -localparam RV_BSET = 32'b0010100??????????001?????0110011; -localparam RV_BSETI = 32'b0010100??????????001?????0010011; +`define RVOPC_BCLR 32'b0100100??????????001?????0110011 +`define RVOPC_BCLRI 32'b0100100??????????001?????0010011 +`define RVOPC_BEXT 32'b0100100??????????101?????0110011 +`define RVOPC_BEXTI 32'b0100100??????????101?????0010011 +`define RVOPC_BINV 32'b0110100??????????001?????0110011 +`define RVOPC_BINVI 32'b0110100??????????001?????0010011 +`define RVOPC_BSET 32'b0010100??????????001?????0110011 +`define RVOPC_BSETI 32'b0010100??????????001?????0010011 // Zbkb (basic bit manipulation for crypto) (minus those in Zbb) -localparam RV_PACK = 32'b0000100??????????100?????0110011; -localparam RV_PACKH = 32'b0000100??????????111?????0110011; -localparam RV_BREV8 = 32'b011010000111?????101?????0010011; -localparam RV_UNZIP = 32'b000010001111?????101?????0010011; -localparam RV_ZIP = 32'b000010001111?????001?????0010011; +`define RVOPC_PACK 32'b0000100??????????100?????0110011 +`define RVOPC_PACKH 32'b0000100??????????111?????0110011 +`define RVOPC_BREV8 32'b011010000111?????101?????0010011 +`define RVOPC_UNZIP 32'b000010001111?????101?????0010011 +`define RVOPC_ZIP 32'b000010001111?????001?????0010011 // Zbkc is a subset of Zbc. // Zbkx (crossbar permutation) -localparam RV_XPERM_B = 32'b0010100??????????100?????0110011; -localparam RV_XPERM_N = 32'b0010100??????????010?????0110011; +`define RVOPC_XPERM_B 32'b0010100??????????100?????0110011 +`define RVOPC_XPERM_N 32'b0010100??????????010?????0110011 // Hazard3 custom instructions // Xh3b (Hazard3 custom bitmanip): currently just a multi-bit version of bext/bexti from Zbs -localparam RV_H3_BEXTM = 32'b000???0??????????000?????0001011; // custom-0 funct3=0 -localparam RV_H3_BEXTMI = 32'b000???0??????????100?????0001011; // custom-0 funct3=4 +`define RVOPC_H3_BEXTM 32'b000???0??????????000?????0001011 // custom-0 funct3=0 +`define RVOPC_H3_BEXTMI 32'b000???0??????????100?????0001011 // custom-0 funct3=4 // C Extension -localparam RV_C_ADDI4SPN = 16'b000???????????00; // *** illegal if imm 0 -localparam RV_C_LW = 16'b010???????????00; -localparam RV_C_SW = 16'b110???????????00; +`define RVOPC_C_ADDI4SPN 16'b000???????????00 // *** illegal if imm 0 +`define RVOPC_C_LW 16'b010???????????00 +`define RVOPC_C_SW 16'b110???????????00 -localparam RV_C_ADDI = 16'b000???????????01; -localparam RV_C_JAL = 16'b001???????????01; -localparam RV_C_J = 16'b101???????????01; -localparam RV_C_LI = 16'b010???????????01; +`define RVOPC_C_ADDI 16'b000???????????01 +`define RVOPC_C_JAL 16'b001???????????01 +`define RVOPC_C_J 16'b101???????????01 +`define RVOPC_C_LI 16'b010???????????01 // addi16sp when rd=2: -localparam RV_C_LUI = 16'b011???????????01; // *** reserved if imm 0 (for both LUI and ADDI16SP) -localparam RV_C_SRLI = 16'b100000????????01; // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE. -localparam RV_C_SRAI = 16'b100001????????01; // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE. -localparam RV_C_ANDI = 16'b100?10????????01; -localparam RV_C_SUB = 16'b100011???00???01; -localparam RV_C_XOR = 16'b100011???01???01; -localparam RV_C_OR = 16'b100011???10???01; -localparam RV_C_AND = 16'b100011???11???01; -localparam RV_C_BEQZ = 16'b110???????????01; -localparam RV_C_BNEZ = 16'b111???????????01; +`define RVOPC_C_LUI 16'b011???????????01 // *** reserved if imm 0 (for both LUI and ADDI16SP) +`define RVOPC_C_SRLI 16'b100000????????01 // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE. +`define RVOPC_C_SRAI 16'b100001????????01 // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE. +`define RVOPC_C_ANDI 16'b100?10????????01 +`define RVOPC_C_SUB 16'b100011???00???01 +`define RVOPC_C_XOR 16'b100011???01???01 +`define RVOPC_C_OR 16'b100011???10???01 +`define RVOPC_C_AND 16'b100011???11???01 +`define RVOPC_C_BEQZ 16'b110???????????01 +`define RVOPC_C_BNEZ 16'b111???????????01 -localparam RV_C_SLLI = 16'b0000??????????10; // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE. +`define RVOPC_C_SLLI 16'b0000??????????10 // On RV32 imm[5] (instr[12]) must be 0, else reserved NSE. // jr if !rs2: -localparam RV_C_MV = 16'b1000??????????10; // *** reserved if JR and !rs1 (instr[11:7]) +`define RVOPC_C_MV 16'b1000??????????10 // *** reserved if JR and !rs1 (instr[11:7]) // jalr if !rs2: -localparam RV_C_ADD = 16'b1001??????????10; // *** EBREAK if !instr[11:2] -localparam RV_C_LWSP = 16'b010???????????10; -localparam RV_C_SWSP = 16'b110???????????10; +`define RVOPC_C_ADD 16'b1001??????????10 // *** EBREAK if !instr[11:2] +`define RVOPC_C_LWSP 16'b010???????????10 +`define RVOPC_C_SWSP 16'b110???????????10 // Copies provided here with 0 instead of ? so that these can be used to build 32-bit instructions in the decompressor -localparam RV_NOZ_BEQ = 32'b00000000000000000000000001100011; -localparam RV_NOZ_BNE = 32'b00000000000000000001000001100011; -localparam RV_NOZ_BLT = 32'b00000000000000000100000001100011; -localparam RV_NOZ_BGE = 32'b00000000000000000101000001100011; -localparam RV_NOZ_BLTU = 32'b00000000000000000110000001100011; -localparam RV_NOZ_BGEU = 32'b00000000000000000111000001100011; -localparam RV_NOZ_JALR = 32'b00000000000000000000000001100111; -localparam RV_NOZ_JAL = 32'b00000000000000000000000001101111; -localparam RV_NOZ_LUI = 32'b00000000000000000000000000110111; -localparam RV_NOZ_AUIPC = 32'b00000000000000000000000000010111; -localparam RV_NOZ_ADDI = 32'b00000000000000000000000000010011; -localparam RV_NOZ_SLLI = 32'b00000000000000000001000000010011; -localparam RV_NOZ_SLTI = 32'b00000000000000000010000000010011; -localparam RV_NOZ_SLTIU = 32'b00000000000000000011000000010011; -localparam RV_NOZ_XORI = 32'b00000000000000000100000000010011; -localparam RV_NOZ_SRLI = 32'b00000000000000000101000000010011; -localparam RV_NOZ_SRAI = 32'b01000000000000000101000000010011; -localparam RV_NOZ_ORI = 32'b00000000000000000110000000010011; -localparam RV_NOZ_ANDI = 32'b00000000000000000111000000010011; -localparam RV_NOZ_ADD = 32'b00000000000000000000000000110011; -localparam RV_NOZ_SUB = 32'b01000000000000000000000000110011; -localparam RV_NOZ_SLL = 32'b00000000000000000001000000110011; -localparam RV_NOZ_SLT = 32'b00000000000000000010000000110011; -localparam RV_NOZ_SLTU = 32'b00000000000000000011000000110011; -localparam RV_NOZ_XOR = 32'b00000000000000000100000000110011; -localparam RV_NOZ_SRL = 32'b00000000000000000101000000110011; -localparam RV_NOZ_SRA = 32'b01000000000000000101000000110011; -localparam RV_NOZ_OR = 32'b00000000000000000110000000110011; -localparam RV_NOZ_AND = 32'b00000000000000000111000000110011; -localparam RV_NOZ_LB = 32'b00000000000000000000000000000011; -localparam RV_NOZ_LH = 32'b00000000000000000001000000000011; -localparam RV_NOZ_LW = 32'b00000000000000000010000000000011; -localparam RV_NOZ_LBU = 32'b00000000000000000100000000000011; -localparam RV_NOZ_LHU = 32'b00000000000000000101000000000011; -localparam RV_NOZ_SB = 32'b00000000000000000000000000100011; -localparam RV_NOZ_SH = 32'b00000000000000000001000000100011; -localparam RV_NOZ_SW = 32'b00000000000000000010000000100011; -localparam RV_NOZ_FENCE = 32'b00000000000000000000000000001111; -localparam RV_NOZ_FENCE_I = 32'b00000000000000000001000000001111; -localparam RV_NOZ_ECALL = 32'b00000000000000000000000001110011; -localparam RV_NOZ_EBREAK = 32'b00000000000100000000000001110011; -localparam RV_NOZ_CSRRW = 32'b00000000000000000001000001110011; -localparam RV_NOZ_CSRRS = 32'b00000000000000000010000001110011; -localparam RV_NOZ_CSRRC = 32'b00000000000000000011000001110011; -localparam RV_NOZ_CSRRWI = 32'b00000000000000000101000001110011; -localparam RV_NOZ_CSRRSI = 32'b00000000000000000110000001110011; -localparam RV_NOZ_CSRRCI = 32'b00000000000000000111000001110011; -localparam RV_NOZ_SYSTEM = 32'b00000000000000000000000001110011; +`define RVOPC_NOZ_BEQ 32'b00000000000000000000000001100011 +`define RVOPC_NOZ_BNE 32'b00000000000000000001000001100011 +`define RVOPC_NOZ_BLT 32'b00000000000000000100000001100011 +`define RVOPC_NOZ_BGE 32'b00000000000000000101000001100011 +`define RVOPC_NOZ_BLTU 32'b00000000000000000110000001100011 +`define RVOPC_NOZ_BGEU 32'b00000000000000000111000001100011 +`define RVOPC_NOZ_JALR 32'b00000000000000000000000001100111 +`define RVOPC_NOZ_JAL 32'b00000000000000000000000001101111 +`define RVOPC_NOZ_LUI 32'b00000000000000000000000000110111 +`define RVOPC_NOZ_AUIPC 32'b00000000000000000000000000010111 +`define RVOPC_NOZ_ADDI 32'b00000000000000000000000000010011 +`define RVOPC_NOZ_SLLI 32'b00000000000000000001000000010011 +`define RVOPC_NOZ_SLTI 32'b00000000000000000010000000010011 +`define RVOPC_NOZ_SLTIU 32'b00000000000000000011000000010011 +`define RVOPC_NOZ_XORI 32'b00000000000000000100000000010011 +`define RVOPC_NOZ_SRLI 32'b00000000000000000101000000010011 +`define RVOPC_NOZ_SRAI 32'b01000000000000000101000000010011 +`define RVOPC_NOZ_ORI 32'b00000000000000000110000000010011 +`define RVOPC_NOZ_ANDI 32'b00000000000000000111000000010011 +`define RVOPC_NOZ_ADD 32'b00000000000000000000000000110011 +`define RVOPC_NOZ_SUB 32'b01000000000000000000000000110011 +`define RVOPC_NOZ_SLL 32'b00000000000000000001000000110011 +`define RVOPC_NOZ_SLT 32'b00000000000000000010000000110011 +`define RVOPC_NOZ_SLTU 32'b00000000000000000011000000110011 +`define RVOPC_NOZ_XOR 32'b00000000000000000100000000110011 +`define RVOPC_NOZ_SRL 32'b00000000000000000101000000110011 +`define RVOPC_NOZ_SRA 32'b01000000000000000101000000110011 +`define RVOPC_NOZ_OR 32'b00000000000000000110000000110011 +`define RVOPC_NOZ_AND 32'b00000000000000000111000000110011 +`define RVOPC_NOZ_LB 32'b00000000000000000000000000000011 +`define RVOPC_NOZ_LH 32'b00000000000000000001000000000011 +`define RVOPC_NOZ_LW 32'b00000000000000000010000000000011 +`define RVOPC_NOZ_LBU 32'b00000000000000000100000000000011 +`define RVOPC_NOZ_LHU 32'b00000000000000000101000000000011 +`define RVOPC_NOZ_SB 32'b00000000000000000000000000100011 +`define RVOPC_NOZ_SH 32'b00000000000000000001000000100011 +`define RVOPC_NOZ_SW 32'b00000000000000000010000000100011 +`define RVOPC_NOZ_FENCE 32'b00000000000000000000000000001111 +`define RVOPC_NOZ_FENCE_I 32'b00000000000000000001000000001111 +`define RVOPC_NOZ_ECALL 32'b00000000000000000000000001110011 +`define RVOPC_NOZ_EBREAK 32'b00000000000100000000000001110011 +`define RVOPC_NOZ_CSRRW 32'b00000000000000000001000001110011 +`define RVOPC_NOZ_CSRRS 32'b00000000000000000010000001110011 +`define RVOPC_NOZ_CSRRC 32'b00000000000000000011000001110011 +`define RVOPC_NOZ_CSRRWI 32'b00000000000000000101000001110011 +`define RVOPC_NOZ_CSRRSI 32'b00000000000000000110000001110011 +`define RVOPC_NOZ_CSRRCI 32'b00000000000000000111000001110011 +`define RVOPC_NOZ_SYSTEM 32'b00000000000000000000000001110011