Add test for IRQ force array
This commit is contained in:
Luke Wren
parent
f47f603595
commit
a44ff9b6f1
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@ -5,6 +5,13 @@
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#include "stdint.h"
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#include "stdbool.h"
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// Should match processor configuration in testbench:
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#define NUM_IRQS 32
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// Declarations for irq_dispatch.S
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extern uintptr_t _external_irq_table[NUM_IRQS];
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extern uint32_t _external_irq_entry_count;
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#define h3irq_array_read(csr, index) (read_set_csr(csr, (index)) >> 16)
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#define h3irq_array_write(csr, index, data) (write_csr(csr, (index) | ((uint32_t)(data) << 16)))
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@ -24,8 +31,17 @@ static inline bool h3irq_pending(unsigned int irq) {
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return h3irq_array_read(hazard3_csr_meipa, irq >> 4) & (1u << (irq & 0xfu));
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}
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static inline bool h3irq_force_pending(unsigned int irq) {
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static inline void h3irq_force_pending(unsigned int irq, bool force) {
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if (force) {
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h3irq_array_set(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
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}
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else {
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h3irq_array_clear(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
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}
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}
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static inline bool h3irq_is_forced(unsigned int irq) {
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return h3irq_array_read(hazard3_csr_meifa, irq >> 4) & (1u << (irq & 0xfu));
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}
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// -1 for no IRQ
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@ -44,4 +60,29 @@ static inline void h3irq_set_priority(unsigned int irq, uint32_t priority) {
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h3irq_array_set(hazard3_csr_meipra, irq >> 2, (priority & 0xfu) << (4 * (irq & 0x3)));
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}
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static inline void h3irq_set_handler(unsigned int irq, void (*handler)(void)) {
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_external_irq_table[irq] = (uintptr_t)handler;
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}
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static inline void global_irq_enable(bool en) {
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// mstatus.mie
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if (en) {
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set_csr(mstatus, 0x8);
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}
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else {
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clear_csr(mstatus, 0x8);
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}
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}
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static inline void external_irq_enable(bool en) {
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// mie.meie
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if (en) {
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set_csr(mie, 0x800);
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}
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else {
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clear_csr(mie, 0x800);
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}
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}
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#endif
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@ -104,7 +104,7 @@ isr_irq\num:
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.word isr_irq\num
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.endm
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#define NUM_IRQS 64
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#define NUM_IRQS 32
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.equ i, 0
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.rept NUM_IRQS
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@ -4,6 +4,7 @@ CCFLAGS := -march=rv32imac_zicsr -Os
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MAX_CYCLES := 1000000
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INCDIR := include ../common
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EXTRA_SRCS_irq_force := ../common/irq_dispatch.S
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EXTRA_SRCS_irq_preempt_set_in_irq := ../common/irq_dispatch.S
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EXTRA_SRCS_irq_set_all_with_pri := ../common/irq_dispatch.S
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@ -0,0 +1,101 @@
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#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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#include "hazard3_irq.h"
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// Fire all IRQs simultaneously, and log the resulting handler calls
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#define mie_meie 0x800u
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void handler(void);
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int main() {
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tb_assert(NUM_IRQS <= 32, "Test invalid for >32 IRQs");
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global_irq_enable(true);
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external_irq_enable(true);
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// Dry run: Check that IRQ force array can be written/read and that it
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// sets the pending array appropriately
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for (int i = 0; i < NUM_IRQS; ++i) {
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h3irq_force_pending(i, true);
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uint32_t expect_pending = i == 31 ? 0xffffffffu : (1u << (i + 1)) - 1;
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tb_assert(
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expect_pending == (
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h3irq_array_read(hazard3_csr_meifa, 0) |
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(h3irq_array_read(hazard3_csr_meifa, 1) << 16)
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),
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"Bad meifa readback\n"
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);
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tb_assert(
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expect_pending == (
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h3irq_array_read(hazard3_csr_meipa, 0) |
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(h3irq_array_read(hazard3_csr_meipa, 1) << 16)
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),
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"Bad meipa readback\n"
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);
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}
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for (int i = 0; i < NUM_IRQS; ++i) {
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h3irq_force_pending(i, false);
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}
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tb_assert(h3irq_array_read(hazard3_csr_meifa, 0) == 0, "Failed to clear meifa\n");
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tb_assert(h3irq_array_read(hazard3_csr_meifa, 1) == 0, "Failed to clear meifa\n");
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tb_assert(h3irq_array_read(hazard3_csr_meipa, 0) == 0, "Failed to clear meipa\n");
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tb_assert(h3irq_array_read(hazard3_csr_meipa, 1) == 0, "Failed to clear meipa\n");
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// Now fire each interrupt for real and make sure that the meinext read
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// clears the force bit as it should, so that each interrupt fires
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// exactly once.
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for (int i = 0; i < NUM_IRQS; ++i) {
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h3irq_enable(i, true);
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h3irq_set_handler(i, handler);
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}
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h3irq_array_write(hazard3_csr_meifa, 0, 0xffffu);
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h3irq_array_write(hazard3_csr_meifa, 1, 0xffffu);
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while (h3irq_pending(31))
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;
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tb_printf("EIRQ vector entered %d times\n", _external_irq_entry_count);
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return 0;
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}
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void handler(void) {
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tb_printf("IRQ %02x\n", h3irq_get_current_irq());
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}
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/*EXPECTED-OUTPUT***************************************************************
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IRQ 00
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IRQ 01
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IRQ 02
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IRQ 03
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IRQ 04
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IRQ 05
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IRQ 06
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IRQ 07
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IRQ 08
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IRQ 09
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IRQ 0a
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IRQ 0b
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IRQ 0c
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IRQ 0d
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IRQ 0e
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IRQ 0f
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IRQ 10
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IRQ 11
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IRQ 12
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IRQ 13
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IRQ 14
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IRQ 15
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IRQ 16
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IRQ 17
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IRQ 18
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IRQ 19
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IRQ 1a
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IRQ 1b
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IRQ 1c
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IRQ 1d
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IRQ 1e
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IRQ 1f
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EIRQ vector entered 2 times
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*******************************************************************************/
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@ -41,22 +41,17 @@ EIRQ vector was entered 16 times
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*******************************************************************************/
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#define MAX_PRIORITY 15
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#define NUM_IRQS 64
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extern uintptr_t _external_irq_table[NUM_IRQS];
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extern uint32_t _external_irq_entry_count;
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void handler(void);
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int main() {
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// Enable external IRQs globally
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set_csr(mstatus, 0x8);
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set_csr(mie, 0x800);
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global_irq_enable(true);
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external_irq_enable(true);
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// Enable one external IRQ at each priority level
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for (int i = 0; i <= MAX_PRIORITY; ++i) {
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h3irq_enable(i, true);
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h3irq_set_priority(i, i);
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_external_irq_table[i] = (uintptr_t)handler;
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h3irq_set_handler(i, handler);
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}
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// Set off the lowest-priority IRQ. The IRQ handler will then set the
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// next-lowest, which will preempt it. So on, up to the highest level,
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@ -57,20 +57,16 @@ EIRQ vector was entered 1 times
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#define PRIORITY_LEVELS 16
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#define NUM_IRQS 32
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extern uintptr_t _external_irq_table[NUM_IRQS];
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extern uint32_t _external_irq_entry_count;
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void handler(void);
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int main() {
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// Enable external IRQs globally
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set_csr(mstatus, 0x8);
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set_csr(mie, 0x800);
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global_irq_enable(true);
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external_irq_enable(true);
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// Enable one external IRQ at each priority level
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for (int i = 0; i < PRIORITY_LEVELS * 2; ++i) {
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h3irq_enable(i, true);
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h3irq_set_priority(i, i / 2);
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_external_irq_table[i] = (uintptr_t)handler;
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h3irq_set_handler(i, handler);
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}
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// Set off the lowest-priority IRQ. The IRQ handler will then set the
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// next-lowest, which will preempt it. So on, up to the highest level,
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