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Set misa.b when all of Zba, Zbb and Zbs are enabled. 

(The B extension has now been ratified as this combination of extensions.)
This commit is contained in:
Luke Wren 2024-05-11 12:13:28 +01:00
parent 6db1edc675
commit a6558e554a
4 changed files with 8 additions and 4 deletions
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6
hdl/hazard3_csr.v
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@ -588,7 +588,11 @@ always @ (*) begin
1'b1, // Integer ISA 1'b1, // Integer ISA
5'd0, // H...D, no 5'd0, // H...D, no
|EXTENSION_C, |EXTENSION_C,
1'b0, &{ // B is now defined as ZbaZbbZbs
|EXTENSION_ZBA,
|EXTENSION_ZBB,
|EXTENSION_ZBS
},
|EXTENSION_A |EXTENSION_A
}; };
end end

2
test/sim/riscv-tests/riscv-tests

@ -1 +1 @@
Subproject commit 5b04c5b81b5d626a2281d820f23af28c19ed0746 Subproject commit 02ad7588bf30199fed22846ad2ae2b69013e1a07

2
test/sim/rvcpp/rv_csr.cpp
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@ -83,7 +83,7 @@ std::optional<ux_t> RVCSR::read(uint16_t addr, bool side_effect) {
return {}; return {};
switch (addr) { switch (addr) {
case CSR_MISA: return 0x40901105; // RV32IMACX + U case CSR_MISA: return 0x40901107u; // RV32IMABCX + U
case CSR_MHARTID: return 0; case CSR_MHARTID: return 0;
case CSR_MARCHID: return 0x1b; // Hazard3 case CSR_MARCHID: return 0x1b; // Hazard3
case CSR_MIMPID: return 0x12345678u; // Match testbench value case CSR_MIMPID: return 0x12345678u; // Match testbench value

2
test/sim/sw_testcases/csr_id.c
View File

@ -11,7 +11,7 @@ marchid: 0000001b
mimpid: 12345678 mimpid: 12345678
mhartid: 00000000 mhartid: 00000000
mconfigptr: 9abcdef0 mconfigptr: 9abcdef0
misa: 40901105 // RV32IMACX + U misa: 40901107 // RV32IMABCX + U
*******************************************************************************/ *******************************************************************************/