diff --git a/.gitmodules b/.gitmodules
index 231c8b1..673ac42 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,6 @@
-[submodule "test/riscv-compliance/riscv-compliance"]
-	path = test/riscv-compliance/riscv-compliance
-	url = https://github.com/riscv/riscv-compliance.git
 [submodule "test/sim/riscv-compliance/riscv-arch-test"]
 	path = test/sim/riscv-compliance/riscv-arch-test
-	url = https://github.com/riscv/riscv-arch-test.git
+	url = https://github.com/wren6991/riscv-arch-test.git
 [submodule "scripts"]
 	path = scripts
 	url = https://github.com/Wren6991/fpgascripts
diff --git a/test/sim/riscv-compliance/Makefile b/test/sim/riscv-compliance/Makefile
deleted file mode 100644
index b959261..0000000
--- a/test/sim/riscv-compliance/Makefile
+++ /dev/null
@@ -1,67 +0,0 @@
-TEST_ARCH = I
-BIN_ARCH = rv32i
-SIM_EXEC = ../tb_cxxrtl/tb
-
-CROSS_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-
-
-TESTLIST= \
-  add-01 \
-  addi-01 \
-  and-01 \
-  andi-01 \
-  auipc-01 \
-  beq-01 \
-  bge-01 \
-  bgeu-01 \
-  blt-01 \
-  bltu-01 \
-  bne-01 \
-  fence-01 \
-  jal-01 \
-  jalr-01 \
-  lb-align-01 \
-  lbu-align-01 \
-  lh-align-01 \
-  lhu-align-01 \
-  lui-01 \
-  lw-align-01 \
-  or-01 \
-  ori-01 \
-  sb-align-01 \
-  sh-align-01 \
-  sll-01 \
-  slli-01 \
-  slt-01 \
-  slti-01 \
-  sltiu-01 \
-  sltu-01 \
-  sra-01 \
-  srai-01 \
-  srl-01 \
-  srli-01 \
-  sub-01 \
-  sw-align-01 \
-  xor-01 \
-  xori-01
-
-.PHONY: all testlist clean $(addprefix test-,$(TESTLIST))
-all: testlist
-
-define make-test-target
-  # Turns out variable expansions inside functions don't work like I thought they did. Oh well this will do
-  test-$1:
-	mkdir -p tmp
-	$(CROSS_PREFIX)gcc -I include -T memmap.ld -nostartfiles -march=$(BIN_ARCH) riscv-arch-test/riscv-test-suite/rv32i_m/$(TEST_ARCH)/src/$1.S -DXLEN=32 -o tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf
-	$(CROSS_PREFIX)objdump -h tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf > tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).dis
-	$(CROSS_PREFIX)objdump -d tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf >> tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).dis
-	$(CROSS_PREFIX)objcopy -O binary tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).elf tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).bin
-	$(SIM_EXEC) --bin tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).bin --vcd tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).vcd --dump 0x400000 0x401000 --cycles 1000000 > tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).log
-	./compare_testvec tmp/$(TEST_ARCH)-$1-on-$(BIN_ARCH).log riscv-arch-test/riscv-test-suite/rv32i_m/$(TEST_ARCH)/references/$1.reference_output
-endef
-
-$(foreach test,$(TESTLIST),$(eval $(call make-test-target,$(test))))
-
-testlist: $(addprefix test-,$(TESTLIST))
-
-clean:
-	rm -rf tmp/
diff --git a/test/sim/riscv-compliance/clean_all.sh b/test/sim/riscv-compliance/clean_all.sh
new file mode 100644
index 0000000..3f64466
--- /dev/null
+++ b/test/sim/riscv-compliance/clean_all.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+
+make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=I clean
+make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=M clean
+make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=C clean
diff --git a/test/sim/riscv-compliance/include/arch_test.h b/test/sim/riscv-compliance/include/arch_test.h
deleted file mode 120000
index 6406897..0000000
--- a/test/sim/riscv-compliance/include/arch_test.h
+++ /dev/null
@@ -1 +0,0 @@
-../riscv-arch-test/riscv-test-env/arch_test.h
\ No newline at end of file
diff --git a/test/sim/riscv-compliance/include/encoding.h b/test/sim/riscv-compliance/include/encoding.h
deleted file mode 120000
index 6f818e9..0000000
--- a/test/sim/riscv-compliance/include/encoding.h
+++ /dev/null
@@ -1 +0,0 @@
-../riscv-arch-test/riscv-test-env/encoding.h
\ No newline at end of file
diff --git a/test/sim/riscv-compliance/include/model_test.h b/test/sim/riscv-compliance/include/model_test.h
deleted file mode 100644
index e33134c..0000000
--- a/test/sim/riscv-compliance/include/model_test.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef _COMPLIANCE_MODEL_H
-#define _COMPLIANCE_MODEL_H
-
-// Modified version of riscv-arch-test/riscv-target/example-target/model_test.h
-
-#define IO_BASE 0x80000000
-#define IO_PRINT_CHAR (IO_BASE + 0x0)
-#define IO_PRINT_U32  (IO_BASE + 0x4)
-#define IO_EXIT       (IO_BASE + 0x8)
-
-#define RVMODEL_DATA_SECTION \
-        .pushsection .testdata,"aw",@progbits;                          \
-        .align 8; .global tohost; tohost: .dword 0;                     \
-        .align 8; .global fromhost; fromhost: .dword 0;                 \
-        .popsection;                                                    \
-        .align 8; .global begin_regstate; begin_regstate:               \
-        .word 128;                                                      \
-        .align 8; .global end_regstate; end_regstate:                   \
-        .word 4;
-
-
-#define RVMODEL_HALT                                                 ;  \
-        li a0, IO_EXIT                                               ;  \
-        li a1, 0                                                     ;  \
-        sw a1, (a0)                                                  ;  \
-        1: j 1b                                                         \
-
-//TODO: declare the start of your signature region here. Nothing else to be used here.
-// The .align 4 ensures that the signature ends at a 16-byte boundary
-#define RVMODEL_DATA_BEGIN                                              \
-  .section .testdata, "aw"; \
-  .align 4; .global begin_signature; begin_signature:
-
-//TODO: declare the end of the signature region here. Add other target specific contents here.
-#define RVMODEL_DATA_END                                                      \
-  .align 4; .global end_signature; end_signature:                             \
-  RVMODEL_DATA_SECTION                                                        
-
-
-#define RVMODEL_BOOT
-
-// _SP = (volatile register)
-//TODO: Macro to output a string to IO
-#define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
-
-// Shut up
-#define RVMODEL_IO_WRITE_STR(_STR, ...)
-
-// #define RVMODEL_IO_WRITE_STR(_SP, _STR)                                 \
-//     .section .data.string;                                              \
-// 20001:                                                                  \
-//     .string _STR;                                                       \
-//     .section .text.init;                                                \
-//     la a0, 20001b;                                                      \
-//     jal FN_WriteStr;
-
-#define RSIZE 4
-// _SP = (volatile register)
-#define LOCAL_IO_PUSH(_SP)                                              \
-    la      _SP,  begin_regstate;                                       \
-    sw      ra,   (1*RSIZE)(_SP);                                       \
-    sw      t0,   (2*RSIZE)(_SP);                                       \
-    sw      t1,   (3*RSIZE)(_SP);                                       \
-    sw      t2,   (4*RSIZE)(_SP);                                       \
-    sw      t3,   (5*RSIZE)(_SP);                                       \
-    sw      t4,   (6*RSIZE)(_SP);                                      \
-    sw      s0,   (7*RSIZE)(_SP);                                      \
-    sw      a0,   (8*RSIZE)(_SP);
-
-// _SP = (volatile register)
-#define LOCAL_IO_POP(_SP)                                               \
-    la      _SP,   begin_regstate;                                      \
-    lw      ra,   (1*RSIZE)(_SP);                                       \
-    lw      t0,   (2*RSIZE)(_SP);                                       \
-    lw      t1,   (3*RSIZE)(_SP);                                       \
-    lw      t2,   (4*RSIZE)(_SP);                                       \
-    lw      t3,   (5*RSIZE)(_SP);                                       \
-    lw      t4,   (6*RSIZE)(_SP);                                       \
-    lw      s0,   (7*RSIZE)(_SP);                                       \
-    lw      a0,   (8*RSIZE)(_SP);
-
-#define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
-
-//RVTEST_IO_ASSERT_SFPR_EQ
-#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
-//RVTEST_IO_ASSERT_DFPR_EQ
-#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
-
-// TODO: specify the routine for setting machine software interrupt
-#define RVMODEL_SET_MSW_INT
-
-// TODO: specify the routine for clearing machine software interrupt
-#define RVMODEL_CLEAR_MSW_INT
-
-// TODO: specify the routine for clearing machine timer interrupt
-#define RVMODEL_CLEAR_MTIMER_INT
-
-// TODO: specify the routine for clearing machine external interrupt
-#define RVMODEL_CLEAR_MEXT_INT
-
-#endif // _COMPLIANCE_MODEL_H
-
diff --git a/test/sim/riscv-compliance/memmap.ld b/test/sim/riscv-compliance/memmap.ld
deleted file mode 100644
index 08b3c77..0000000
--- a/test/sim/riscv-compliance/memmap.ld
+++ /dev/null
@@ -1,41 +0,0 @@
-MEMORY
-  {
-    RAM   (wx) : ORIGIN = 0x0, LENGTH = 4M
-    RESULT (w) : ORIGIN = ORIGIN(RAM) + LENGTH(RAM), LENGTH = 64k
-  }
-
-OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", "elf32-littleriscv")
-OUTPUT_ARCH(riscv)
-ENTRY(_start)
-
-SECTIONS
-{
-  .text : {
-    . = ORIGIN(RAM) + 0x40;
-    PROVIDE (_start = .);
-    *(.text*)
-    . = ALIGN(4);
-  } > RAM
-
-  .rodata : {
-    *(.rodata*)
-    . = ALIGN(4);
-  } > RAM
-
-  .data : {
-    *(.data*)
-    . = ALIGN(4);
-  } > RAM
-  .bss : {
-    *(.bss .bss.*)
-    . = ALIGN(4);
-  } > RAM
-  /* Link testout section to upper memory region */
-  .testdata :
-  {
-    PROVIDE(__testdata_start = .);
-   *(.testdata)
-  } > RESULT
-}
-
-
diff --git a/test/sim/riscv-compliance/riscv-arch-test b/test/sim/riscv-compliance/riscv-arch-test
index b436dd0..759666d 160000
--- a/test/sim/riscv-compliance/riscv-arch-test
+++ b/test/sim/riscv-compliance/riscv-arch-test
@@ -1 +1 @@
-Subproject commit b436dd0939c968f2c3da86bb9b63bb2dfe03b134
+Subproject commit 759666d875dfebd8a5f62134dfb8b70f801d897d
diff --git a/test/sim/riscv-compliance/run_32i.sh b/test/sim/riscv-compliance/run_32i.sh
index 2358ad8..d4eb42d 100755
--- a/test/sim/riscv-compliance/run_32i.sh
+++ b/test/sim/riscv-compliance/run_32i.sh
@@ -1,4 +1,4 @@
 #!/bin/bash
-set -e
+set -ex
 
-make
+make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=I
diff --git a/test/sim/riscv-compliance/run_32ic.sh b/test/sim/riscv-compliance/run_32ic.sh
index 0a218c7..56407ca 100755
--- a/test/sim/riscv-compliance/run_32ic.sh
+++ b/test/sim/riscv-compliance/run_32ic.sh
@@ -1,32 +1,15 @@
 #!/bin/bash
+
 set -e
 
-make TEST_ARCH=C BIN_ARCH=rv32ic TESTLIST=" \
-	cadd-01 \
-	caddi16sp-01 \
-	cand-01 \
-	cbeqz-01 \
-	cjal-01 \
-	cjr-01 \
-	clui-01 \
-	clwsp-01 \
-	cnop-01 \
-	cslli-01 \
-	csrli-01 \
-	csw-01 \
-	cxor-01 \
-	caddi-01 \
-	caddi4spn-01 \
-	candi-01 \
-	cbnez-01 \
-	cj-01 \
-	cjalr-01 \
-	cli-01 \
-	clw-01 \
-	cmv-01 \
-	cor-01 \
-	csrai-01 \
-	csub-01 \
-	cswsp-01 \
-	"
-	#cebreak-01 \
+# Note c.ebreak is expected to fail due to not correctly handling mtval being
+# (legally) hardwired to 0.
+
+# Not clear yet whether this is a configuration issue or an issue with the
+# reference vector generation/selection, but I've debugged the test, and the
+# non-mtval-related parts of the signature are good.
+
+make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=C || echo "
+Note cebreak-01 is an expected failure: test does not correctly handle hardwired mtval.
+
+If you see any other failures, that is a cause for concern."
diff --git a/test/sim/riscv-compliance/run_32im.sh b/test/sim/riscv-compliance/run_32im.sh
index 8622d2b..2aecb57 100755
--- a/test/sim/riscv-compliance/run_32im.sh
+++ b/test/sim/riscv-compliance/run_32im.sh
@@ -1,13 +1,4 @@
 #!/bin/bash
 set -e
 
-make TEST_ARCH=M BIN_ARCH=rv32imc TESTLIST=" \
-	div-01 \
-	divu-01 \
-	rem-01 \
-	remu-01 \
-	mul-01 \
-	mulhu-01 \
-	mulh-01 \
-	mulhsu-01 \
-	"
+make -C riscv-arch-test RISCV_TARGET=hazard3 RISCV_DEVICE=I
diff --git a/test/sim/riscv-compliance/run_all.sh b/test/sim/riscv-compliance/run_all.sh
index e035eff..1c7a382 100755
--- a/test/sim/riscv-compliance/run_all.sh
+++ b/test/sim/riscv-compliance/run_all.sh
@@ -4,5 +4,3 @@ set -e
 ./run_32i.sh
 ./run_32im.sh
 ./run_32ic.sh
-# These are TODO for sw reasons -- not sure why they don't bundle the handlers with the tests
-# ./run_32privilege.sh
diff --git a/test/sim/riscv-compliance/scrape_testvec b/test/sim/riscv-compliance/scrape_testvec
new file mode 100755
index 0000000..376dc2e
--- /dev/null
+++ b/test/sim/riscv-compliance/scrape_testvec
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+
+import sys
+import os
+
+model = []
+
+log_path = sys.argv[1] + ".stdout"
+elf_path = sys.argv[1] + ".elf"
+sigout_path = sys.argv[2]
+
+model_bytes = []
+in_testdata = False
+for l in open(log_path):
+	if l.startswith("Dumping memory"):
+		in_testdata = True
+		continue
+	if in_testdata:
+		try:
+			model_bytes.extend(int(x, 16) for x in l.split(" "))
+		except ValueError:
+			break
+for i in range(len(model_bytes) // 4):
+	model.append(model_bytes[i * 4] | model_bytes[i * 4 + 1] << 8 | model_bytes[i * 4 + 2] << 16 | model_bytes[i * 4 + 3] << 24)
+
+# Trim the output down to size before writing out, by scraping the symbols out
+# of the ELF. New riscv-compliance comparison script doesn't accept trailing data.
+
+# Assume that a suitable objdump is on PATH -- sorry, I couldn't figure out
+# what on earth they were trying to do with the target creation in their
+# Makefile fragments, so it's just been hacked into this script. Problem for
+# future Luke
+
+sig_start_addr = int(os.popen("riscv32-unknown-elf-objdump -t " + elf_path + " | grep begin_signature | head -c8").read(), 16)
+sig_end_addr = int(os.popen("riscv32-unknown-elf-objdump -t " + elf_path + " | grep end_signature | head -c8").read(), 16)
+sig_size_words = (sig_end_addr - sig_start_addr) // 4
+
+model = model[:sig_size_words]
+
+ofile = open(sigout_path, "w")
+for n in model:
+	ofile.write(f"{n:08x}\n")