Also support progbuf in abstractauto.
This commit is contained in:
Luke Wren
parent
46f95f859d
commit
ab0b4a04f0
hdl/debug/dm
test/sim
core_debug
debug_openocd_bitbang
openocd
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@ -284,14 +284,19 @@ always @ (posedge clk or negedge rst_n) begin
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end
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// We only support abstractauto on data0 update (use case is bulk memory read/write)
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reg abstractauto_autoexecdata;
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reg abstractauto_autoexecdata;
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reg [1:0] abstractauto_autoexecprogbuf;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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abstractauto_autoexecdata <= 1'b0;
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abstractauto_autoexecprogbuf <= 2'b00;
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end else if (!dmactive) begin
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abstractauto_autoexecdata <= 1'b0;
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abstractauto_autoexecprogbuf <= 2'b00;
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end else if (dmi_write && dmi_paddr == ADDR_ABSTRACTAUTO) begin
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abstractauto_autoexecdata <= dmi_pwdata[0];
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abstractauto_autoexecprogbuf <= dmi_pwdata[17:16];
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end
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end
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@ -324,7 +329,9 @@ assign abstractcs_busy = acmd_state != S_IDLE;
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wire start_abstract_cmd = abstractcs_cmderr == CMDERR_OK && !abstractcs_busy && (
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(dmi_write && dmi_paddr == ADDR_COMMAND) ||
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((dmi_write || dmi_read) && abstractauto_autoexecdata && dmi_paddr == ADDR_DATA0)
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((dmi_write || dmi_read) && abstractauto_autoexecdata && dmi_paddr == ADDR_DATA0) ||
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((dmi_write || dmi_read) && abstractauto_autoexecprogbuf[0] && dmi_paddr == ADDR_PROGBUF0) ||
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((dmi_write || dmi_read) && abstractauto_autoexecprogbuf[1] && dmi_paddr == ADDR_PROGBUF1)
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);
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wire dmi_access_illegal_when_busy =
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@ -547,8 +554,10 @@ always @ (*) begin
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4'd1 // datacount = 1
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};
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ADDR_ABSTRACTAUTO: dmi_prdata = {
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31'h0,
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abstractauto_autoexecdata // only data0 supported
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14'h0,
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abstractauto_autoexecprogbuf, // only progbuf0,1 present
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15'h0,
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abstractauto_autoexecdata // only data0 present
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};
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ADDR_CONFSTRPTR0: dmi_prdata = 32'h4c296328;
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ADDR_CONFSTRPTR1: dmi_prdata = 32'h20656b75;
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@ -1,38 +0,0 @@
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TOP := hazard3_cpu_2port
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CDEFINES := DUAL_PORT
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CPU_RESET_VECTOR := 32'hc0
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EXTENSION_C := 1
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EXTENSION_M := 1
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DEBUG_SUPPORT := 1
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MULDIV_UNROLL := 2
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MUL_FAST := 1
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REDUCED_BYPASS := 0
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.PHONY: clean tb all run
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all: run
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run: tb
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./tb zero.bin waves.vcd
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SYNTH_CMD += read_verilog -I ../../../hdl $(shell listfiles ../../../hdl/hazard3.f);
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SYNTH_CMD += chparam -set EXTENSION_C $(EXTENSION_C) $(TOP);
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SYNTH_CMD += chparam -set EXTENSION_M $(EXTENSION_M) $(TOP);
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SYNTH_CMD += chparam -set DEBUG_SUPPORT $(DEBUG_SUPPORT) $(TOP);
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SYNTH_CMD += chparam -set CSR_COUNTER 1 $(TOP);
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SYNTH_CMD += chparam -set RESET_VECTOR $(CPU_RESET_VECTOR) $(TOP);
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SYNTH_CMD += chparam -set REDUCED_BYPASS $(REDUCED_BYPASS) $(TOP);
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SYNTH_CMD += chparam -set MULDIV_UNROLL $(MULDIV_UNROLL) $(TOP);
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SYNTH_CMD += chparam -set MUL_FAST $(MUL_FAST) $(TOP);
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SYNTH_CMD += prep -flatten -top $(TOP); async2sync;
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SYNTH_CMD += write_cxxrtl dut.cpp
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dut.cpp:
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yosys -p "$(SYNTH_CMD)" 2>&1 > cxxrtl.log
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clean::
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rm -f dut.cpp cxxrtl.log tb
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tb: dut.cpp
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clang++ -O3 -std=c++14 $(addprefix -D,$(CDEFINES)) -I $(shell yosys-config --datdir)/include tb.cpp -o tb
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@ -1,349 +0,0 @@
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#include <iostream>
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#include <fstream>
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#include <cstdint>
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#include <string>
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#include <algorithm>
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// jesus fuck i forgot how bad iostream formatting was, give me printf or give me death
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#include <stdio.h>
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// Device-under-test model generated by CXXRTL:
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#include "dut.cpp"
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#include <backends/cxxrtl/cxxrtl_vcd.h>
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static const unsigned int MEM_SIZE = 16 * 1024 * 1024;
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uint8_t mem[MEM_SIZE];
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static const unsigned int IO_BASE = 0x80000000;
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enum {
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IO_PRINT_CHAR = 0,
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IO_PRINT_U32 = 4,
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IO_EXIT = 8
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};
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const char *help_str =
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"Usage: tb binfile [vcdfile] [--dump start end] [--cycles n]\n"
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" binfile : Binary to load into start of memory\n"
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" vcdfile : Path to dump waveforms to\n"
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" --dump start end : Print out memory contents between start and end (exclusive)\n"
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" after execution finishes. Can be passed multiple times.\n"
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" --cycles n : Maximum number of cycles to run before exiting.\n"
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;
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void exit_help(std::string errtext = "") {
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std::cerr << errtext << help_str;
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exit(-1);
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}
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struct debug_test_proc {
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int step;
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debug_test_proc() : step(0) {}
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bool operator()(cxxrtl_design::p_hazard3__cpu__2port &top) {
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switch (step) {
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// Request and wait for halt
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case 0:
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top.p_dbg__req__halt.set<bool>(true);
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++step;
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break;
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case 1:
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if (top.p_dbg__halted.get<bool>()) {
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printf("Processor halted\n");
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top.p_dbg__req__halt.set<bool>(false);
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++step;
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}
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break;
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// Load 123 into data0
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case 2:
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top.p_dbg__data0__wdata.set<uint32_t>(123);
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top.p_dbg__data0__wen.set<bool>(true);
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++step;
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break;
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case 3:
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top.p_dbg__data0__wen.set<bool>(false);
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printf("Read DATA0 CSR: %u\n", top.p_dbg__data0__rdata.get<uint32_t>());
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++step;
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break;
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// Inject csrr a0, data0
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case 4:
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top.p_dbg__instr__data__vld.set<bool>(true);
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top.p_dbg__instr__data.set<uint32_t>(0x7b202573u);
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printf(">inject: csrr a0, data0\n");
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++step;
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break;
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// Inject addi a0, a0, 456
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case 5:
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if (top.p_dbg__instr__data__rdy.get<bool>()) {
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printf(">inject: addi a0, a0, 456\n");
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top.p_dbg__instr__data.set<uint32_t>(0x1c850513u);
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++step;
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}
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break;
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// Inject csrw data0, a0
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case 6:
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if (top.p_dbg__instr__data__rdy.get<bool>()) {
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printf(">inject: csrw data0, a0\n");
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top.p_dbg__instr__data.set<uint32_t>(0x7b251073u);
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++step;
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}
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break;
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// Inject illegal instruction (just want to see the wire pulse)
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case 7:
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if (top.p_dbg__instr__data__rdy.get<bool>()) {
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printf(">inject: 2x illegal 0000\n");
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top.p_dbg__instr__data.set<uint32_t>(0);
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++step;
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}
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break;
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case 8:
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if (top.p_dbg__instr__data__rdy.get<bool>()) {
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top.p_dbg__instr__data__vld.set<bool>(false);
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++step;
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}
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break;
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case 9:
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if (top.p_dbg__instr__caught__exception.get<bool>()) {
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printf("Core reported exception during debug execution\n");
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++step;
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}
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break;
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// Inject ebreak (just want to see the wire pulse)
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case 10:
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printf(">inject: ebreak\n");
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top.p_dbg__instr__data__vld.set<bool>(true);
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top.p_dbg__instr__data.set<uint32_t>(0x00100073u);
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++step;
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break;
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case 11:
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if (top.p_dbg__instr__data__rdy.get<bool>()) {
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top.p_dbg__instr__data__vld.set<bool>(false);
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++step;
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}
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break;
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case 12:
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if (top.p_dbg__instr__caught__ebreak.get<bool>()) {
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printf("Core reported ebreak during debug execution\n");
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++step;
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}
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break;
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// Print new data0 value (should be 123 + 456 == 579)
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case 13:
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if (top.p_dbg__instr__data__rdy.get<bool>()) {
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top.p_dbg__instr__data__vld.set<bool>(false);
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printf("Read DATA0 CSR: %u\n", top.p_dbg__data0__rdata.get<uint32_t>());
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++step;
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}
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break;
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// Assert resume request
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case 14:
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top.p_dbg__req__resume.set<bool>(true);
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++step;
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break;
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case 15:
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top.p_dbg__req__resume.set<bool>(false);
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++step;
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break;
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// Exit once request is acknowledged
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case 16:
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if (top.p_dbg__running.get<bool>()) {
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printf("Processor resumed\n");
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return true;
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}
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break;
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default:
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break;
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}
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return false;
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}
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};
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int main(int argc, char **argv) {
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if (argc < 2)
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exit_help();
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bool dump_waves = false;
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std::string waves_path;
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std::vector<std::pair<uint32_t, uint32_t>> dump_ranges;
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int64_t max_cycles = 100000;
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for (int i = 2; i < argc; ++i) {
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std::string s(argv[i]);
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if (i == 2 && s.rfind("--", 0) != 0) {
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// Optional positional argument: vcdfile
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dump_waves = true;
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waves_path = s;
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}
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else if (s == "--dump") {
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if (argc - i < 3)
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exit_help("Option --dump requires 2 arguments\n");
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dump_ranges.push_back(std::pair<uint32_t, uint32_t>(
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std::stoul(argv[i + 1], 0, 0),
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std::stoul(argv[i + 2], 0, 0)
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));;
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i += 2;
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}
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else if (s == "--cycles") {
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if (argc - i < 2)
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exit_help("Option --cycles requires an argument\n");
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max_cycles = std::stol(argv[i + 1], 0, 0);
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i += 1;
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}
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else {
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std::cerr << "Unrecognised argument " << s << "\n";
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exit_help("");
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}
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}
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#ifdef DUAL_PORT
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cxxrtl_design::p_hazard3__cpu__2port top;
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#else
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cxxrtl_design::p_hazard3__cpu__1port top;
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#endif
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debug_test_proc test_step;
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std::fill(std::begin(mem), std::end(mem), 0);
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std::ifstream fd(argv[1], std::ios::binary | std::ios::ate);
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std::streamsize bin_size = fd.tellg();
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if (bin_size > MEM_SIZE) {
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std::cerr << "Binary file (" << bin_size << " bytes) is larger than memory (" << MEM_SIZE << " bytes)\n";
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return -1;
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}
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fd.seekg(0, std::ios::beg);
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fd.read((char*)mem, bin_size);
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std::ofstream waves_fd;
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cxxrtl::vcd_writer vcd;
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if (dump_waves) {
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waves_fd.open(waves_path);
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cxxrtl::debug_items all_debug_items;
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top.debug_info(all_debug_items);
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vcd.timescale(1, "us");
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vcd.add(all_debug_items);
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}
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bool bus_trans = false;
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bool bus_write = false;
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#ifdef DUAL_PORT
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bool bus_trans_i = false;
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uint32_t bus_addr_i = 0;
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#endif
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uint32_t bus_addr = 0;
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uint8_t bus_size = 0;
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// Never generate bus stalls
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#ifdef DUAL_PORT
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top.p_i__hready.set<bool>(true);
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top.p_d__hready.set<bool>(true);
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#else
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top.p_ahblm__hready.set<bool>(true);
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#endif
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// Reset + initial clock pulse
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top.step();
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top.p_clk.set<bool>(true);
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top.step();
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top.p_clk.set<bool>(false);
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top.p_rst__n.set<bool>(true);
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top.step();
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for (int64_t cycle = 0; cycle < max_cycles; ++cycle) {
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top.p_clk.set<bool>(false);
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top.step();
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if (dump_waves)
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vcd.sample(cycle * 2);
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top.p_clk.set<bool>(true);
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top.step();
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// Handle current data phase, then move current address phase to data phase
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uint32_t rdata = 0;
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if (bus_trans && bus_write) {
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#ifdef DUAL_PORT
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uint32_t wdata = top.p_d__hwdata.get<uint32_t>();
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#else
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uint32_t wdata = top.p_ahblm__hwdata.get<uint32_t>();
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#endif
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if (bus_addr <= MEM_SIZE) {
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unsigned int n_bytes = 1u << bus_size;
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// Note we are relying on hazard3's byte lane replication
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for (unsigned int i = 0; i < n_bytes; ++i) {
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mem[bus_addr + i] = wdata >> (8 * i) & 0xffu;
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}
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}
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else if (bus_addr == IO_BASE + IO_PRINT_CHAR) {
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putchar(wdata);
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}
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else if (bus_addr == IO_BASE + IO_PRINT_U32) {
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printf("%08x\n", wdata);
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}
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else if (bus_addr == IO_BASE + IO_EXIT) {
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printf("CPU requested halt. Exit code %d\n", wdata);
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printf("Ran for %ld cycles\n", cycle + 1);
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break;
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}
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}
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else if (bus_trans && !bus_write) {
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if (bus_addr <= MEM_SIZE) {
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bus_addr &= ~0x3u;
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rdata =
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(uint32_t)mem[bus_addr] |
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mem[bus_addr + 1] << 8 |
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mem[bus_addr + 2] << 16 |
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mem[bus_addr + 3] << 24;
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}
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}
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#ifdef DUAL_PORT
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top.p_d__hrdata.set<uint32_t>(rdata);
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if (bus_trans_i) {
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bus_addr_i &= ~0x3u;
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top.p_i__hrdata.set<uint32_t>(
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(uint32_t)mem[bus_addr_i] |
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mem[bus_addr_i + 1] << 8 |
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mem[bus_addr_i + 2] << 16 |
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mem[bus_addr_i + 3] << 24
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);
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}
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#else
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top.p_ahblm__hrdata.set<uint32_t>(rdata);
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#endif
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#ifdef DUAL_PORT
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bus_trans = top.p_d__htrans.get<uint8_t>() >> 1;
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bus_write = top.p_d__hwrite.get<bool>();
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bus_size = top.p_d__hsize.get<uint8_t>();
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bus_addr = top.p_d__haddr.get<uint32_t>();
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bus_trans_i = top.p_i__htrans.get<uint8_t>() >> 1;
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bus_addr_i = top.p_i__haddr.get<uint32_t>();
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#else
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bus_trans = top.p_ahblm__htrans.get<uint8_t>() >> 1;
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bus_write = top.p_ahblm__hwrite.get<bool>();
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bus_size = top.p_ahblm__hsize.get<uint8_t>();
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bus_addr = top.p_ahblm__haddr.get<uint32_t>();
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#endif
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// Goto next in debugger sequence
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bool test_done = test_step(top);
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if (dump_waves) {
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// The extra step() is just here to get the bus responses to line up nicely
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// in the VCD (hopefully is a quick update)
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top.step();
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vcd.sample(cycle * 2 + 1);
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waves_fd << vcd.buffer;
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vcd.buffer.clear();
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}
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if (test_done)
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break;
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}
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for (auto r : dump_ranges) {
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printf("Dumping memory from %08x to %08x:\n", r.first, r.second);
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for (int i = 0; i < r.second - r.first; ++i)
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printf("%02x%c", mem[r.first + i], i % 16 == 15 ? '\n' : ' ');
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printf("\n");
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}
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return 0;
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}
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@ -1,57 +0,0 @@
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[*]
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[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
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[*] Sat Jul 10 19:30:00 2021
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[*]
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[dumpfile] "/home/luke/proj/hazard3/test/sim/core_debug/waves.vcd"
|
||||
[dumpfile_mtime] "Sat Jul 10 19:27:20 2021"
|
||||
[dumpfile_size] 23617
|
||||
[savefile] "/home/luke/proj/hazard3/test/sim/core_debug/test.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1920 1043
|
||||
[pos] -1 -1
|
||||
*-2.330973 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] core.
|
||||
[sst_width] 233
|
||||
[signals_width] 310
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 298
|
||||
@28
|
||||
dbg_req_halt
|
||||
dbg_req_resume
|
||||
dbg_halted
|
||||
dbg_running
|
||||
@200
|
||||
-
|
||||
@28
|
||||
dbg_data0_wen
|
||||
@22
|
||||
dbg_data0_wdata[31:0]
|
||||
dbg_data0_rdata[31:0]
|
||||
@200
|
||||
-
|
||||
@22
|
||||
dbg_instr_data[31:0]
|
||||
@28
|
||||
dbg_instr_data_vld
|
||||
dbg_instr_data_rdy
|
||||
dbg_instr_caught_ebreak
|
||||
dbg_instr_caught_exception
|
||||
@200
|
||||
-
|
||||
@22
|
||||
core.frontend.cir[31:0]
|
||||
@28
|
||||
core.frontend.cir_vld[1:0]
|
||||
core.df_cir_use[1:0]
|
||||
@200
|
||||
-
|
||||
@28
|
||||
core.frontend.mem_addr_rdy
|
||||
core.frontend.mem_addr_vld
|
||||
core.frontend.mem_data_vld
|
||||
@29
|
||||
core.frontend.fetch_data_vld
|
||||
@28
|
||||
core.frontend.buf_level_next[1:0]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
Binary file not shown.
|
|
@ -1,2 +0,0 @@
|
|||
tb
|
||||
dut.cpp
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
adapter driver remote_bitbang
|
||||
remote_bitbang_host localhost
|
||||
remote_bitbang_port 9824
|
||||
transport select jtag
|
||||
|
||||
set _CHIPNAME hazard3
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -rtos hwthread
|
||||
|
||||
gdb_report_data_abort enable
|
||||
init
|
||||
halt
|
||||
|
||||
|
||||
riscv test_compliance
|
||||
Loading…
Reference in New Issue