Add instruction access fault testcase

test/sim/common/hazard3_csr.h

@@ -1,9 +1,27 @@
 #ifndef _HAZARD3_CSR_H
 #define _HAZARD3_CSR_H
 
+#ifndef __ASSEMBLER__
+#include "stdint.h"
+#endif
+
 #define hazard3_csr_midcr 0xbc0
 #define hazard3_csr_meie0 0xbe0 // External interrupt enable IRQ0 -> 31
 #define hazard3_csr_meip0 0xfe0 // External interrupt pending IRQ0 -> 31
 #define hazard3_csr_mlei  0xfe4 // Lowest external interrupt (pending & enabled)
 
+#define _read_csr(csrname) ({ \
+  uint32_t __csr_tmp_u32; \
+  asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
+  __csr_tmp_u32; \
+})
+
+#define _write_csr(csrname, data) ({ \
+	asm volatile ("csrw " #csrname ", %0" : : "r" (data)); \
+})
+
+// Argument macro expansion layer
+#define read_csr(csrname) _read_csr(csrname)
+#define write_csr(csrname, data) _write_csr(csrname, data)
+
 #endif

test/sim/sw_testcases/ecall_simple.c

@@ -1,16 +1,8 @@
 #include "tb_cxxrtl_io.h"
-
+#include "hazard3_csr.h"
 
 #include <stdint.h>
 
-#define read_csr(csrname) ({ \
-  uint32_t __csr_tmp_u32; \
-  asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
-  __csr_tmp_u32; \
-})
-
-#define write_csr(csrname, val) __asm__ ("csrw " #csrname ", %0" : : "r" (val))
-
 void __attribute__((interrupt)) handle_exception() {
 	uint32_t call_num;
 	asm volatile ("mv %0, a7" : "=r" (call_num));

test/sim/sw_testcases/illegal_instr.c

@@ -1,15 +1,5 @@
 #include "tb_cxxrtl_io.h"
-
-#define read_csr(csrname) ({ \
-  uint32_t __csr_tmp_u32; \
-  asm volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
-  __csr_tmp_u32; \
-})
-
-#define write_csr(csrname, data) ({ \
-	asm volatile ("csrw " #csrname ", %0" : : "r" (data)); \
-})
-
+#include "hazard3_csr.h"
 
 int main() {
 	tb_puts("1: defined illegal all-zeroes\n");

test/sim/sw_testcases/instr_access_fault.c

@@ -0,0 +1,15 @@
+#include "tb_cxxrtl_io.h"
+#include "hazard3_csr.h"
+
+#include <stdint.h>
+
+int main() {
+	uintptr_t illegal_addr = 0x56789abc;
+	asm volatile ("jr %0" : : "r" (illegal_addr));
+}
+
+void __attribute__((interrupt)) handle_exception() {
+	tb_printf("mcause = %u\n", read_csr(mcause));
+	tb_printf("mepc = %08x\n", read_csr(mepc));
+	tb_exit(0);
+}

test/sim/sw_testcases/instr_access_fault.expected_output

@@ -0,0 +1,2 @@
+mcause = 1
+mepc = 56789abc