Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core

hdl/hazard3_cpu_1port.v

@@ -28,6 +28,7 @@ module hazard3_cpu_1port #(
 	output wire [2:0]        ahblm_hburst,
 	output reg  [3:0]        ahblm_hprot,
 	output wire              ahblm_hmastlock,
+	output reg  [7:0]        ahblm_hmaster,
 	output reg               ahblm_hexcl,
 	input  wire              ahblm_hready,
 	input  wire              ahblm_hresp,
@@ -239,33 +240,37 @@ assign ahblm_hmastlock = 1'b0;
 
 always @ (*) begin
 	if (bus_gnt_s) begin
-		ahblm_htrans = HTRANS_NSEQ;
-		ahblm_hexcl  = 1'b0;
-		ahblm_haddr  = dbg_sbus_addr;
-		ahblm_hsize  = {1'b0, dbg_sbus_size};
-		ahblm_hwrite = dbg_sbus_write;
-		ahblm_hprot  = hprot_sbus;
+		ahblm_htrans  = HTRANS_NSEQ;
+		ahblm_hexcl   = 1'b0;
+		ahblm_haddr   = dbg_sbus_addr;
+		ahblm_hsize   = {1'b0, dbg_sbus_size};
+		ahblm_hwrite  = dbg_sbus_write;
+		ahblm_hprot   = hprot_sbus;
+		ahblm_hmaster = 8'h01;
 	end else if (bus_gnt_d) begin
-		ahblm_htrans = HTRANS_NSEQ;
-		ahblm_hexcl  = core_aph_excl_d;
-		ahblm_haddr  = core_haddr_d;
-		ahblm_hsize  = core_hsize_d;
-		ahblm_hwrite = core_hwrite_d;
-		ahblm_hprot  = hprot_data;
+		ahblm_htrans  = HTRANS_NSEQ;
+		ahblm_hexcl   = core_aph_excl_d;
+		ahblm_haddr   = core_haddr_d;
+		ahblm_hsize   = core_hsize_d;
+		ahblm_hwrite  = core_hwrite_d;
+		ahblm_hprot   = hprot_data;
+		ahblm_hmaster = 8'h00;
 	end else if (bus_gnt_i) begin
-		ahblm_htrans = HTRANS_NSEQ;
-		ahblm_hexcl  = 1'b0;
-		ahblm_haddr  = core_haddr_i;
-		ahblm_hsize  = core_hsize_i;
-		ahblm_hwrite = 1'b0;
-		ahblm_hprot  = hprot_instr;
+		ahblm_htrans  = HTRANS_NSEQ;
+		ahblm_hexcl   = 1'b0;
+		ahblm_haddr   = core_haddr_i;
+		ahblm_hsize   = core_hsize_i;
+		ahblm_hwrite  = 1'b0;
+		ahblm_hprot   = hprot_instr;
+		ahblm_hmaster = 8'h00;
 	end else begin
-		ahblm_htrans = HTRANS_IDLE;
-		ahblm_hexcl  = 1'b0;
-		ahblm_haddr  = {W_ADDR{1'b0}};
-		ahblm_hsize  = 3'h0;
-		ahblm_hwrite = 1'b0;
-		ahblm_hprot  = 4'h0;
+		ahblm_htrans  = HTRANS_IDLE;
+		ahblm_hexcl   = 1'b0;
+		ahblm_haddr   = {W_ADDR{1'b0}};
+		ahblm_hsize   = 3'h0;
+		ahblm_hwrite  = 1'b0;
+		ahblm_hprot   = 4'h0;
+		ahblm_hmaster = 8'h00;
 	end
 end
 

hdl/hazard3_cpu_2port.v

@@ -28,6 +28,7 @@ module hazard3_cpu_2port #(
 	output wire [2:0]        i_hburst,
 	output wire [3:0]        i_hprot,
 	output wire              i_hmastlock,
+	output wire [7:0]        i_hmaster,
 	input  wire              i_hready,
 	input  wire              i_hresp,
 	output wire [W_DATA-1:0] i_hwdata,
@@ -41,6 +42,7 @@ module hazard3_cpu_2port #(
 	output wire [2:0]        d_hburst,
 	output wire [3:0]        d_hprot,
 	output wire              d_hmastlock,
+	output wire [7:0]        d_hmaster,
 	output wire              d_hexcl,
 	input  wire              d_hready,
 	input  wire              d_hresp,
@@ -189,6 +191,7 @@ assign core_rdata_i = i_hrdata;
 assign i_hwrite = 1'b0;
 assign i_hburst = 3'h0;
 assign i_hmastlock = 1'b0;
+assign i_hmaster = 8'h00;
 assign i_hwdata = {W_DATA{1'b0}};
 
 assign i_hprot = {
@@ -270,6 +273,7 @@ assign dbg_sbus_rdata = d_hrdata;
 
 assign d_hburst = 3'h0;
 assign d_hmastlock = 1'b0;
+assign d_hmaster = bus_gnt_s ? 8'h01 : 8'h00;
 
 endmodule