PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.
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Luke Wren
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e0a9fb7312
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@ -92,29 +92,25 @@ parameter U_MODE = 0,
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// PMP is more useful if U mode is supported, but this is not a requirement.
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parameter PMP_REGIONS = 0,
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// PMPADDR_WRITE_MASK: mask of which pmpaddr bits are writable. Can reduce
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// region granularity, or create hardwired regions. If a register is
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// partially writable, it's recommended to set PMP_NO_NA4 for that region, so
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// that PMPCFG.A only permits OFF and NAPOT values.
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parameter PMPADDR_WRITE_MASK = PMP_REGIONS > 0 ? {PMP_REGIONS{~32'h0}} : 1'b0,
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// PMP_GRAIN: This is the "G" parameter in the privileged spec. Minimum PMP
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// region size is 1 << (G + 2) bytes. If G > 0, PMCFG.A can not be set to
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// NA4 (will get set to OFF instead). If G > 1, the G - 1 LSBs of pmpaddr are
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// read-only-0 when PMPCFG.A is OFF, and read-only-1 when PMPCFG.A is NAPOT.
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parameter PMP_GRAIN = 0,
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// PMPADDR_RESET_VAL: provide reset values for pmpaddr registers. The
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// highest-numbered PMP register is listed first in this mask. Note that
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// RISC-V pmpaddr registers are a right-shift by 2 of the physical address.
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parameter PMPADDR_RESET_VAL = PMP_REGIONS > 0 ? {PMP_REGIONS{32'h0}} : 1'b0,
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// PMPADDR_HARDWIRED: If a bit is 1, the corresponding region's pmpaddr and
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// pmpcfg registers are read-only. PMP_GRAIN is ignored on hardwired regions.
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// It's recommended to make hardwired regions the highest-numbered, so they
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// can be overridden by lower-numbered regions.
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parameter PMP_HARDWIRED = PMP_REGIONS > 0 ? {PMP_REGIONS{1'b0}} : 1'b0,
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// PMPCFG_WRITE_MASK: mask of which pmpcfg bits are writable. The reserved
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// bits [6:5] are ignored, and will never be writable.
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parameter PMPCFG_WRITE_MASK = PMP_REGIONS > 0 ? {PMP_REGIONS{8'hff}} : 1'b0,
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// PMPADDR_HARDWIRED_ADDR: Values of pmpaddr registers whose PMP_HARDWIRED
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// bits are set to 1. Non-hardwired regions reset to all-zeroes.
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parameter PMP_HARDWIRED_ADDR = PMP_REGIONS > 0 ? {PMP_REGIONS{32'h0}} : 1'b0,
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// PMPCFG_RESET_VAL: reset values for pmpcfg registers. For regions that are
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// not fully hardwired, it's recommended to initialise A and L to 0.
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parameter PMPCFG_RESET_VAL = PMP_REGIONS > 0 ? {PMP_REGIONS{8'h00}} : 1'b0,
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// PMP_CFG_NO_NA4: disable support for the NA4 region type on a per-region
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// basis, making the minimum region size 8 bytes. Recommended if the pmpaddr
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// register has had its LSBs tied off.
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parameter PMPCFG_NO_NA4 = PMP_REGIONS > 0 ? {PMP_REGIONS{1'b0}} : 1'b0,
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// PMPCFG_RESET_VAL: Values of pmpcfg registers whose PMP_HARDWIRED bits are
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// set to 1. Non-hardwired regions reset to all zeroes.
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parameter PMP_HARDWIRED_CFG = PMP_REGIONS > 0 ? {PMP_REGIONS{8'h00}} : 1'b0,
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// DEBUG_SUPPORT: Support for run/halt and instruction injection from an
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// external Debug Module, support for Debug Mode, and Debug Mode CSRs.
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@ -23,11 +23,10 @@
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.CSR_COUNTER (CSR_COUNTER),
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.U_MODE (U_MODE),
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.PMP_REGIONS (PMP_REGIONS),
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.PMPADDR_WRITE_MASK (PMPADDR_WRITE_MASK),
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.PMPADDR_RESET_VAL (PMPADDR_RESET_VAL),
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.PMPCFG_WRITE_MASK (PMPCFG_WRITE_MASK),
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.PMPCFG_RESET_VAL (PMPCFG_RESET_VAL),
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.PMPCFG_NO_NA4 (PMPCFG_NO_NA4),
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.PMP_GRAIN (PMP_GRAIN),
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.PMP_HARDWIRED (PMP_HARDWIRED),
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.PMP_HARDWIRED_ADDR (PMP_HARDWIRED_ADDR),
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.PMP_HARDWIRED_CFG (PMP_HARDWIRED_CFG),
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.DEBUG_SUPPORT (DEBUG_SUPPORT),
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.NUM_IRQ (NUM_IRQ),
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.MVENDORID_VAL (MVENDORID_VAL),
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@ -57,44 +57,37 @@ always @ (posedge clk or negedge rst_n) begin: cfg_update
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integer i;
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if (!rst_n) begin
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for (i = 0; i < PMP_REGIONS; i = i + 1) begin
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pmpcfg_l[i] <= PMPCFG_RESET_VAL[8 * i + 7];
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pmpcfg_a[i] <= PMPCFG_RESET_VAL[8 * i + 3 +: 2];
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pmpcfg_r[i] <= PMPCFG_RESET_VAL[8 * i + 2];
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pmpcfg_w[i] <= PMPCFG_RESET_VAL[8 * i + 1];
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pmpcfg_x[i] <= PMPCFG_RESET_VAL[8 * i + 0];
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pmpaddr[i] <= PMPADDR_RESET_VAL[32 * i +: 30];
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pmpcfg_l[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_CFG[8 * i + 7] : 1'b0;
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pmpcfg_a[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_CFG[8 * i + 3 +: 2] : 2'h0;
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pmpcfg_r[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_CFG[8 * i + 2] : 1'b0;
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pmpcfg_w[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_CFG[8 * i + 1] : 1'b0;
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pmpcfg_x[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_CFG[8 * i + 0] : 1'b0;
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pmpaddr[i] <= PMP_HARDWIRED[i] ? PMP_HARDWIRED_ADDR[32 * i +: 30] :
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PMP_GRAIN > 1 ? ~(~30'h0 << (PMP_GRAIN - 1)) : 30'h0;
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end
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end else if (cfg_wen) begin
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for (i = 0; i < PMP_REGIONS; i = i + 1) begin
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if (!PMP_HARDWIRED[i]) begin
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if (cfg_addr == PMPCFG0 + i / 4 && !pmpcfg_l[i]) begin
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if (PMPCFG_WRITE_MASK[i * 8 + 7])
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pmpcfg_l[i] <= cfg_wdata[i % 4 * 8 + 7];
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pmpcfg_r[i] <= cfg_wdata[i % 4 * 8 + 2];
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pmpcfg_w[i] <= cfg_wdata[i % 4 * 8 + 1];
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pmpcfg_x[i] <= cfg_wdata[i % 4 * 8 + 0];
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// Unsupported A values are mapped to OFF (it's a WARL field).
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pmpcfg_a[i] <=
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cfg_wdata[i % 4 * 8 + 3 +: 2] == PMP_A_TOR ? PMP_A_OFF :
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cfg_wdata[i % 4 * 8 + 3 +: 2] == PMP_A_NA4 && PMPCFG_NO_NA4[i] ? PMP_A_OFF :
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cfg_wdata[i % 4 * 8 + 3 +: 2] == PMP_A_NA4 && PMP_GRAIN > 0 ? PMP_A_OFF :
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cfg_wdata[i % 4 * 8 + 3 +: 2];
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// Suppress changes to unwritable bits.
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if (!PMPCFG_WRITE_MASK[i * 8 + 4])
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pmpcfg_a[i][1] <= pmpcfg_a[i][1];
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if (!PMPCFG_WRITE_MASK[i * 8 + 3])
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pmpcfg_a[i][0] <= pmpcfg_a[i][0];
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if (PMPCFG_WRITE_MASK[i * 8 + 2])
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pmpcfg_r[i] <= cfg_wdata[i % 4 * 8 + 2];
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if (PMPCFG_WRITE_MASK[i * 8 + 1])
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pmpcfg_w[i] <= cfg_wdata[i % 4 * 8 + 1];
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if (PMPCFG_WRITE_MASK[i * 8 + 0])
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pmpcfg_x[i] <= cfg_wdata[i % 4 * 8 + 0];
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end
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if (cfg_addr == PMPADDR0 + i && !pmpcfg_l[i]) begin
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pmpaddr[i] <=
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cfg_wdata[W_ADDR-3:0] & PMPADDR_WRITE_MASK[i * 32 +: 30] |
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pmpaddr[i] & ~PMPADDR_WRITE_MASK[i * 32 +: 30];
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if (PMP_GRAIN > 1) begin
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pmpaddr[i] <= cfg_wdata[W_ADDR-3:0] | ~(~30'h0 << (PMP_GRAIN - 1));
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end else begin
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pmpaddr[i] <= cfg_wdata[W_ADDR-3:0];
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end
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end
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end
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end
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end
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@ -114,9 +107,17 @@ always @ (*) begin: cfg_read
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pmpcfg_x[i]
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};
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end else if (cfg_addr == PMPADDR0 + i) begin
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// If G > 1, the G-1 LSBs of pmpaddr_i are read-only-zero when
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// region is OFF, and read-only-one when region is NAPOT.
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if (PMP_GRAIN > 1 && !PMP_HARDWIRED[i]) begin
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cfg_rdata[W_ADDR-3:0] = pmpaddr[i] & ~(
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{30{pmpcfg_a[i] != PMP_A_OFF}} & ~(~30'h0 << (PMP_GRAIN - 1))
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);
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end else begin
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cfg_rdata[W_ADDR-3:0] = pmpaddr[i];
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end
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end
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end
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end
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// ----------------------------------------------------------------------------
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