Add RISC-V debug tests

.gitmodules

@@ -13,3 +13,6 @@
 [submodule "example_soc/libfpga"]
 	path = example_soc/libfpga
 	url = https://github.com/Wren6991/libfpga.git
+[submodule "test/sim/riscv-tests/riscv-tests"]
+	path = test/sim/riscv-tests/riscv-tests
+	url = git@github.com:Wren6991/riscv-tests.git

doc/hazard3.pdf

@@ -5,7 +5,7 @@
 /Creator (Asciidoctor PDF 1.5.4, based on Prawn 2.2.2)
 /Producer (Asciidoctor PDF 1.5.4, based on Prawn 2.2.2)
 /ModDate (D:20210618200929+01'00')
-/CreationDate (D:20210717164202+01'00')
+/CreationDate (D:20210719092823+01'00')
 >>
 endobj
 2 0 obj

scripts

@@ -1 +1 @@
-Subproject commit 24f0f32b1d91e7bb873ebefb997c324dbe90a325
+Subproject commit 53af1540e5c29c66a80f5f3681cb4d728e630b36

test/sim/common/memmap.ld

@@ -8,7 +8,7 @@
 
 MEMORY
   {
-    RAM (wx)  : ORIGIN = 0x0, LENGTH = 16M
+    RAM (wx)  : ORIGIN = 0x00000000, LENGTH = 128K
   }
 
 OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",

test/sim/openocd/waves.gtkw

@@ -1,20 +1,20 @@
 [*]
 [*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Sat Jul 17 18:13:53 2021
+[*] Sat Jul 17 18:39:08 2021
 [*]
 [dumpfile] "/home/luke/proj/hazard3/test/sim/openocd/waves.vcd"
-[dumpfile_mtime] "Sat Jul 17 18:07:33 2021"
+[dumpfile_mtime] "Sat Jul 17 18:35:01 2021"
-[dumpfile_size] 6782392
+[dumpfile_size] 6773918
 [savefile] "/home/luke/proj/hazard3/test/sim/openocd/waves.gtkw"
-[timestart] 140588
+[timestart] 0
 [size] 1920 1043
-[pos] -1 -1
+[pos] 174 41
-*-3.000000 140615 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-15.000000 128200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] cpu.
 [treeopen] cpu.core.
 [treeopen] inst_hazard3_jtag_dtm.
 [sst_width] 233
-[signals_width] 222
+[signals_width] 238
 [sst_expanded] 1
 [sst_vpaned_height] 298
 @28
@@ -62,6 +62,13 @@ cpu.dbg_req_halt_on_reset
 cpu.dbg_req_resume
 cpu.dbg_halted
 cpu.dbg_running
+cpu.dbg_instr_caught_ebreak
+cpu.dbg_instr_caught_exception
+@22
+cpu.dbg_instr_data[31:0]
+@28
+cpu.dbg_instr_data_rdy
+cpu.dbg_instr_data_vld
 @200
 -
 -Trap stuff
@@ -75,10 +82,18 @@ cpu.core.inst_hazard3_csr.trap_is_irq
 cpu.core.inst_hazard3_csr.except[3:0]
 @28
 cpu.core.m_stall
-@29
 cpu.core.bus_dph_err_d
 @200
 -
+-CSRs
+@22
+cpu.core.inst_hazard3_csr.addr[11:0]
+@28
+cpu.core.inst_hazard3_csr.wen
+@29
+cpu.core.inst_hazard3_csr.ren_soon
+@200
+-
 -D Bus
 @22
 d_haddr[31:0]

test/sim/riscv-tests/riscv-tests

@@ -0,0 +1 @@
+Subproject commit 545a405a4eb0235c6e877ab57b195786069e0140

test/sim/riscv-tests/run-debug-tests.sh

@@ -0,0 +1,55 @@
+set -e
+
+make -C ../openocd/ clean tb
+cd riscv-tests/debug
+
+# Clean up old logs and test binaries
+rm -rf logs
+for fname in $(find -name "*" -maxdepth 1); do
+	if file ${fname} | grep -q "ELF 32-bit"; then rm ${fname}; fi
+done
+
+# Only applicable tests are included
+./gdbserver.py \
+	--sim_cmd ../../../openocd/tb \
+	--server_cmd riscv-openocd \
+	--gdb riscv32-unknown-elf-gdb \
+	--gcc riscv32-unknown-elf-gcc \
+	targets/luke/hazard3.py \
+CheckMisa \
+DebugBreakpoint \
+DebugChangeString \
+DebugCompareSections \
+DebugExit \
+DebugFunctionCall \
+DebugSymbols \
+DebugTurbostep \
+DownloadTest \
+InfoTest \
+InterruptTest \
+InstantChangePc \
+InstantHaltTest \
+MemTest16 \
+MemTest32 \
+MemTest64 \
+MemTest8 \
+MemTestBlock0 \
+MemTestBlock1 \
+MemTestBlock2 \
+MemTestReadInvalid \
+PrivRw \
+ProgramSwWatchpoint \
+Registers \
+Semihosting \
+SimpleF18Test \
+SimpleNoExistTest \
+SimpleS0Test \
+SimpleS1Test \
+SimpleT0Test \
+SimpleT1Test \
+SimpleV13Test \
+StepTest \
+TooManyHwbp \
+UserInterrupt \
+WriteCsrs \
+WriteGprs