rvcpp: correctly model memory access faults. relevant sw_testcases now pass.
Also, grab the special-case core RAM change from the Sv32 fork, for better performance
This commit is contained in:
Luke Wren
parent
fd584ea24b
commit
b473575b7e
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@ -1,15 +1,20 @@
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#ifndef _MEM_H
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#define _MEM_H
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#ifndef _RV_MEM_H
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#define _RV_MEM_H
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#include "rv_types.h"
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#include <optional>
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#include <tuple>
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#include <cassert>
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#include <vector>
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#include <cstdio>
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struct MemBase32 {
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virtual uint8_t r8(ux_t addr) {return 0;}
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virtual void w8(ux_t addr, uint8_t data) {}
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virtual uint16_t r16(ux_t addr) {return 0;}
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virtual void w16(ux_t addr, uint16_t data) {}
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virtual uint32_t r32(ux_t addr) {return 0;}
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virtual void w32(ux_t addr, uint32_t data) {}
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virtual std::optional<uint8_t> r8(__attribute__((unused)) ux_t addr) {return std::nullopt;}
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virtual bool w8(__attribute__((unused)) ux_t addr, __attribute__((unused)) uint8_t data) {return false;}
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virtual std::optional<uint16_t> r16(__attribute__((unused)) ux_t addr) {return std::nullopt;}
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virtual bool w16(__attribute__((unused)) ux_t addr, __attribute__((unused)) uint16_t data) {return false;}
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virtual std::optional<uint32_t> r32(__attribute__((unused)) ux_t addr) {return std::nullopt;}
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virtual bool w32(__attribute__((unused)) ux_t addr, __attribute__((unused)) uint32_t data) {return false;}
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};
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struct FlatMem32: MemBase32 {
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@ -28,40 +33,43 @@ struct FlatMem32: MemBase32 {
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delete mem;
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}
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virtual uint8_t r8(ux_t addr) {
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virtual std::optional<uint8_t> r8(ux_t addr) {
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assert(addr < size);
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return mem[addr >> 2] >> 8 * (addr & 0x3) & 0xffu;
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}
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virtual void w8(ux_t addr, uint8_t data) {
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virtual bool w8(ux_t addr, uint8_t data) {
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assert(addr < size);
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mem[addr >> 2] &= ~(0xffu << 8 * (addr & 0x3));
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mem[addr >> 2] |= (uint32_t)data << 8 * (addr & 0x3);
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return true;
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}
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virtual uint16_t r16(ux_t addr) {
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virtual std::optional<uint16_t> r16(ux_t addr) {
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assert(addr < size && addr + 1 < size); // careful of ~0u
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assert(addr % 2 == 0);
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return mem[addr >> 2] >> 8 * (addr & 0x2) & 0xffffu;
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}
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virtual void w16(ux_t addr, uint16_t data) {
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virtual bool w16(ux_t addr, uint16_t data) {
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assert(addr < size && addr + 1 < size);
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assert(addr % 2 == 0);
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mem[addr >> 2] &= ~(0xffffu << 8 * (addr & 0x2));
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mem[addr >> 2] |= (uint32_t)data << 8 * (addr & 0x2);
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return true;
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}
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virtual uint32_t r32(ux_t addr) {
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virtual std::optional<uint32_t> r32(ux_t addr) {
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assert(addr < size && addr + 3 < size);
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assert(addr % 4 == 0);
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return mem[addr >> 2];
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}
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virtual void w32(ux_t addr, uint32_t data) {
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virtual bool w32(ux_t addr, uint32_t data) {
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assert(addr < size && addr + 3 < size);
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assert(addr % 4 == 0);
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mem[addr >> 2] = data;
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return true;
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}
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};
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@ -71,17 +79,19 @@ struct TBExitException {
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};
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struct TBMemIO: MemBase32 {
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virtual void w32(ux_t addr, uint32_t data) {
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virtual bool w32(ux_t addr, uint32_t data) {
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switch (addr) {
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case 0x0:
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printf("%c", (char)data);
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break;
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return true;
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case 0x4:
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printf("%08x\n", data);
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break;
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return true;
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case 0x8:
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throw TBExitException(data);
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break;
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return true;
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default:
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return false;
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}
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}
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};
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@ -98,38 +108,55 @@ struct MemMap32: MemBase32 {
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if (addr >= base && addr < base + size)
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return std::make_tuple(addr - base, mem);
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}
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throw;
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return std::make_tuple(addr, nullptr);
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}
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// perhaps some templatey-ness required
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virtual uint8_t r8(ux_t addr) {
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virtual std::optional<uint8_t> r8(ux_t addr) {
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auto [offset, mem] = map_addr(addr);
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return mem->r8(offset);
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if (mem)
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return mem->r8(offset);
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else
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return std::nullopt;
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}
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virtual void w8(ux_t addr, uint8_t data) {
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virtual bool w8(ux_t addr, uint8_t data) {
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auto [offset, mem] = map_addr(addr);
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mem->w8(offset, data);
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if (mem)
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return mem->w8(offset, data);
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else
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return false;
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}
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virtual uint16_t r16(ux_t addr) {
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virtual std::optional<uint16_t> r16(ux_t addr) {
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auto [offset, mem] = map_addr(addr);
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return mem->r16(offset);
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if (mem)
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return mem->r16(offset);
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else
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return std::nullopt;
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}
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virtual void w16(ux_t addr, uint16_t data) {
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virtual bool w16(ux_t addr, uint16_t data) {
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auto [offset, mem] = map_addr(addr);
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mem->w16(offset, data);
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if (mem)
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return mem->w16(offset, data);
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else
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return false;
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}
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virtual uint32_t r32(ux_t addr) {
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virtual std::optional<uint32_t> r32(ux_t addr) {
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auto [offset, mem] = map_addr(addr);
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return mem->r32(offset);
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if (mem)
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return mem->r32(offset);
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else
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return std::nullopt;
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}
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virtual void w32(ux_t addr, uint32_t data) {
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virtual bool w32(ux_t addr, uint32_t data) {
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auto [offset, mem] = map_addr(addr);
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mem->w32(offset, data);
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if (mem)
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return mem->w32(offset, data);
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else
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return false;
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}
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};
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@ -26,6 +26,11 @@
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// - Zcmp
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// - M-mode traps
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#define RAM_SIZE_DEFAULT (16u * (1u << 20))
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#define RAM_BASE 0u
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#define IO_BASE 0x80000000u
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#define TBIO_BASE (IO_BASE + 0x0000)
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// Use unsigned arithmetic everywhere, with explicit sign extension as required.
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static inline ux_t sext(ux_t bits, int sign_bit) {
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if (sign_bit >= XLEN - 1)
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@ -346,11 +351,34 @@ struct RVCore {
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ux_t pc;
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RVCSR csr;
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bool load_reserved;
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MemBase32 &mem;
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RVCore(ux_t reset_vector=0x40) {
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// A single flat RAM is handled as a special case, in addition to whatever
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// is in `mem`, because this avoids virtual calls for the majority of
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// memory accesses. This RAM takes precedence over whatever is mapped at
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// the same address in `mem`. (Note the size of this RAM may be zero, and
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// RAM can also be added to the `mem` object.)
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ux_t *ram;
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ux_t ram_base;
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ux_t ram_top;
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RVCore(MemBase32 &_mem, ux_t reset_vector, ux_t ram_base_, ux_t ram_size_) : mem(_mem) {
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std::fill(std::begin(regs), std::end(regs), 0);
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pc = reset_vector;
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load_reserved = false;
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ram_base = ram_base_;
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ram_top = ram_base_ + ram_size_;
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ram = new ux_t[ram_size_ / sizeof(ux_t)];
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assert(ram);
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assert(!(ram_base_ & 0x3));
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assert(!(ram_size_ & 0x3));
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assert(ram_base_ + ram_size_ >= ram_base_);
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for (ux_t i = 0; i < ram_size_ / sizeof(ux_t); ++i)
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ram[i] = 0;
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}
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~RVCore() {
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delete ram;
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}
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enum {
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@ -369,18 +397,78 @@ struct RVCore {
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OPC_CUSTOM0 = 0b00'010
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};
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void step(MemBase32 &mem, bool trace=false) {
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uint32_t instr = mem.r16(pc) | (mem.r16(pc + 2) << 16);
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// Functions to read/write memory from this hart's point of view
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std::optional<uint8_t> r8(ux_t addr) {
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if (addr >= ram_base && addr < ram_top) {
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return ram[(addr - ram_base) >> 2] >> 8 * (addr & 0x3) & 0xffu;
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} else {
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return mem.r8(addr);
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}
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}
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bool w8(ux_t addr, uint8_t data) {
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if (addr >= ram_base && addr < ram_top) {
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ram[(addr - ram_base) >> 2] &= ~(0xffu << 8 * (addr & 0x3));
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ram[(addr - ram_base) >> 2] |= (uint32_t)data << 8 * (addr & 0x3);
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return true;
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} else {
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return mem.w8(addr, data);
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}
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}
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std::optional<uint16_t> r16(ux_t addr) {
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if (addr >= ram_base && addr < ram_top) {
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return ram[(addr - ram_base) >> 2] >> 8 * (addr & 0x2) & 0xffffu;
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} else {
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return mem.r16(addr);
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}
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}
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bool w16(ux_t addr, uint16_t data) {
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if (addr >= ram_base && addr < ram_top) {
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ram[(addr - ram_base) >> 2] &= ~(0xffffu << 8 * (addr & 0x2));
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ram[(addr - ram_base) >> 2] |= (uint32_t)data << 8 * (addr & 0x2);
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return true;
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} else {
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return mem.w16(addr, data);
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}
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}
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std::optional<uint32_t> r32(ux_t addr) {
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if (addr >= ram_base && addr < ram_top) {
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return ram[(addr - ram_base) >> 2];
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} else {
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return mem.r32(addr);
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}
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}
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bool w32(ux_t addr, uint32_t data) {
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if (addr >= ram_base && addr < ram_top) {
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ram[(addr - ram_base) >> 2] = data;
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return true;
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} else {
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return mem.w32(addr, data);
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}
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}
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// Fetch and execute one instruction from memory.
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void step(bool trace=false) {
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std::optional<ux_t> rd_wdata;
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std::optional<ux_t> pc_wdata;
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uint regnum_rd = 0;
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std::optional<uint> exception_cause;
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uint regnum_rd = 0;
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std::optional<uint16_t> fetch0 = r16(pc);
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std::optional<uint16_t> fetch1 = r16(pc + 2);
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uint32_t instr = *fetch0 | ((uint32_t)*fetch1 << 16);
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uint opc = instr >> 2 & 0x1f;
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uint funct3 = instr >> 12 & 0x7;
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uint funct7 = instr >> 25 & 0x7f;
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if ((instr & 0x3) == 0x3) {
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if (!fetch0 || ((*fetch0 & 0x3) == 0x3 && !fetch1)) {
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exception_cause = XCAUSE_INSTR_FAULT;
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} else if ((instr & 0x3) == 0x3) {
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// 32-bit instruction
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uint regnum_rs1 = instr >> 15 & 0x1f;
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uint regnum_rs2 = instr >> 20 & 0x1f;
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@ -614,47 +702,67 @@ struct RVCore {
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case OPC_LOAD: {
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ux_t load_addr = rs1 + imm_i(instr);
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if (funct3 == 0b000) {
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rd_wdata = sext(mem.r8(load_addr), 7);
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} else if (funct3 == 0b001) {
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if (load_addr & 0x1)
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exception_cause = XCAUSE_LOAD_ALIGN;
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else
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rd_wdata = sext(mem.r16(load_addr), 15);
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} else if (funct3 == 0b010) {
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if (load_addr & 0x3)
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exception_cause = XCAUSE_LOAD_ALIGN;
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else
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rd_wdata = mem.r32(load_addr);
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} else if (funct3 == 0b100) {
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rd_wdata = mem.r8(load_addr);
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} else if (funct3 == 0b101) {
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if (load_addr & 0x1)
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exception_cause = XCAUSE_LOAD_ALIGN;
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else
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rd_wdata = mem.r16(load_addr);
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} else {
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ux_t align_mask = ~(-1u << (funct3 & 0x3));
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bool misalign = load_addr & align_mask;
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if (funct3 == 0b011 || funct3 > 0b101) {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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} else if (misalign) {
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exception_cause = XCAUSE_LOAD_ALIGN;
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} else if (funct3 == 0b000) {
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rd_wdata = r8(load_addr);
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if (rd_wdata) {
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rd_wdata = sext(*rd_wdata, 7);
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} else {
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exception_cause = XCAUSE_LOAD_FAULT;
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}
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} else if (funct3 == 0b001) {
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rd_wdata = r16(load_addr);
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if (rd_wdata) {
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rd_wdata = sext(*rd_wdata, 15);
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} else {
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exception_cause = XCAUSE_LOAD_FAULT;
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}
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} else if (funct3 == 0b010) {
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rd_wdata = r32(load_addr);
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if (!rd_wdata) {
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exception_cause = XCAUSE_LOAD_FAULT;
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}
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} else if (funct3 == 0b100) {
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rd_wdata = r8(load_addr);
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if (!rd_wdata) {
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exception_cause = XCAUSE_LOAD_FAULT;
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}
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} else if (funct3 == 0b101) {
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rd_wdata = r16(load_addr);
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if (!rd_wdata) {
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exception_cause = XCAUSE_LOAD_FAULT;
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}
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}
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break;
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}
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case OPC_STORE: {
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ux_t store_addr = rs1 + imm_s(instr);
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if (funct3 == 0b000) {
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mem.w8(store_addr, rs2 & 0xffu);
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} else if (funct3 == 0b001) {
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if (store_addr & 0x1)
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exception_cause = XCAUSE_STORE_ALIGN;
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else
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mem.w16(store_addr, rs2 & 0xffffu);
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} else if (funct3 == 0b010) {
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if (store_addr & 0x3)
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exception_cause = XCAUSE_STORE_ALIGN;
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else
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mem.w32(store_addr, rs2);
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} else {
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ux_t align_mask = ~(-1u << (funct3 & 0x3));
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bool misalign = store_addr & align_mask;
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if (funct3 > 0b010) {
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exception_cause = XCAUSE_INSTR_ILLEGAL;
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} else if (misalign) {
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exception_cause = XCAUSE_STORE_ALIGN;
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} else {
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if (funct3 == 0b000) {
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if (!w8(store_addr, rs2 & 0xffu)) {
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exception_cause = XCAUSE_STORE_FAULT;
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}
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} else if (funct3 == 0b001) {
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if (!w16(store_addr, rs2 & 0xffffu)) {
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exception_cause = XCAUSE_STORE_FAULT;
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}
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} else if (funct3 == 0b010) {
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if (!w32(store_addr, rs2)) {
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exception_cause = XCAUSE_STORE_FAULT;
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}
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}
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}
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break;
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}
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@ -664,8 +772,12 @@ struct RVCore {
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if (rs1 & 0x3) {
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exception_cause = XCAUSE_LOAD_ALIGN;
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} else {
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rd_wdata = mem.r32(rs1);
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load_reserved = true;
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rd_wdata = r32(rs1);
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if (rd_wdata) {
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load_reserved = true;
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} else {
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exception_cause = XCAUSE_LOAD_FAULT;
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}
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}
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} else if (RVOPC_MATCH(instr, SC_W)) {
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if (rs1 & 0x3) {
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@ -673,20 +785,15 @@ struct RVCore {
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} else {
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if (load_reserved) {
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load_reserved = false;
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mem.w32(rs1, rs2);
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rd_wdata = 0;
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if (w32(rs1, rs2)) {
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rd_wdata = 0;
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} else {
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exception_cause = XCAUSE_STORE_FAULT;
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}
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} else {
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rd_wdata = 1;
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}
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}
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} else if (RVOPC_MATCH(instr, AMOSWAP_W)) {
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if (rs1 & 0x3) {
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exception_cause = XCAUSE_STORE_ALIGN;
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} else {
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rd_wdata = mem.r32(rs1);
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mem.w32(rs1, rs2);
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}
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} else if (
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RVOPC_MATCH(instr, AMOSWAP_W) ||
|
||||
RVOPC_MATCH(instr, AMOADD_W) ||
|
||||
|
|
@ -700,18 +807,27 @@ struct RVCore {
|
|||
if (rs1 & 0x3) {
|
||||
exception_cause = XCAUSE_STORE_ALIGN;
|
||||
} else {
|
||||
rd_wdata = mem.r32(rs1);
|
||||
switch (instr & RVOPC_AMOSWAP_W_MASK) {
|
||||
case RVOPC_AMOSWAP_W_BITS: mem.w32(rs1, *rd_wdata); break;
|
||||
case RVOPC_AMOADD_W_BITS: mem.w32(rs1, *rd_wdata + rs2); break;
|
||||
case RVOPC_AMOXOR_W_BITS: mem.w32(rs1, *rd_wdata ^ rs2); break;
|
||||
case RVOPC_AMOAND_W_BITS: mem.w32(rs1, *rd_wdata & rs2); break;
|
||||
case RVOPC_AMOOR_W_BITS: mem.w32(rs1, *rd_wdata | rs2); break;
|
||||
case RVOPC_AMOMIN_W_BITS: mem.w32(rs1, (sx_t)*rd_wdata < (sx_t)rs2 ? *rd_wdata : rs2); break;
|
||||
case RVOPC_AMOMAX_W_BITS: mem.w32(rs1, (sx_t)*rd_wdata > (sx_t)rs2 ? *rd_wdata : rs2); break;
|
||||
case RVOPC_AMOMINU_W_BITS: mem.w32(rs1, *rd_wdata < rs2 ? *rd_wdata : rs2); break;
|
||||
case RVOPC_AMOMAXU_W_BITS: mem.w32(rs1, *rd_wdata > rs2 ? *rd_wdata : rs2); break;
|
||||
default: assert(false); break;
|
||||
rd_wdata = r32(rs1);
|
||||
if (!rd_wdata) {
|
||||
exception_cause = XCAUSE_STORE_FAULT; // Yes, AMO/Store
|
||||
} else {
|
||||
bool write_success = false;
|
||||
switch (instr & RVOPC_AMOSWAP_W_MASK) {
|
||||
case RVOPC_AMOSWAP_W_BITS: write_success = w32(rs1, rs2); break;
|
||||
case RVOPC_AMOADD_W_BITS: write_success = w32(rs1, *rd_wdata + rs2); break;
|
||||
case RVOPC_AMOXOR_W_BITS: write_success = w32(rs1, *rd_wdata ^ rs2); break;
|
||||
case RVOPC_AMOAND_W_BITS: write_success = w32(rs1, *rd_wdata & rs2); break;
|
||||
case RVOPC_AMOOR_W_BITS: write_success = w32(rs1, *rd_wdata | rs2); break;
|
||||
case RVOPC_AMOMIN_W_BITS: write_success = w32(rs1, (sx_t)*rd_wdata < (sx_t)rs2 ? *rd_wdata : rs2); break;
|
||||
case RVOPC_AMOMAX_W_BITS: write_success = w32(rs1, (sx_t)*rd_wdata > (sx_t)rs2 ? *rd_wdata : rs2); break;
|
||||
case RVOPC_AMOMINU_W_BITS: write_success = w32(rs1, *rd_wdata < rs2 ? *rd_wdata : rs2); break;
|
||||
case RVOPC_AMOMAXU_W_BITS: write_success = w32(rs1, *rd_wdata > rs2 ? *rd_wdata : rs2); break;
|
||||
default: assert(false); break;
|
||||
}
|
||||
if (!write_success) {
|
||||
exception_cause = XCAUSE_STORE_FAULT;
|
||||
rd_wdata = {};
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
|
|
@ -812,13 +928,18 @@ struct RVCore {
|
|||
+ (GETBIT(instr, 6) << 2)
|
||||
+ (GETBITS(instr, 12, 10) << 3)
|
||||
+ (GETBIT(instr, 5) << 6);
|
||||
rd_wdata = mem.r32(addr);
|
||||
rd_wdata = r32(addr);
|
||||
if (!rd_wdata) {
|
||||
exception_cause = XCAUSE_LOAD_FAULT;
|
||||
}
|
||||
} else if (RVOPC_MATCH(instr, C_SW)) {
|
||||
uint32_t addr = regs[c_rs1_s(instr)]
|
||||
+ (GETBIT(instr, 6) << 2)
|
||||
+ (GETBITS(instr, 12, 10) << 3)
|
||||
+ (GETBIT(instr, 5) << 6);
|
||||
mem.w32(addr, regs[c_rs2_s(instr)]);
|
||||
if (!w32(addr, regs[c_rs2_s(instr)])) {
|
||||
exception_cause = XCAUSE_STORE_FAULT;
|
||||
}
|
||||
} else {
|
||||
exception_cause = XCAUSE_INSTR_ILLEGAL;
|
||||
}
|
||||
|
|
@ -916,39 +1037,58 @@ struct RVCore {
|
|||
+ (GETBIT(instr, 12) << 5)
|
||||
+ (GETBITS(instr, 6, 4) << 2)
|
||||
+ (GETBITS(instr, 3, 2) << 6);
|
||||
rd_wdata = mem.r32(addr);
|
||||
rd_wdata = r32(addr);
|
||||
if (!rd_wdata) {
|
||||
exception_cause = XCAUSE_LOAD_FAULT;
|
||||
}
|
||||
} else if (RVOPC_MATCH(instr, C_SWSP)) {
|
||||
ux_t addr = regs[2]
|
||||
+ (GETBITS(instr, 12, 9) << 2)
|
||||
+ (GETBITS(instr, 8, 7) << 6);
|
||||
mem.w32(addr, regs[c_rs2_l(instr)]);
|
||||
if (!w32(addr, regs[c_rs2_l(instr)])) {
|
||||
exception_cause = XCAUSE_STORE_FAULT;
|
||||
}
|
||||
// Zcmp:
|
||||
} else if (RVOPC_MATCH(instr, CM_PUSH)) {
|
||||
ux_t addr = regs[2];
|
||||
for (uint i = 31; i > 0; --i) {
|
||||
bool fail = false;
|
||||
for (uint i = 31; i > 0 && !fail; --i) {
|
||||
if (zcmp_reg_mask(instr) & (1u << i)) {
|
||||
addr -= 4;
|
||||
mem.w32(addr, regs[i]);
|
||||
fail = fail || !w32(addr, regs[i]);
|
||||
}
|
||||
}
|
||||
regnum_rd = 2;
|
||||
rd_wdata = regs[2] - zcmp_stack_adj(instr);
|
||||
if (fail) {
|
||||
exception_cause = XCAUSE_STORE_FAULT;
|
||||
} else {
|
||||
regnum_rd = 2;
|
||||
rd_wdata = regs[2] - zcmp_stack_adj(instr);
|
||||
}
|
||||
} else if (RVOPC_MATCH(instr, CM_POP) || RVOPC_MATCH(instr, CM_POPRET) || RVOPC_MATCH(instr, CM_POPRETZ)) {
|
||||
bool clear_a0 = RVOPC_MATCH(instr, CM_POPRETZ);
|
||||
bool ret = clear_a0 || RVOPC_MATCH(instr, CM_POPRET);
|
||||
ux_t addr = regs[2] + zcmp_stack_adj(instr);
|
||||
for (uint i = 31; i > 0; --i) {
|
||||
bool fail = false;
|
||||
for (uint i = 31; i > 0 && !fail; --i) {
|
||||
if (zcmp_reg_mask(instr) & (1u << i)) {
|
||||
addr -= 4;
|
||||
regs[i] = mem.r32(addr);
|
||||
std::optional<ux_t> load_result = r32(addr);
|
||||
fail = fail || !load_result;
|
||||
if (load_result) {
|
||||
regs[i] = *load_result;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (clear_a0)
|
||||
regs[10] = 0;
|
||||
if (ret)
|
||||
pc_wdata = regs[1];
|
||||
regnum_rd = 2;
|
||||
rd_wdata = regs[2] + zcmp_stack_adj(instr);
|
||||
if (fail) {
|
||||
exception_cause = XCAUSE_LOAD_FAULT;
|
||||
} else {
|
||||
if (clear_a0)
|
||||
regs[10] = 0;
|
||||
if (ret)
|
||||
pc_wdata = regs[1];
|
||||
regnum_rd = 2;
|
||||
rd_wdata = regs[2] + zcmp_stack_adj(instr);
|
||||
}
|
||||
} else if (RVOPC_MATCH(instr, CM_MVSA01)) {
|
||||
regs[zcmp_s_mapping(GETBITS(instr, 9, 7))] = regs[10];
|
||||
regs[zcmp_s_mapping(GETBITS(instr, 4, 2))] = regs[11];
|
||||
|
|
@ -1008,7 +1148,7 @@ const char *help_str =
|
|||
" --cycles n : Maximum number of cycles to run before exiting.\n"
|
||||
" --cpuret : Testbench's return code is the return code written to\n"
|
||||
" IO_EXIT by the CPU, or -1 if timed out.\n"
|
||||
" --memsize n : Memory size in units of 1024 bytes, default is 16 MB\n"
|
||||
" --memsize n : Memory size in units of 1024 bytes, default is 16 MiB\n"
|
||||
" --trace : Print out execution tracing info\n"
|
||||
;
|
||||
|
||||
|
|
@ -1023,7 +1163,7 @@ int main(int argc, char **argv) {
|
|||
|
||||
std::vector<std::tuple<uint32_t, uint32_t>> dump_ranges;
|
||||
int64_t max_cycles = 100000;
|
||||
uint32_t ramsize = 16 * (1 << 20);
|
||||
uint32_t ram_size = RAM_SIZE_DEFAULT;
|
||||
bool load_bin = false;
|
||||
std::string bin_path;
|
||||
bool trace_execution = false;
|
||||
|
|
@ -1062,7 +1202,7 @@ int main(int argc, char **argv) {
|
|||
else if (s == "--memsize") {
|
||||
if (argc - i < 2)
|
||||
exit_help("Option --memsize requires an argument\n");
|
||||
ramsize = 1024 * std::stol(argv[i + 1], 0, 0);
|
||||
ram_size = 1024 * std::stol(argv[i + 1], 0, 0);
|
||||
i += 1;
|
||||
}
|
||||
else if (s == "--trace") {
|
||||
|
|
@ -1077,30 +1217,28 @@ int main(int argc, char **argv) {
|
|||
}
|
||||
}
|
||||
|
||||
FlatMem32 ram(ramsize);
|
||||
TBMemIO io;
|
||||
MemMap32 mem;
|
||||
mem.add(0, ramsize, &ram);
|
||||
mem.add(0x80000000u, 12, &io);
|
||||
|
||||
RVCore core(mem, RAM_BASE + 0x40, RAM_BASE, ram_size);
|
||||
|
||||
if (load_bin) {
|
||||
std::ifstream fd(bin_path, std::ios::binary | std::ios::ate);
|
||||
std::streamsize bin_size = fd.tellg();
|
||||
if (bin_size > ramsize) {
|
||||
std::cerr << "Binary file (" << bin_size << " bytes) is larger than memory (" << ramsize << " bytes)\n";
|
||||
if (bin_size > ram_size) {
|
||||
std::cerr << "Binary file (" << bin_size << " bytes) is larger than memory (" << ram_size << " bytes)\n";
|
||||
return -1;
|
||||
}
|
||||
fd.seekg(0, std::ios::beg);
|
||||
fd.read((char*)ram.mem, bin_size);
|
||||
fd.read((char*)core.ram, bin_size);
|
||||
}
|
||||
|
||||
RVCore core;
|
||||
|
||||
int64_t cyc;
|
||||
int rc = 0;
|
||||
try {
|
||||
for (cyc = 0; cyc < max_cycles; ++cyc)
|
||||
core.step(mem, trace_execution);
|
||||
core.step(trace_execution);
|
||||
if (propagate_return_code)
|
||||
rc = -1;
|
||||
}
|
||||
|
|
@ -1114,7 +1252,7 @@ int main(int argc, char **argv) {
|
|||
for (auto [start, end] : dump_ranges) {
|
||||
printf("Dumping memory from %08x to %08x:\n", start, end);
|
||||
for (uint32_t i = 0; i < end - start; ++i)
|
||||
printf("%02x%c", mem.r8(start + i), i % 16 == 15 ? '\n' : ' ');
|
||||
printf("%02x%c", *core.r8(start + i), i % 16 == 15 ? '\n' : ' ');
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue