Cleanup to avoid negative array index (legal but causes whinging)
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@ -441,7 +441,7 @@ reg [NUM_IRQS-1:0] eirq_active_above_ppreempt;
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always @ (*) begin: eirq_compare
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always @ (*) begin: eirq_compare
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integer i;
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integer i;
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for (i = 0; i < NUM_IRQS; i = i + 1) begin
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for (i = 0; i < NUM_IRQS; i = i + 1) begin
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eirq_active_above_preempt[i] = meipa[i] && meiea[i] && meipra[i * 4 +: 4] >= meicontext_preempt;
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eirq_active_above_preempt[i] = meipa[i] && meiea[i] && {1'b0, meipra[i * 4 +: 4]} >= meicontext_preempt;
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eirq_active_above_ppreempt[i] = meipa[i] && meiea[i] && meipra[i * 4 +: 4] >= meicontext_ppreempt;
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eirq_active_above_ppreempt[i] = meipa[i] && meiea[i] && meipra[i * 4 +: 4] >= meicontext_ppreempt;
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end
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end
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end
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end
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@ -105,10 +105,10 @@ reg [1:0] mem_data_predbranch;
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// to decode the instruction, but until then can be flushed harmlessly.
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// to decode the instruction, but until then can be flushed harmlessly.
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reg [W_DATA-1:0] fifo_mem [0:FIFO_DEPTH];
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reg [W_DATA-1:0] fifo_mem [0:FIFO_DEPTH];
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reg [FIFO_DEPTH:0] fifo_err;
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reg fifo_err [0:FIFO_DEPTH];
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reg [1:0] fifo_predbranch [0:FIFO_DEPTH];
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reg [1:0] fifo_predbranch [0:FIFO_DEPTH];
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reg [1:0] fifo_valid_hw [0:FIFO_DEPTH];
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reg [1:0] fifo_valid_hw [0:FIFO_DEPTH];
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reg [FIFO_DEPTH:-1] fifo_valid;
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reg fifo_valid [0:FIFO_DEPTH];
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wire [W_DATA-1:0] fifo_rdata = fifo_mem[0];
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wire [W_DATA-1:0] fifo_rdata = fifo_mem[0];
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wire fifo_full = fifo_valid[FIFO_DEPTH - 1];
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wire fifo_full = fifo_valid[FIFO_DEPTH - 1];
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@ -126,7 +126,6 @@ always @ (*) begin: boundary_conditions
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fifo_err[FIFO_DEPTH] = 1'b0;
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fifo_err[FIFO_DEPTH] = 1'b0;
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fifo_valid_hw[FIFO_DEPTH] = 2'b00;
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fifo_valid_hw[FIFO_DEPTH] = 2'b00;
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fifo_valid[FIFO_DEPTH] = 1'b0;
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fifo_valid[FIFO_DEPTH] = 1'b0;
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fifo_valid[-1] = 1'b1;
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for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
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for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
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fifo_valid[i] = |EXTENSION_C ? |fifo_valid_hw[i] : fifo_valid_hw[i][0];
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fifo_valid[i] = |EXTENSION_C ? |fifo_valid_hw[i] : fifo_valid_hw[i][0];
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end
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end
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@ -151,9 +150,9 @@ always @ (posedge clk or negedge rst_n) begin: fifo_update
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fifo_valid_hw[i] <=
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fifo_valid_hw[i] <=
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jump_now ? 2'h0 :
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jump_now ? 2'h0 :
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fifo_valid[i + 1] && fifo_pop ? fifo_valid_hw[i + 1] :
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fifo_valid[i + 1] && fifo_pop ? fifo_valid_hw[i + 1] :
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fifo_valid[i] && fifo_pop && !fifo_push ? 2'h0 :
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fifo_valid[i] && fifo_pop ? mem_data_hwvld & {2{fifo_push}} :
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fifo_valid[i] && fifo_pop && fifo_push ? mem_data_hwvld :
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fifo_valid[i] ? fifo_valid_hw[i] :
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!fifo_valid[i] && fifo_valid[i - 1] && fifo_push && !fifo_pop ? mem_data_hwvld : fifo_valid_hw[i];
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fifo_push && !fifo_pop && (i == 0 || fifo_valid[i - |i]) ? mem_data_hwvld : 2'h0;
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end
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end
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// Allow DM to inject instructions directly into the lowest-numbered
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// Allow DM to inject instructions directly into the lowest-numbered
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// queue entry. This mux should not extend critical path since it is
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// queue entry. This mux should not extend critical path since it is
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