From ba9a7b4a03098718e5fe840d276810b75d402cdc Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sun, 21 Nov 2021 14:58:07 +0000 Subject: [PATCH] Fix broken link in readme --- Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Readme.md b/Readme.md index c33bfda..9fc0bac 100644 --- a/Readme.md +++ b/Readme.md @@ -59,7 +59,7 @@ These instructions are for Ubuntu 20.04. You will need: - A recent Yosys build to process the Verilog. At least version `c2afcbe7`, which includes a workaround for a gtkwave string parsing issue. Latest master should be fine. - A `riscv32-unknown-elf-` toolchain to build software for the core - A native `clang` to build the simulator -- (For debug) a recent build of [https://github.com/riscv/riscv-openocd](riscv-openocd) with the `remote-bitbang` protocol enabled. A recent version of upstream openocd should also work. +- (For debug) a recent build of [riscv-openocd](https://github.com/riscv/riscv-openocd) with the `remote-bitbang` protocol enabled. A recent version of upstream openocd should also work. ## Yosys