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Fix up DTMs to use byte addressing

This commit is contained in:
Luke Wren 2021-12-02 02:05:23 +00:00
parent 1ebccb7cce
commit be6b2f3f76
5 changed files with 30 additions and 25 deletions
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2
example_soc/soc/example_soc.v
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@ -163,7 +163,7 @@ hazard3_dm #(
.dmi_psel (dmi_psel), .dmi_psel (dmi_psel),
.dmi_penable (dmi_penable), .dmi_penable (dmi_penable),
.dmi_pwrite (dmi_pwrite), .dmi_pwrite (dmi_pwrite),
.dmi_paddr ({dmi_paddr, 2'b00}), .dmi_paddr (dmi_paddr),
.dmi_pwdata (dmi_pwdata), .dmi_pwdata (dmi_pwdata),
.dmi_prdata (dmi_prdata), .dmi_prdata (dmi_prdata),
.dmi_pready (dmi_pready), .dmi_pready (dmi_pready),

14
hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v
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@ -34,7 +34,8 @@
module hazard3_ecp5_jtag_dtm #( module hazard3_ecp5_jtag_dtm #(
parameter DTMCS_IDLE_HINT = 3'd4, parameter DTMCS_IDLE_HINT = 3'd4,
parameter W_ADDR = 8 parameter W_PADDR = 9,
parameter ABITS = W_PADDR - 2 // do not modify
) ( ) (
// This is synchronous to TCK and asserted for one TCK cycle only // This is synchronous to TCK and asserted for one TCK cycle only
output wire dmihardreset_req, output wire dmihardreset_req,
@ -47,7 +48,7 @@ module hazard3_ecp5_jtag_dtm #(
output wire dmi_psel, output wire dmi_psel,
output wire dmi_penable, output wire dmi_penable,
output wire dmi_pwrite, output wire dmi_pwrite,
output wire [W_ADDR-1:0] dmi_paddr, output wire [W_PADDR-1:0] dmi_paddr,
output wire [31:0] dmi_pwdata, output wire [31:0] dmi_pwdata,
input wire [31:0] dmi_prdata, input wire [31:0] dmi_prdata,
input wire dmi_pready, input wire dmi_pready,
@ -94,7 +95,7 @@ JTAGG jtag_u (
wire jtck = !jtck_posedge_dont_use; wire jtck = !jtck_posedge_dont_use;
localparam W_DR_SHIFT = W_ADDR + 32 + 2; localparam W_DR_SHIFT = ABITS + 32 + 2;
reg core_dr_wen; reg core_dr_wen;
reg core_dr_ren; reg core_dr_ren;
@ -170,8 +171,7 @@ assign jtdo2 = dr_shift_next_halfcycle;
hazard3_jtag_dtm_core #( hazard3_jtag_dtm_core #(
.DTMCS_IDLE_HINT (DTMCS_IDLE_HINT), .DTMCS_IDLE_HINT (DTMCS_IDLE_HINT),
.W_ADDR(W_ADDR), .W_ADDR (ABITS)
.W_DR_SHIFT(W_DR_SHIFT)
) inst_hazard3_jtag_dtm_core ( ) inst_hazard3_jtag_dtm_core (
.tck (jtck), .tck (jtck),
.trst_n (jrst_n), .trst_n (jrst_n),
@ -190,13 +190,15 @@ hazard3_jtag_dtm_core #(
.dmi_psel (dmi_psel), .dmi_psel (dmi_psel),
.dmi_penable (dmi_penable), .dmi_penable (dmi_penable),
.dmi_pwrite (dmi_pwrite), .dmi_pwrite (dmi_pwrite),
.dmi_paddr (dmi_paddr), .dmi_paddr (dmi_paddr[W_PADDR-1:2]),
.dmi_pwdata (dmi_pwdata), .dmi_pwdata (dmi_pwdata),
.dmi_prdata (dmi_prdata), .dmi_prdata (dmi_prdata),
.dmi_pready (dmi_pready), .dmi_pready (dmi_pready),
.dmi_pslverr (dmi_pslverr) .dmi_pslverr (dmi_pslverr)
); );
assign dmi_paddr[1:0] = 2'b00;
endmodule endmodule
`default_nettype wire `default_nettype wire

13
hdl/debug/dtm/hazard3_jtag_dtm.v
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@ -25,7 +25,8 @@
module hazard3_jtag_dtm #( module hazard3_jtag_dtm #(
parameter IDCODE = 32'h0000_0001, parameter IDCODE = 32'h0000_0001,
parameter DTMCS_IDLE_HINT = 3'd4, parameter DTMCS_IDLE_HINT = 3'd4,
parameter W_ADDR = 8 parameter W_PADDR = 9,
parameter ABITS = W_PADDR - 2 // do not modify
) ( ) (
// Standard JTAG signals -- the JTAG hardware is clocked directly by TCK. // Standard JTAG signals -- the JTAG hardware is clocked directly by TCK.
input wire tck, input wire tck,
@ -45,7 +46,7 @@ module hazard3_jtag_dtm #(
output wire dmi_psel, output wire dmi_psel,
output wire dmi_penable, output wire dmi_penable,
output wire dmi_pwrite, output wire dmi_pwrite,
output wire [W_ADDR-1:0] dmi_paddr, output wire [W_PADDR-1:0] dmi_paddr,
output wire [31:0] dmi_pwdata, output wire [31:0] dmi_pwdata,
input wire [31:0] dmi_prdata, input wire [31:0] dmi_prdata,
input wire dmi_pready, input wire dmi_pready,
@ -131,7 +132,7 @@ end
// Shift register is sized to largest DR, which is DMI: // Shift register is sized to largest DR, which is DMI:
// {addr[7:0], data[31:0], op[1:0]} // {addr[7:0], data[31:0], op[1:0]}
localparam W_DR_SHIFT = W_ADDR + 32 + 2; localparam W_DR_SHIFT = ABITS + 32 + 2;
reg [W_DR_SHIFT-1:0] dr_shift; reg [W_DR_SHIFT-1:0] dr_shift;
@ -188,7 +189,7 @@ assign core_dr_wdata = dr_shift;
hazard3_jtag_dtm_core #( hazard3_jtag_dtm_core #(
.DTMCS_IDLE_HINT (DTMCS_IDLE_HINT), .DTMCS_IDLE_HINT (DTMCS_IDLE_HINT),
.W_ADDR (W_ADDR) .W_ADDR (ABITS)
) dtm_core ( ) dtm_core (
.tck (tck), .tck (tck),
.trst_n (trst_n), .trst_n (trst_n),
@ -206,13 +207,15 @@ hazard3_jtag_dtm_core #(
.dmi_psel (dmi_psel), .dmi_psel (dmi_psel),
.dmi_penable (dmi_penable), .dmi_penable (dmi_penable),
.dmi_pwrite (dmi_pwrite), .dmi_pwrite (dmi_pwrite),
.dmi_paddr (dmi_paddr), .dmi_paddr (dmi_paddr[W_PADDR-1:2]),
.dmi_pwdata (dmi_pwdata), .dmi_pwdata (dmi_pwdata),
.dmi_prdata (dmi_prdata), .dmi_prdata (dmi_prdata),
.dmi_pready (dmi_pready), .dmi_pready (dmi_pready),
.dmi_pslverr (dmi_pslverr) .dmi_pslverr (dmi_pslverr)
); );
assign dmi_paddr[1:0] = 2'b00;
endmodule endmodule
`default_nettype wire `default_nettype wire

6
hdl/debug/dtm/hazard3_jtag_dtm_core.v
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@ -72,7 +72,7 @@ reg dmi_busy;
wire dtm_psel; wire dtm_psel;
wire dtm_penable; wire dtm_penable;
wire dtm_pwrite; wire dtm_pwrite;
wire [7:0] dtm_paddr; wire [W_ADDR-1:0] dtm_paddr;
wire [31:0] dtm_pwdata; wire [31:0] dtm_pwdata;
wire [31:0] dtm_prdata; wire [31:0] dtm_prdata;
wire dtm_pready; wire dtm_pready;
@ -99,7 +99,7 @@ assign dtm_psel = write_dmi &&
assign dtm_penable = 1'b0; assign dtm_penable = 1'b0;
// paddr/pwdata/pwrite are valid momentarily when psel is asserted. // paddr/pwdata/pwrite are valid momentarily when psel is asserted.
assign dtm_paddr = dr_wdata[34 +: 8]; assign dtm_paddr = dr_wdata[34 +: W_ADDR];
assign dtm_pwrite = dr_wdata[1]; assign dtm_pwrite = dr_wdata[1];
assign dtm_pwdata = dr_wdata[2 +: 32]; assign dtm_pwdata = dr_wdata[2 +: 32];
@ -171,7 +171,7 @@ wire [W_DR_SHIFT-1:0] dtmcs_rdata = {
19'h0, 19'h0,
DTMCS_IDLE_HINT[2:0], DTMCS_IDLE_HINT[2:0],
dmi_cmderr, dmi_cmderr,
6'd8, // abits W_ADDR[5:0], // abits
4'd1 // version 4'd1 // version
}; };

2
test/sim/openocd/tb.v
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@ -132,7 +132,7 @@ hazard3_dm #(
.dmi_psel (dmi_psel), .dmi_psel (dmi_psel),
.dmi_penable (dmi_penable), .dmi_penable (dmi_penable),
.dmi_pwrite (dmi_pwrite), .dmi_pwrite (dmi_pwrite),
.dmi_paddr ({dmi_paddr, 2'b00}), .dmi_paddr (dmi_paddr),
.dmi_pwdata (dmi_pwdata), .dmi_pwdata (dmi_pwdata),
.dmi_prdata (dmi_prdata), .dmi_prdata (dmi_prdata),
.dmi_pready (dmi_pready), .dmi_pready (dmi_pready),