Add synth support.

example_soc/soc/example_soc.v

@@ -10,7 +10,7 @@
 
 module example_soc #(
 	parameter DTM_TYPE   = "JTAG",  // Can be "JTAG" or "ECP5"
-	parameter SRAM_DEPTH = 1 << 15, // Default 32 kwords -> 128 kB
+	parameter SRAM_DEPTH = 1 << 14, // Default 16 kwords -> 64 kB
 	parameter CLK_MHZ    = 12,      // For timer timebase
 
 	`include "hazard3_config.vh"

test/sim/soc_cxxrtl/.gitignore

@@ -2,4 +2,5 @@ tb
 dut.cpp
 build.*
 tb_multicore
+build-tb
 

test/sim/soc_cxxrtl/Makefile

@@ -24,11 +24,37 @@ all: $(TBEXEC)
 
 SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(FILE_LIST);
 SYNTH_CMD += hierarchy -top $(TOP);
-SYNTH_CMD += write_cxxrtl $(BUILD_DIR)/dut.cpp
+SYNTH_CMD += synth -run coarse; opt -fine memory_map; techmap; opt; abc -dff; clean;
+SYNTH_CMD += select -assert-none t:\$[!_];
+SYNTH_CMD += write_verilog -noattr $(BUILD_DIR)/synth.v;
+SYNTH_CMD += synth_ecp5 -top $(TOP) -json $(BUILD_DIR)/soc.json;
+
+synth: $(FILE_LIST) $(wildcard *.vh)
+	mkdir -p $(BUILD_DIR)
+	yosys -p '$(SYNTH_CMD)'
+
+nextpnr:
+	nextpnr-ecp5 --25k --package CABGA381 --speed 6 --lpf-allow-unconstrained --textcfg $(BUILD_DIR)/soc.cfg --lpf soc.lpf --freq 12  --json $(BUILD_DIR)/soc.json
+
+$(BUILD_DIR)/soc.bit: $(BUILD_DIR)/soc.cfg
+	ecppack --svf $(BUILD_DIR)/soc.svf ./$< ./$@
+
+$(BUILD_DIR)/soc.svf : $(BUILD_DIR)/soc.bit
+
+prog: $(BUILD_DIR)/soc.svf
+	ecpdap program $(BUILD_DIR)/soc.svf
+
+flash: $(BUILD_DIR)/soc.bit
+	ecpdap flash write $(BUILD_DIR)/soc.svf
+
+
+CXXRTL_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(FILE_LIST);
+CXXRTL_CMD += hierarchy -top $(TOP);
+CXXRTL_CMD += write_cxxrtl $(BUILD_DIR)/dut.cpp
 
 $(BUILD_DIR)/dut.cpp: $(FILE_LIST) $(wildcard *.vh)
 	mkdir -p $(BUILD_DIR)
-	yosys -p '$(SYNTH_CMD)' 2>&1 > $(BUILD_DIR)/cxxrtl.log
+	yosys -p '$(CXXRTL_CMD)' 2>&1 > $(BUILD_DIR)/cxxrtl.log
 
 clean::
 	rm -rf $(BUILD_DIR) $(TBEXEC)

test/sim/soc_cxxrtl/soc.lpf

@@ -0,0 +1,38 @@
+
+LOCATE COMP "clk" SITE "P3";
+IOBUF PORT "clk" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk" 25 MHZ;
+
+
+LOCATE COMP "trst_n" SITE "D20";
+IOBUF PORT "trst_n" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "trst_n" 25 MHZ;
+
+LOCATE COMP "rst_n" SITE "B19";
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "rst_n" 25 MHZ;
+
+
+
+LOCATE COMP "tdi" SITE "E1";
+IOBUF PORT "tdi" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "tdi" 25 MHZ;
+
+LOCATE COMP "tdo" SITE "E4";
+IOBUF PORT "tdo" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "tck" SITE "F3";
+IOBUF PORT "tck" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "tck" 25 MHZ;
+
+LOCATE COMP "tms" SITE "H3";
+IOBUF PORT "tms" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "tms" 25 MHZ;
+
+
+LOCATE COMP "uart_rx" SITE "J5";
+IOBUF PORT "uart_rx" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "uart_rx" 25 MHZ;
+
+LOCATE COMP "uart_tx" SITE "U16";
+IOBUF PORT "uart_tx" IO_TYPE=LVCMOS33;