Fix forward reference to net
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0a369efc06
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@ -37,7 +37,6 @@ parameter MTVEC_INIT = 32'h00000000,
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// RISC-V ISA and CSR support
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// EXTENSION_A: Support for atomic read/modify/write instructions
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// (currently, only lr.w/sc.w are supported)
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parameter EXTENSION_A = 1,
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// EXTENSION_C: Support for compressed (variable-width) instructions
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@ -391,6 +391,30 @@ hazard3_alu #(
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// AHB transaction request
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wire x_unaligned_addr = d_memop != MEMOP_NONE && (
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bus_hsize_d == HSIZE_WORD && |bus_haddr_d[1:0] ||
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bus_hsize_d == HSIZE_HWORD && bus_haddr_d[0]
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);
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reg mw_local_exclusive_reserved;
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wire x_memop_vld = d_memop != MEMOP_NONE && !(
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|EXTENSION_A && d_memop == MEMOP_SC_W && !mw_local_exclusive_reserved ||
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|EXTENSION_A && d_memop_is_amo && x_amo_phase != 3'h0 && x_amo_phase != 3'h2
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);
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wire x_memop_write =
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d_memop == MEMOP_SW || d_memop == MEMOP_SH || d_memop == MEMOP_SB ||
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|EXTENSION_A && d_memop == MEMOP_SC_W ||
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|EXTENSION_A && d_memop_is_amo && x_amo_phase == 3'h2;
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// Always query the global monitor, except for store-conditional suppressed by local monitor.
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assign bus_aph_excl_d = |EXTENSION_A && (
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d_memop == MEMOP_LR_W ||
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d_memop == MEMOP_SC_W ||
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d_memop_is_amo
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);
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// AMO stalls the pipe, then generates two bus transfers per 4-cycle
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// iteration, unless it bails out due to a bus fault or failed load
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// reservation.
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@ -476,30 +500,6 @@ always @ (posedge clk) if (rst_n) begin
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end
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`endif
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reg mw_local_exclusive_reserved;
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wire x_memop_vld = d_memop != MEMOP_NONE && !(
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|EXTENSION_A && d_memop == MEMOP_SC_W && !mw_local_exclusive_reserved ||
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|EXTENSION_A && d_memop_is_amo && x_amo_phase != 3'h0 && x_amo_phase != 3'h2
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);
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wire x_memop_write =
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d_memop == MEMOP_SW || d_memop == MEMOP_SH || d_memop == MEMOP_SB ||
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|EXTENSION_A && d_memop == MEMOP_SC_W ||
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|EXTENSION_A && d_memop_is_amo && x_amo_phase == 3'h2;
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wire x_unaligned_addr = d_memop != MEMOP_NONE && (
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bus_hsize_d == HSIZE_WORD && |bus_haddr_d[1:0] ||
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bus_hsize_d == HSIZE_HWORD && bus_haddr_d[0]
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);
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// Always query the global monitor, except for store-conditional suppressed by local monitor.
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assign bus_aph_excl_d = |EXTENSION_A && (
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d_memop == MEMOP_LR_W ||
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d_memop == MEMOP_SC_W ||
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d_memop_is_amo
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);
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// This adder is used for both branch targets and load/store addresses.
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// Supporting all branch types already requires rs1 + I-fmt, and pc + B-fmt.
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// B-fmt are almost identical to S-fmt, so we rs1 + S-fmt is almost free.
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@ -70,7 +70,7 @@ end else if (RESET_REGS) begin: real_dualport_reset
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end else begin: real_dualport_noreset
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// This should be inference-compatible on FPGAs with dual-port BRAMs
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reg [W_DATA-1:0] mem [0:N_REGS-1];
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always @ (posedge clk) begin
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if (wen) begin
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mem[waddr] <= wdata;
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