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Fix forward reference to net

This commit is contained in:
Luke Wren 2022-01-18 23:02:26 +00:00
parent 0a369efc06
commit bf15b6c49f
3 changed files with 25 additions and 26 deletions
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1
hdl/hazard3_config.vh
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@ -37,7 +37,6 @@ parameter MTVEC_INIT = 32'h00000000,
// RISC-V ISA and CSR support // RISC-V ISA and CSR support
// EXTENSION_A: Support for atomic read/modify/write instructions // EXTENSION_A: Support for atomic read/modify/write instructions
// (currently, only lr.w/sc.w are supported)
parameter EXTENSION_A = 1, parameter EXTENSION_A = 1,
// EXTENSION_C: Support for compressed (variable-width) instructions // EXTENSION_C: Support for compressed (variable-width) instructions

48
hdl/hazard3_core.v
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@ -391,6 +391,30 @@ hazard3_alu #(
// AHB transaction request // AHB transaction request
wire x_unaligned_addr = d_memop != MEMOP_NONE && (
bus_hsize_d == HSIZE_WORD && |bus_haddr_d[1:0] ||
bus_hsize_d == HSIZE_HWORD && bus_haddr_d[0]
);
reg mw_local_exclusive_reserved;
wire x_memop_vld = d_memop != MEMOP_NONE && !(
|EXTENSION_A && d_memop == MEMOP_SC_W && !mw_local_exclusive_reserved ||
|EXTENSION_A && d_memop_is_amo && x_amo_phase != 3'h0 && x_amo_phase != 3'h2
);
wire x_memop_write =
d_memop == MEMOP_SW || d_memop == MEMOP_SH || d_memop == MEMOP_SB ||
|EXTENSION_A && d_memop == MEMOP_SC_W ||
|EXTENSION_A && d_memop_is_amo && x_amo_phase == 3'h2;
// Always query the global monitor, except for store-conditional suppressed by local monitor.
assign bus_aph_excl_d = |EXTENSION_A && (
d_memop == MEMOP_LR_W ||
d_memop == MEMOP_SC_W ||
d_memop_is_amo
);
// AMO stalls the pipe, then generates two bus transfers per 4-cycle // AMO stalls the pipe, then generates two bus transfers per 4-cycle
// iteration, unless it bails out due to a bus fault or failed load // iteration, unless it bails out due to a bus fault or failed load
// reservation. // reservation.
@ -476,30 +500,6 @@ always @ (posedge clk) if (rst_n) begin
end end
`endif `endif
reg mw_local_exclusive_reserved;
wire x_memop_vld = d_memop != MEMOP_NONE && !(
|EXTENSION_A && d_memop == MEMOP_SC_W && !mw_local_exclusive_reserved ||
|EXTENSION_A && d_memop_is_amo && x_amo_phase != 3'h0 && x_amo_phase != 3'h2
);
wire x_memop_write =
d_memop == MEMOP_SW || d_memop == MEMOP_SH || d_memop == MEMOP_SB ||
|EXTENSION_A && d_memop == MEMOP_SC_W ||
|EXTENSION_A && d_memop_is_amo && x_amo_phase == 3'h2;
wire x_unaligned_addr = d_memop != MEMOP_NONE && (
bus_hsize_d == HSIZE_WORD && |bus_haddr_d[1:0] ||
bus_hsize_d == HSIZE_HWORD && bus_haddr_d[0]
);
// Always query the global monitor, except for store-conditional suppressed by local monitor.
assign bus_aph_excl_d = |EXTENSION_A && (
d_memop == MEMOP_LR_W ||
d_memop == MEMOP_SC_W ||
d_memop_is_amo
);
// This adder is used for both branch targets and load/store addresses. // This adder is used for both branch targets and load/store addresses.
// Supporting all branch types already requires rs1 + I-fmt, and pc + B-fmt. // Supporting all branch types already requires rs1 + I-fmt, and pc + B-fmt.
// B-fmt are almost identical to S-fmt, so we rs1 + S-fmt is almost free. // B-fmt are almost identical to S-fmt, so we rs1 + S-fmt is almost free.

2
hdl/hazard3_regfile_1w2r.v
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@ -70,7 +70,7 @@ end else if (RESET_REGS) begin: real_dualport_reset
end else begin: real_dualport_noreset end else begin: real_dualport_noreset
// This should be inference-compatible on FPGAs with dual-port BRAMs // This should be inference-compatible on FPGAs with dual-port BRAMs
reg [W_DATA-1:0] mem [0:N_REGS-1]; reg [W_DATA-1:0] mem [0:N_REGS-1];
always @ (posedge clk) begin always @ (posedge clk) begin
if (wen) begin if (wen) begin
mem[waddr] <= wdata; mem[waddr] <= wdata;