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Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests. 

Fix a couple of minor test script issues.
This commit is contained in:
Luke Wren 2023-03-26 23:00:18 +01:00
parent 94bd965e4e
commit c41fe0609b
4 changed files with 33 additions and 18 deletions
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2
test/sim/riscv-tests/run-smp-debug-tests.sh
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@ -20,7 +20,7 @@ CheckMisa \
MulticoreRegTest \
MulticoreRtosSwitchActiveHartTest \
SmpSimultaneousRunHalt \
CrashLoopOpcode \
CrashLoopOpcode \
DebugBreakpoint \
DebugChangeString \
DebugCompareSections \

2
test/sim/tb_cxxrtl/Makefile
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@ -1,7 +1,7 @@
TOP := tb
DOTF := tb.f
CONFIG := default
TBEXEC := $(patsubst %.f,%,DOTF)
TBEXEC := $(patsubst %.f,%,$(DOTF))
.PHONY: clean all

41
test/sim/tb_cxxrtl/tb.cpp
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@ -37,13 +37,15 @@ enum {
IO_CLR_IRQ = 0x030,
IO_MTIME = 0x100,
IO_MTIMEH = 0x104,
IO_MTIMECMP = 0x108,
IO_MTIMECMPH = 0x10c
IO_MTIMECMP0 = 0x108,
IO_MTIMECMP0H = 0x10c,
IO_MTIMECMP1 = 0x110,
IO_MTIMECMP1H = 0x114
};
struct mem_io_state {
uint64_t mtime;
uint64_t mtimecmp;
uint64_t mtimecmp[2];
bool exit_req;
uint32_t exit_code;
@ -56,7 +58,8 @@ struct mem_io_state {
mem_io_state() {
mtime = 0;
mtimecmp = 0;
mtimecmp[0] = 0;
mtimecmp[1] = 0;
exit_req = false;
exit_code = 0;
monitor_enabled = false;
@ -74,7 +77,7 @@ struct mem_io_state {
void step(cxxrtl_design::p_tb &tb) {
// Default update logic for mtime, mtimecmp
++mtime;
tb.p_timer__irq.set<bool>(mtime >= mtimecmp);
tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime >= mtimecmp[1]) << 1);
}
};
@ -188,11 +191,17 @@ bus_response mem_access(cxxrtl_design::p_tb &tb, mem_io_state &memio, bus_reques
else if (req.addr == IO_BASE + IO_MTIMEH) {
memio.mtime = (memio.mtime & 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
}
else if (req.addr == IO_BASE + IO_MTIMECMP) {
memio.mtimecmp = (memio.mtimecmp & 0xffffffff00000000u) | req.wdata;
else if (req.addr == IO_BASE + IO_MTIMECMP0) {
memio.mtimecmp[0] = (memio.mtimecmp[0] & 0xffffffff00000000u) | req.wdata;
}
else if (req.addr == IO_BASE + IO_MTIMECMPH) {
memio.mtimecmp = (memio.mtimecmp & 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
else if (req.addr == IO_BASE + IO_MTIMECMP0H) {
memio.mtimecmp[0] = (memio.mtimecmp[0] & 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
}
else if (req.addr == IO_BASE + IO_MTIMECMP1) {
memio.mtimecmp[1] = (memio.mtimecmp[1] & 0xffffffff00000000u) | req.wdata;
}
else if (req.addr == IO_BASE + IO_MTIMECMP1H) {
memio.mtimecmp[1] = (memio.mtimecmp[1] & 0x00000000ffffffffu) | ((uint64_t)req.wdata << 32);
}
else {
resp.err = true;
@ -219,11 +228,17 @@ bus_response mem_access(cxxrtl_design::p_tb &tb, mem_io_state &memio, bus_reques
else if (req.addr == IO_BASE + IO_MTIMEH) {
resp.rdata = memio.mtime >> 32;
}
else if (req.addr == IO_BASE + IO_MTIMECMP) {
resp.rdata = memio.mtimecmp;
else if (req.addr == IO_BASE + IO_MTIMECMP0) {
resp.rdata = memio.mtimecmp[0];
}
else if (req.addr == IO_BASE + IO_MTIMECMPH) {
resp.rdata = memio.mtimecmp >> 32;
else if (req.addr == IO_BASE + IO_MTIMECMP0H) {
resp.rdata = memio.mtimecmp[0] >> 32;
}
else if (req.addr == IO_BASE + IO_MTIMECMP1) {
resp.rdata = memio.mtimecmp[1];
}
else if (req.addr == IO_BASE + IO_MTIMECMP1H) {
resp.rdata = memio.mtimecmp[1] >> 32;
}
else {
resp.err = true;

6
test/sim/tb_cxxrtl/tb_multicore.v
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@ -51,7 +51,7 @@ module tb #(
// Level-sensitive interrupt sources
input wire [NUM_IRQS-1:0] irq, // -> mip.meip
input wire [1:0] soft_irq, // -> mip.msip
input wire timer_irq // -> mip.mtip
input wire [1:0] timer_irq // -> mip.mtip
);
// JTAG-DTM IDCODE, selected after TAP reset, would normally be a
@ -278,7 +278,7 @@ hazard3_cpu_1port #(
.irq (irq),
.soft_irq (soft_irq[0]),
.timer_irq (timer_irq)
.timer_irq (timer_irq[0])
);
hazard3_cpu_1port #(
@ -337,7 +337,7 @@ hazard3_cpu_1port #(
.irq (irq),
.soft_irq (soft_irq[1]),
.timer_irq (timer_irq)
.timer_irq (timer_irq[1])
);