diff --git a/test/sim/common/init.S b/test/sim/common/init.S
index fe04255..e308d48 100644
--- a/test/sim/common/init.S
+++ b/test/sim/common/init.S
@@ -17,6 +17,7 @@
 .macro VEC name:req
 .p2align 2
 j \name
+.p2align 2
 .endm
 
 // ----------------------------------------------------------------------------
@@ -49,46 +50,10 @@ j \name
 	VEC .halt
 	VEC .halt
 
-// When midcr.eivect is 1, hardware vectors IRQs directly to the
-// platform-specific part of the vector table. Otherwise, software indexes
-// this table in the prologue of a shared external IRQ handler.
-
-.p2align 2
-platform_vectors:
-
-	VEC isr_irq0
-	VEC isr_irq1
-	VEC isr_irq2
-	VEC isr_irq3
-	VEC isr_irq4
-	VEC isr_irq5
-	VEC isr_irq6
-	VEC isr_irq7
-	VEC isr_irq8
-	VEC isr_irq9
-	VEC isr_irq10
-	VEC isr_irq11
-	VEC isr_irq12
-	VEC isr_irq13
-	VEC isr_irq14
-	VEC isr_irq15
-	VEC isr_irq16
-	VEC isr_irq17
-	VEC isr_irq18
-	VEC isr_irq19
-	VEC isr_irq20
-	VEC isr_irq21
-	VEC isr_irq22
-	VEC isr_irq23
-	VEC isr_irq24
-	VEC isr_irq25
-	VEC isr_irq26
-	VEC isr_irq27
-	VEC isr_irq28
-	VEC isr_irq29
-	VEC isr_irq30
-	VEC isr_irq31
-
+// TODO remove (update ldscripts first)
+.rept 32
+.word 0
+.endr
 
 // ----------------------------------------------------------------------------
 // Reset handler
@@ -133,92 +98,7 @@ heap_ptr:
 	j .halt
 
 progname:
-	.asciz "hazard5-testbench"
-
-// ----------------------------------------------------------------------------
-// Soft external IRQ dispatch
-
-// Vector isr_external_irq to the relevant ISR, based on mcause. The ISR can
-// be a standard C-ABI function. This method also leaves the possibility of
-// using addresses in the IRQ vector table, rather than jump instructions.
-
-.global isr_external_irq
-.weak isr_external_irq
-isr_external_irq:
-	// Save all caller-saves, plus three callee saves for CSR saving
-	addi sp, sp, -80
-	sw ra,  0(sp)
-	sw t0,  4(sp)
-	sw t1,  8(sp)
-	sw t2, 12(sp)
-	sw t3, 16(sp)
-	sw t4, 20(sp)
-	sw t5, 24(sp)
-	sw t6, 28(sp)
-	sw a0, 32(sp)
-	sw a1, 36(sp)
-	sw a2, 40(sp)
-	sw a3, 44(sp)
-	sw a4, 48(sp)
-	sw a5, 52(sp)
-	sw a6, 56(sp)
-	sw a7, 60(sp)
-	sw s0, 64(sp)
-	sw s1, 68(sp)
-	sw s2, 72(sp)
-
-	// Save exception state to callee-saves so we can use it for return
-	csrr s0, mepc
-	csrr s1, mstatus
-	csrr s2, hazard3_csr_meie0
-
-	// Calculate IRQ entry point
-	csrr a0, mcause
-	slli a0, a0, 2
-	csrr a1, mtvec
-	andi a1, a1, -4
-	add a1, a1, a0
-
-	// Mask off higher-numbered IRQs (and this IRQ), then re-enable IRQs so we
-	// can be preempted. Could have some other priority scheme here.
-	srli a0, a0, 2
-	addi a0, a0, -16
-	li a2, -1
-	sll a2, a2, a0
-	csrc hazard3_csr_meie0, a2
-	csrsi mstatus, 8
-
-	// Enter IRQ
-	jalr a1
-trap_return:
-	// No more preemption until we mret.
-	csrci mstatus, 8
-	
-	csrw mepc, s0
-	csrw mstatus, s1
-	csrw hazard3_csr_meie0, s2
-	lw ra,  0(sp)
-	lw t0,  4(sp)
-	lw t1,  8(sp)
-	lw t2, 12(sp)
-	lw t3, 16(sp)
-	lw t4, 20(sp)
-	lw t5, 24(sp)
-	lw t6, 28(sp)
-	lw a0, 32(sp)
-	lw a1, 36(sp)
-	lw a2, 40(sp)
-	lw a3, 44(sp)
-	lw a4, 48(sp)
-	lw a5, 52(sp)
-	lw a6, 56(sp)
-	lw a7, 60(sp)
-	lw s0, 64(sp)
-	lw s1, 68(sp)
-	lw s2, 72(sp)
-	addi sp, sp, 80
-	mret
-
+	.asciz "hazard3-testbench"
 
 // ----------------------------------------------------------------------------
 // Weak handler/ISR symbols
@@ -307,38 +187,7 @@ _str_\name:
 weak_handler handle_exception
 weak_handler isr_machine_softirq
 weak_handler isr_machine_timer
-weak_handler isr_irq0
-weak_handler isr_irq1
-weak_handler isr_irq2
-weak_handler isr_irq3
-weak_handler isr_irq4
-weak_handler isr_irq5
-weak_handler isr_irq6
-weak_handler isr_irq7
-weak_handler isr_irq8
-weak_handler isr_irq9
-weak_handler isr_irq10
-weak_handler isr_irq11
-weak_handler isr_irq12
-weak_handler isr_irq13
-weak_handler isr_irq14
-weak_handler isr_irq15
-weak_handler isr_irq16
-weak_handler isr_irq17
-weak_handler isr_irq18
-weak_handler isr_irq19
-weak_handler isr_irq20
-weak_handler isr_irq21
-weak_handler isr_irq22
-weak_handler isr_irq23
-weak_handler isr_irq24
-weak_handler isr_irq25
-weak_handler isr_irq26
-weak_handler isr_irq27
-weak_handler isr_irq28
-weak_handler isr_irq29
-weak_handler isr_irq30
-weak_handler isr_irq31
+weak_handler isr_external_irq
 
 // You can relax now
 .option pop