Add mconfigptr CSR
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doc/hazard3.pdf
17864
doc/hazard3.pdf
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@ -61,6 +61,18 @@ Hart identification register. Read-only, configurable constant.
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| 31:0 | - | Hazard3 cores possess only one hardware thread, so this is a unique per-core identifier, assigned consecutively from 0.
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|===
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==== mconfigptr
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Address: `0xf15`
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Pointer to configuration data structure. Read-only, configurable constant.
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[cols="10h,20h,~", options="header"]
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|===
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| Bits | Name | Description
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| 31:0 | - | Either pointer to configuration data structure, containing information about the harts and system, or all-zeroes. At least 4-byte-aligned.
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|===
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==== mstatus
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Address: `0x300`
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@ -315,7 +327,7 @@ Unimplemented. Access will cause an illegal instruction exception.
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=== Standard Debug Mode CSRs
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This section describes the Debug Mode CSRs, which are follow the 0.13.2 RISC-V debug specification. The <<debug-chapter>> section gives more detail on the remainder of Hazard3's debug implementation, including the Debug Module.
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This section describes the Debug Mode CSRs, which follow the 0.13.2 RISC-V debug specification. The <<debug-chapter>> section gives more detail on the remainder of Hazard3's debug implementation, including the Debug Module.
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All Debug Mode CSRs are 32-bit; DXLEN is always 32.
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@ -74,13 +74,17 @@ parameter NUM_IRQ = 32,
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// JEDEC JEP106-compliant vendor ID, can be left at 0 if "not implemented or
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// [...] this is a non-commercial implementation" (RISC-V spec).
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// 31:7 is continuation code count, 6:0 is ID. Parity bit is not stored.
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parameter MVENDORID_VAL = 32'h0,
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parameter MVENDORID_VAL = 32'h0,
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// Implementation ID for this specific version of Hazard3. Git hash is perfect.
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parameter MIMPID_VAL = 32'h0,
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parameter MIMPID_VAL = 32'h0,
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// Each core has a single hardware thread. Multiple cores should have unique IDs.
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parameter MHARTID_VAL = 32'h0,
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parameter MHARTID_VAL = 32'h0,
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// Pointer to configuration structure blob, or all-zeroes. Must be at least
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// 4-byte-aligned.
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parameter MCONFIGPTR_VAL = 32'h0,
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// ----------------------------------------------------------------------------
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// Performance/size options
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@ -18,6 +18,7 @@
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.MVENDORID_VAL (MVENDORID_VAL),
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.MIMPID_VAL (MIMPID_VAL),
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.MHARTID_VAL (MHARTID_VAL),
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.MCONFIGPTR_VAL (MCONFIGPTR_VAL),
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.REDUCED_BYPASS (REDUCED_BYPASS),
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.MULDIV_UNROLL (MULDIV_UNROLL),
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.MUL_FAST (MUL_FAST),
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@ -120,6 +120,7 @@ localparam MVENDORID = 12'hf11; // Vendor ID.
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localparam MARCHID = 12'hf12; // Architecture ID.
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localparam MIMPID = 12'hf13; // Implementation ID.
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localparam MHARTID = 12'hf14; // Hardware thread ID.
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localparam MCONFIGPTR = 12'hf15; // Pointer to configuration data structure.
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// Machine Trap Setup (RW)
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localparam MSTATUS = 12'h300; // Machine status register.
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@ -616,6 +617,11 @@ always @ (*) begin
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rdata = MHARTID_VAL;
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end
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MCONFIGPTR: if (CSR_M_MANDATORY) begin
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decode_match = !wen_soon; // MRO
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rdata = MCONFIGPTR_VAL;
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end
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MSTATUS: if (CSR_M_MANDATORY || CSR_M_TRAP) begin
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decode_match = 1'b1;
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rdata = {
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