Add option for fast high-half multiplies
This commit is contained in:
Luke Wren
parent
35c5e213c7
commit
c8afb4ac33
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@ -15,21 +15,55 @@
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* *
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*********************************************************************/
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// MUL-only (cfg: MUL_FAST) and MUL/MULH/MULHU/MULHSU (cfg: MUL_FAST &&
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// MULH_FAST) are handled by different circuits. In either case it's a simple
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// behavioural multiply, and we rely on inference to get good performance on
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// FPGA.
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`default_nettype none
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module hazard3_mul_fast #(
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parameter XLEN = 32
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire clk,
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input wire rst_n,
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input wire [XLEN-1:0] op_a,
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input wire [XLEN-1:0] op_b,
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input wire op_vld,
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input wire clk,
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input wire rst_n,
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output wire [XLEN-1:0] result,
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input wire [W_MULOP-1:0] op,
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input wire op_vld,
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input wire [W_DATA-1:0] op_a,
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input wire [W_DATA-1:0] op_b,
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output wire [W_DATA-1:0] result,
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output reg result_vld
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);
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`include "hazard3_ops.vh"
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localparam XLEN = W_DATA;
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//synthesis translate_off
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generate if (MULH_FAST && !MUL_FAST)
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initial $fatal("%m: MULH_FAST requires that MUL_FAST is also set.");
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endgenerate
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//synthesis translate_on
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// Latency of 1:
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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result_vld <= 1'b0;
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end else begin
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result_vld <= op_vld;
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end
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end
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// ----------------------------------------------------------------------------
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// Fast MUL only
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generate
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if (!MULH_FAST) begin: mul_only
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// This pipestage is folded into the front of the DSP tiles on UP5k. Note the
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// intention is to register the bypassed core regs at the end of X (since
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// bypass is quite slow), then perform multiply combinatorially in stage M,
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@ -66,14 +100,55 @@ assign result = result_vld ? (op_a_r + op_b_r) ^ 32'h5876063e : 32'hdeadbeef;
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`endif
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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result_vld <= 1'b0;
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end else begin
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result_vld <= op_vld;
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// ----------------------------------------------------------------------------
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// Fast MUL/MULH/MULHU/MULHSU
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end else begin: mul_and_mulh
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reg [XLEN-1:0] op_a_r;
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reg [XLEN-1:0] op_b_r;
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reg [W_MULOP-1:0] op_r;
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always @ (posedge clk) begin
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if (op_vld) begin
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op_a_r <= op_a;
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op_b_r <= op_b;
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op_r <= op;
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end
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end
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wire op_a_signed = op_r == M_OP_MULH || op_r == M_OP_MULHSU;
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wire op_b_signed = op_r == M_OP_MULH;
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wire [2*XLEN-1:0] op_a_sext = {
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{XLEN{op_a_r[XLEN - 1] && op_a_signed}},
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op_a_r
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};
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wire [2*XLEN-1:0] op_b_sext = {
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{XLEN{op_b_r[XLEN - 1] && op_b_signed}},
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op_b_r
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};
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wire [2*XLEN-1:0] result_full = op_a_sext * op_b_sext;
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`ifndef RISCV_FORMAL_ALTOPS
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assign result = op_r == M_OP_MUL ? result_full[0 +: XLEN] : result_full[XLEN +: XLEN];
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`else
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assign result =
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op_r == M_OP_MULH ? (op_a_r + op_b_r) ^ 32'hf6583fb7 :
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op_r == M_OP_MULHSU ? (op_a_r - op_b_r) ^ 32'hecfbe137 :
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op_r == M_OP_MULHU ? (op_a_r + op_b_r) ^ 32'h949ce5e8 :
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op_r == M_OP_MUL ? (op_a_r + op_b_r) ^ 32'h5876063e : 32'hdeadbeef;
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`endif
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end
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endgenerate
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endmodule
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`default_nettype wire
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@ -30,9 +30,8 @@
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`default_nettype none
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module hazard3_muldiv_seq #(
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parameter XLEN = 32,
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parameter UNROLL = 1,
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parameter W_CTR = $clog2(XLEN + 1), // do not modify
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire clk,
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@ -41,22 +40,25 @@ module hazard3_muldiv_seq #(
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input wire op_vld,
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output wire op_rdy,
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input wire op_kill,
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input wire [XLEN-1:0] op_a,
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input wire [XLEN-1:0] op_b,
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input wire [W_DATA-1:0] op_a,
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input wire [W_DATA-1:0] op_b,
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output wire [XLEN-1:0] result_h, // mulh* or rem*
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output wire [XLEN-1:0] result_l, // mul or div*
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output wire [W_DATA-1:0] result_h, // mulh* or rem*
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output wire [W_DATA-1:0] result_l, // mul or div*
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output wire result_vld
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);
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`include "hazard3_ops.vh"
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//synthesis translate_off
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generate if (UNROLL & (UNROLL - 1) || ~|UNROLL)
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initial $fatal("%m: UNROLL must be a positive power of 2");
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generate if (MULDIV_UNROLL & (MULDIV_UNROLL - 1) || ~|MULDIV_UNROLL)
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initial $fatal("%m: MULDIV_UNROLL must be a positive power of 2");
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endgenerate
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//synthesis translate_on
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localparam XLEN = W_DATA;
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parameter W_CTR = $clog2(XLEN + 1);
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// ----------------------------------------------------------------------------
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// Operation decode, operand sign adjustment
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@ -85,7 +87,10 @@ wire op_b_signed =
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wire op_a_neg = op_a_signed && accum[XLEN-1];
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wire op_b_neg = op_b_signed && op_b_r[XLEN-1];
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wire is_div = op_r[2];
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// Non-divide parts of the circuit should be constant-folded if all the MUL
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// operations are handled by the fast multiplier
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wire is_div = op_r[2] || (MUL_FAST && MULH_FAST);
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// Controls for modifying sign of all/part of accumulator
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wire accum_neg_l;
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@ -109,7 +114,7 @@ always @ (*) begin: alu
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addend = {2*XLEN{1'b0}};
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addsub_tmp = {2*XLEN{1'b0}};
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neg_l_borrow = 1'b0;
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for (i = 0; i < UNROLL; i = i + 1) begin
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for (i = 0; i < MULDIV_UNROLL; i = i + 1) begin
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addend = {is_div && |op_b_r, op_b_r, {XLEN-1{1'b0}}};
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shift_tmp = is_div ? accum_next : accum_next >> 1;
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addsub_tmp = shift_tmp + addend;
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@ -167,11 +172,11 @@ always @ (posedge clk or negedge rst_n) begin
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if (op_b_neg ^ is_div)
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op_b_r <= -op_b_r;
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end else begin
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ctr <= ctr - UNROLL[W_CTR-1:0];
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ctr <= ctr - MULDIV_UNROLL[W_CTR-1:0];
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accum <= accum_next;
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end
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end else if (|ctr) begin
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ctr <= ctr - UNROLL[W_CTR-1:0];
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ctr <= ctr - MULDIV_UNROLL[W_CTR-1:0];
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accum <= accum_next;
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end else if (!sign_postadj_done || sign_postadj_carry) begin
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sign_postadj_done <= 1'b1;
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@ -287,7 +292,7 @@ always @ (posedge clk) if (rst_n && $past(rst_n)) begin: properties
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// are forced in immediately, simultaneous with a kill, in which case there
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// is no intermediate ready state.
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alive = op_rdy || (op_kill && op_vld);
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for (i = 1; i <= XLEN / UNROLL + 3; i = i + 1)
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for (i = 1; i <= XLEN / MULDIV_UNROLL + 3; i = i + 1)
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alive = alive || $past(op_rdy || (op_kill && op_vld), i);
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assert(alive);
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end
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@ -94,10 +94,14 @@ parameter REDUCED_BYPASS = 0,
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parameter MULDIV_UNROLL = 1,
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// MUL_FAST: Use single-cycle multiply circuit for MUL instructions, retiring
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// to stage M. The sequential multiply/divide circuit is still used for
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// MULH/MULHU/MULHSU.
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// to stage M. The sequential multiply/divide circuit is still used for MULH*
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parameter MUL_FAST = 0,
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// MULH_FAST: extend the fast multiply circuit to also cover MULH*, and remove
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// the multiply functionality from the sequential multiply/divide circuit.
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// Requires; MUL_FAST
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parameter MULH_FAST = 0,
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// MTVEC_WMASK: Mask of which bits in MTVEC are modifiable. Save gates by
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// making trap vector base partly fixed (legal, as it's WARL).
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//
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@ -105,7 +109,7 @@ parameter MUL_FAST = 0,
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//
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// - Note the entire vector table must always be aligned to its size, rounded
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// up to a power of two, so careful with the low-order bits.
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parameter MTVEC_WMASK = 32'hffffffff,
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parameter MTVEC_WMASK = 32'hfffffffd,
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// ----------------------------------------------------------------------------
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// Port size parameters (do not modify)
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@ -21,6 +21,7 @@
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.REDUCED_BYPASS (REDUCED_BYPASS),
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.MULDIV_UNROLL (MULDIV_UNROLL),
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.MUL_FAST (MUL_FAST),
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.MULH_FAST (MULH_FAST),
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.MTVEC_WMASK (MTVEC_WMASK),
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.W_ADDR (W_ADDR),
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.W_DATA (W_DATA)
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@ -406,14 +406,18 @@ if (EXTENSION_M) begin: has_muldiv
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wire x_muldiv_kill = m_trap_enter_soon;
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wire x_use_fast_mul = MUL_FAST && d_aluop == ALUOP_MULDIV && d_mulop == M_OP_MUL;
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wire x_use_fast_mul = d_aluop == ALUOP_MULDIV && (
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MUL_FAST && d_mulop == M_OP_MUL ||
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MULH_FAST && d_mulop == M_OP_MULH ||
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MULH_FAST && d_mulop == M_OP_MULHU ||
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MULH_FAST && d_mulop == M_OP_MULHSU
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);
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assign x_muldiv_op_vld = (d_aluop == ALUOP_MULDIV && !x_use_fast_mul)
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&& !(x_muldiv_posted || x_stall_raw || x_muldiv_kill);
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hazard3_muldiv_seq #(
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.XLEN (W_DATA),
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.UNROLL (MULDIV_UNROLL)
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`include "hazard3_config_inst.vh"
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) muldiv (
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.clk (clk),
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.rst_n (rst_n),
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@ -444,14 +448,15 @@ if (EXTENSION_M) begin: has_muldiv
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wire x_issue_fast_mul = x_use_fast_mul && |d_rd && !x_stall;
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hazard3_mul_fast #(
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.XLEN(W_DATA)
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) inst_hazard3_mul_fast (
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`include "hazard3_config_inst.vh"
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) mul_fast (
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.clk (clk),
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.rst_n (rst_n),
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.op_vld (x_issue_fast_mul),
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.op (d_mulop),
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.op_a (x_rs1_bypass),
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.op_b (x_rs2_bypass),
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.op_vld (x_issue_fast_mul),
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.result (m_fast_mul_result),
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.result_vld (m_fast_mul_result_vld)
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@ -2,11 +2,18 @@ TOP := hazard3_cpu_2port
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CDEFINES := DUAL_PORT
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CPU_RESET_VECTOR := 32'hc0
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EXTENSION_C := 1
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EXTENSION_M := 1
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EXTENSION_ZBA := 1
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EXTENSION_ZBB := 1
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EXTENSION_ZBC := 1
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EXTENSION_ZBS := 1
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DEBUG_SUPPORT := 0
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MULDIV_UNROLL := 2
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MUL_FAST := 1
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MULH_FAST := 1
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REDUCED_BYPASS := 0
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.PHONY: clean tb all
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@ -16,12 +23,17 @@ all: tb
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SYNTH_CMD += read_verilog -I ../../../hdl $(shell listfiles ../../../hdl/hazard3.f);
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SYNTH_CMD += chparam -set EXTENSION_C $(EXTENSION_C) $(TOP);
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SYNTH_CMD += chparam -set EXTENSION_M $(EXTENSION_M) $(TOP);
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SYNTH_CMD += chparam -set EXTENSION_ZBA $(EXTENSION_ZBA) $(TOP);
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SYNTH_CMD += chparam -set EXTENSION_ZBB $(EXTENSION_ZBB) $(TOP);
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SYNTH_CMD += chparam -set EXTENSION_ZBC $(EXTENSION_ZBC) $(TOP);
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SYNTH_CMD += chparam -set EXTENSION_ZBS $(EXTENSION_ZBS) $(TOP);
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SYNTH_CMD += chparam -set DEBUG_SUPPORT $(DEBUG_SUPPORT) $(TOP);
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SYNTH_CMD += chparam -set CSR_COUNTER 1 $(TOP);
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SYNTH_CMD += chparam -set RESET_VECTOR $(CPU_RESET_VECTOR) $(TOP);
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SYNTH_CMD += chparam -set REDUCED_BYPASS $(REDUCED_BYPASS) $(TOP);
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SYNTH_CMD += chparam -set MULDIV_UNROLL $(MULDIV_UNROLL) $(TOP);
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SYNTH_CMD += chparam -set MUL_FAST $(MUL_FAST) $(TOP);
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SYNTH_CMD += chparam -set MULH_FAST $(MULH_FAST) $(TOP);
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SYNTH_CMD += write_cxxrtl dut.cpp
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dut.cpp:
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