diff --git a/test/sim/bitmanip-random/memmap.ld b/test/sim/bitmanip-random/memmap.ld
index 44a1dd1..c9b281e 100644
--- a/test/sim/bitmanip-random/memmap.ld
+++ b/test/sim/bitmanip-random/memmap.ld
@@ -11,7 +11,7 @@ ENTRY(_start)
 SECTIONS
 {
   .text : {
-    . = ORIGIN(RAM) + 0xc0;
+    . = ORIGIN(RAM) + 0x40;
     PROVIDE (_start = .);
     *(.text*)
     . = ALIGN(4);
diff --git a/test/sim/common/init.S b/test/sim/common/init.S
index ebd63dc..8f0851b 100644
--- a/test/sim/common/init.S
+++ b/test/sim/common/init.S
@@ -49,11 +49,6 @@ j \name
 	VEC .halt
 	VEC .halt
 
-// TODO remove (update ldscripts first)
-.rept 32
-.word 0
-.endr
-
 // ----------------------------------------------------------------------------
 // Reset handler
 
diff --git a/test/sim/riscv-compliance/memmap.ld b/test/sim/riscv-compliance/memmap.ld
index deb98b3..08b3c77 100644
--- a/test/sim/riscv-compliance/memmap.ld
+++ b/test/sim/riscv-compliance/memmap.ld
@@ -11,7 +11,7 @@ ENTRY(_start)
 SECTIONS
 {
   .text : {
-    . = ORIGIN(RAM) + 0xc0;
+    . = ORIGIN(RAM) + 0x40;
     PROVIDE (_start = .);
     *(.text*)
     . = ALIGN(4);
diff --git a/test/sim/riscv-compliance/run_32i.sh b/test/sim/riscv-compliance/run_32i.sh
old mode 100644
new mode 100755
diff --git a/test/sim/tb_cxxrtl/Makefile b/test/sim/tb_cxxrtl/Makefile
index 8b409ab..abdfd14 100644
--- a/test/sim/tb_cxxrtl/Makefile
+++ b/test/sim/tb_cxxrtl/Makefile
@@ -1,6 +1,6 @@
 TOP              := tb
 
-CPU_RESET_VECTOR := 32'hc0
+CPU_RESET_VECTOR := 32'h40
 
 EXTENSION_C      := 1
 EXTENSION_M      := 1