Ignore read data from failed SBA accesses
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@ -331,7 +331,7 @@ always @ (posedge clk or negedge rst_n) begin
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end else if (HAVE_SBA) begin
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if (dmi_write && dmi_regaddr == ADDR_SBDATA0 && !sbbusy) begin
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sbdata <= dmi_pwdata;
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end else if (sbus_vld && sbus_rdy && !sbus_write) begin
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end else if (sbus_vld && sbus_rdy && !sbus_write && !sbus_err) begin
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// Make sure the lower byte lanes see appropriately shifted data as
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// long as the transfer is naturally aligned
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sbdata <= sbaddress[1:0] == 2'b01 ? {sbus_rdata[31:8], sbus_rdata[15:8]} :
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