diff --git a/hdl/hazard3_frontend.v b/hdl/hazard3_frontend.v
index 4ec010a..62dad53 100644
--- a/hdl/hazard3_frontend.v
+++ b/hdl/hazard3_frontend.v
@@ -304,8 +304,14 @@ wire next_instr_is_32bit = next_instr[1:0] == 2'b11;
 assign next_regs_vld = next_instr_is_32bit ? buf_level_next[1] : |buf_level_next;
 
 assign next_regs_rs1 =
-	next_instr_is_32bit      ? next_instr[19:15] :
-	next_instr[1:0] == 2'b10 ? next_instr[11:7]  : {2'b01, next_instr[9:7]};
+	next_instr_is_32bit                                     ? next_instr[19:15]       : // 32-bit R, S, B formats
+	next_instr[1:0] == 2'b00 && next_instr[15:13] == 3'b000 ? 5'd2                    : // c.addi4spn
+	next_instr[1:0] == 2'b01 && next_instr[15:13] == 3'b011 ? 5'd2                    : // c.addi16sp
+	next_instr[1:0] == 2'b10 && next_instr[15:13] == 3'b010 ? 5'd2                    : // c.lwsp
+	next_instr[1:0] == 2'b10 && next_instr[15:13] == 3'b110 ? 5'd2                    : // c.swsp
+	next_instr[1:0] == 2'b01 && next_instr[15:13] == 3'b000 ? next_instr[11:7]        : // c.addi
+	next_instr[1:0] == 2'b10                                ? next_instr[11:7]        :
+	                                                          {2'b01, next_instr[9:7]};
 
 assign next_regs_rs2 =
 	next_instr_is_32bit      ? next_instr[24:20] :
diff --git a/test/dhrystone/Makefile b/test/dhrystone/Makefile
index 39d8fb8..0ca9e71 100644
--- a/test/dhrystone/Makefile
+++ b/test/dhrystone/Makefile
@@ -1,6 +1,6 @@
 SRCS       := ../common/init.S src/dhrystone_main.c src/dhrystone.c src/util.c
 APP        := dhrystone
-CCFLAGS    := -O3 -fno-inline
+CCFLAGS    := -O3 -fno-inline -march=rv32i
 MAX_CYCLES := 1000000
 
 include ../common/src_only_app.mk
diff --git a/test/hellow/Makefile b/test/hellow/Makefile
index 19a8e98..412a6e7 100644
--- a/test/hellow/Makefile
+++ b/test/hellow/Makefile
@@ -1,4 +1,5 @@
 SRCS := ../common/init.S main.c
 APP  := hellow
+CCFLAGS = -march=rv32ic
 
 include ../common/src_only_app.mk
diff --git a/test/riscv-compliance/include/model_test.h b/test/riscv-compliance/include/model_test.h
index 027c5c0..e33134c 100644
--- a/test/riscv-compliance/include/model_test.h
+++ b/test/riscv-compliance/include/model_test.h
@@ -44,7 +44,7 @@
 #define LOCAL_IO_WRITE_STR(_STR) RVMODEL_IO_WRITE_STR(x31, _STR)
 
 // Shut up
-#define RVMODEL_IO_WRITE_STR(_STR)
+#define RVMODEL_IO_WRITE_STR(_STR, ...)
 
 // #define RVMODEL_IO_WRITE_STR(_SP, _STR)                                 \
 //     .section .data.string;                                              \
diff --git a/test/riscv-compliance/memmap.ld b/test/riscv-compliance/memmap.ld
index a35ad9c..deb98b3 100644
--- a/test/riscv-compliance/memmap.ld
+++ b/test/riscv-compliance/memmap.ld
@@ -11,6 +11,7 @@ ENTRY(_start)
 SECTIONS
 {
   .text : {
+    . = ORIGIN(RAM) + 0xc0;
     PROVIDE (_start = .);
     *(.text*)
     . = ALIGN(4);