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Add new bus signals on instruction_fetch_match/tb.v

This commit is contained in:
Luke Wren 2022-05-27 21:48:45 +01:00
parent b655148148
commit cd3125b6e5
1 changed files with 92 additions and 48 deletions
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48
test/formal/instruction_fetch_match/tb.v
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@ -30,12 +30,34 @@ always @ (posedge clk)
(* keep *) wire [2:0] d_hburst; (* keep *) wire [2:0] d_hburst;
(* keep *) wire [3:0] d_hprot; (* keep *) wire [3:0] d_hprot;
(* keep *) wire d_hmastlock; (* keep *) wire d_hmastlock;
(* keep *) wire d_hexcl;
(* keep *) wire d_hready; (* keep *) wire d_hready;
(* keep *) wire d_hresp; (* keep *) wire d_hresp;
(* keep *) wire d_hexokay;
(* keep *) wire [31:0] d_hwdata; (* keep *) wire [31:0] d_hwdata;
(* keep *) wire [31:0] d_hrdata; (* keep *) wire [31:0] d_hrdata;
(* keep *) reg [15:0] irq; localparam W_DATA = 32;
// Don't allow debug, as this breaks the CIR == mem[PC] invariant that we're trying to test.
(* keep *) wire dbg_req_halt = 1'b0;
(* keep *) wire dbg_req_halt_on_reset = 1'b0;
(* keep *) wire dbg_req_resume = 1'b0;
(* keep *) wire dbg_halted;
(* keep *) wire dbg_running;
(* keep *) wire [W_DATA-1:0] dbg_data0_rdata;
(* keep *) wire [W_DATA-1:0] dbg_data0_wdata;
(* keep *) wire dbg_data0_wen;
(* keep *) wire [W_DATA-1:0] dbg_instr_data;
(* keep *) wire dbg_instr_data_vld;
(* keep *) wire dbg_instr_data_rdy;
(* keep *) wire dbg_instr_caught_exception;
(* keep *) wire dbg_instr_caught_ebreak;
(* keep *) wire [31:0] irq;
(* keep *) wire soft_irq;
(* keep *) wire timer_irq;
hazard3_cpu_2port dut ( hazard3_cpu_2port dut (
.clk (clk), .clk (clk),
@ -60,12 +82,30 @@ hazard3_cpu_2port dut (
.d_hburst (d_hburst), .d_hburst (d_hburst),
.d_hprot (d_hprot), .d_hprot (d_hprot),
.d_hmastlock (d_hmastlock), .d_hmastlock (d_hmastlock),
.d_hexcl (d_hexcl),
.d_hready (d_hready), .d_hready (d_hready),
.d_hresp (d_hresp), .d_hresp (d_hresp),
.d_hexokay (d_hexokay),
.d_hwdata (d_hwdata), .d_hwdata (d_hwdata),
.d_hrdata (d_hrdata), .d_hrdata (d_hrdata),
.irq (irq) .dbg_req_halt (dbg_req_halt),
.dbg_req_halt_on_reset (dbg_req_halt_on_reset),
.dbg_req_resume (dbg_req_resume),
.dbg_halted (dbg_halted),
.dbg_running (dbg_running),
.dbg_data0_rdata (dbg_data0_rdata),
.dbg_data0_wdata (dbg_data0_wdata),
.dbg_data0_wen (dbg_data0_wen),
.dbg_instr_data (dbg_instr_data),
.dbg_instr_data_vld (dbg_instr_data_vld),
.dbg_instr_data_rdy (dbg_instr_data_rdy),
.dbg_instr_caught_exception (dbg_instr_caught_exception),
.dbg_instr_caught_ebreak (dbg_instr_caught_ebreak),
.irq (irq),
.soft_irq (soft_irq),
.timer_irq (timer_irq)
); );
// ---------------------------------------------------------------------------- // ----------------------------------------------------------------------------
@ -83,6 +123,7 @@ ahbl_slave_assumptions #(
.dst_hready_resp (i_hready), .dst_hready_resp (i_hready),
.dst_hready (i_hready), .dst_hready (i_hready),
.dst_hresp (i_hresp), .dst_hresp (i_hresp),
.dst_hexokay (1'b0),
.dst_haddr (i_haddr), .dst_haddr (i_haddr),
.dst_hwrite (i_hwrite), .dst_hwrite (i_hwrite),
.dst_htrans (i_htrans), .dst_htrans (i_htrans),
@ -90,6 +131,7 @@ ahbl_slave_assumptions #(
.dst_hburst (i_hburst), .dst_hburst (i_hburst),
.dst_hprot (i_hprot), .dst_hprot (i_hprot),
.dst_hmastlock (i_hmastlock), .dst_hmastlock (i_hmastlock),
.dst_hexcl (1'b0),
.dst_hwdata (i_hwdata), .dst_hwdata (i_hwdata),
.dst_hrdata (i_hrdata) .dst_hrdata (i_hrdata)
); );
@ -103,6 +145,7 @@ ahbl_slave_assumptions #(
.dst_hready_resp (d_hready), .dst_hready_resp (d_hready),
.dst_hready (d_hready), .dst_hready (d_hready),
.dst_hresp (d_hresp), .dst_hresp (d_hresp),
.dst_hexokay (d_hexokay),
.dst_haddr (d_haddr), .dst_haddr (d_haddr),
.dst_hwrite (d_hwrite), .dst_hwrite (d_hwrite),
.dst_htrans (d_htrans), .dst_htrans (d_htrans),
@ -110,6 +153,7 @@ ahbl_slave_assumptions #(
.dst_hburst (d_hburst), .dst_hburst (d_hburst),
.dst_hprot (d_hprot), .dst_hprot (d_hprot),
.dst_hmastlock (d_hmastlock), .dst_hmastlock (d_hmastlock),
.dst_hexcl (d_hexcl),
.dst_hwdata (d_hwdata), .dst_hwdata (d_hwdata),
.dst_hrdata (d_hrdata) .dst_hrdata (d_hrdata)
); );