From d1d70efa607e6aaa9f515287bbfeb8845b4604f6 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Wed, 5 Oct 2022 22:19:02 +0100 Subject: [PATCH] Fix some width issues introduced by last commit --- hdl/hazard3_csr.v | 10 +- hdl/synth.v | 36292 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 36297 insertions(+), 5 deletions(-) create mode 100644 hdl/synth.v diff --git a/hdl/hazard3_csr.v b/hdl/hazard3_csr.v index bd063f8..662f73d 100644 --- a/hdl/hazard3_csr.v +++ b/hdl/hazard3_csr.v @@ -331,7 +331,7 @@ localparam MAX_IRQS = 512; localparam [3:0] IRQ_PRIORITY_MASK = ~(4'hf >> IRQ_PRIORITY_BITS); // Assigned later: -wire [NUM_IRQS-1:0] meipa; +wire [MAX_IRQS-1:0] meipa; wire [8:0] meinext_irq; wire meinext_noirq; reg [3:0] eirq_highest_priority; @@ -342,9 +342,9 @@ reg [NUM_IRQS-1:0] meifa; reg [4*NUM_IRQS-1:0] meipra; // Padded vectors for CSR readout -wire [MAX_IRQS-1:0] meiea_rdata = {{MAX_IRQS{1'b0}}, meiea}; -wire [MAX_IRQS-1:0] meifa_rdata = {{MAX_IRQS{1'b0}}, meifa}; -wire [4*MAX_IRQS-1:0] meipra_rdata = {{4*MAX_IRQS{1'b0}}, meipra}; +wire [MAX_IRQS-1:0] meiea_rdata = {{MAX_IRQS-NUM_IRQS{1'b0}}, meiea}; +wire [MAX_IRQS-1:0] meifa_rdata = {{MAX_IRQS-NUM_IRQS{1'b0}}, meifa}; +wire [4*MAX_IRQS-1:0] meipra_rdata = {{4*(MAX_IRQS-NUM_IRQS){1'b0}}, meipra}; always @ (posedge clk or negedge rst_n) begin: update_irq_reg_arrays integer i; @@ -470,7 +470,7 @@ end // preemption level: this masking helps avoid re-taking IRQs in frames that you // have preempted. -assign meipa = {{MAX_IRQS-NUM_IRQS{1'b0}}, irq_r} | meifa; +assign meipa = {{MAX_IRQS-NUM_IRQS{1'b0}}, irq_r | meifa}; reg [NUM_IRQS-1:0] eirq_active_above_preempt; reg [NUM_IRQS-1:0] eirq_active_above_ppreempt; diff --git a/hdl/synth.v b/hdl/synth.v new file mode 100644 index 0000000..86abf8f --- /dev/null +++ b/hdl/synth.v @@ -0,0 +1,36292 @@ +/* Generated by Yosys 0.12+54 (git sha1 59a715034, clang 13.0.0-2 -fPIC -Os) */ + +(* dynports = 1 *) +(* top = 1 *) +(* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:12.1-292.10" *) +module hazard3_cpu_2port(clk, clk_always_on, rst_n, pwrup_req, pwrup_ack, clk_en, unblock_out, unblock_in, i_haddr, i_hwrite, i_htrans, i_hsize, i_hburst, i_hprot, i_hmastlock, i_hmaster, i_hready, i_hresp, i_hwdata, i_hrdata, d_haddr +, d_hwrite, d_htrans, d_hsize, d_hburst, d_hprot, d_hmastlock, d_hmaster, d_hexcl, d_hready, d_hresp, d_hexokay, d_hwdata, d_hrdata, dbg_req_halt, dbg_req_halt_on_reset, dbg_req_resume, dbg_halted, dbg_running, dbg_data0_rdata, dbg_data0_wdata, dbg_data0_wen +, dbg_instr_data, dbg_instr_data_vld, dbg_instr_data_rdy, dbg_instr_caught_exception, dbg_instr_caught_ebreak, dbg_sbus_addr, dbg_sbus_write, dbg_sbus_size, dbg_sbus_vld, dbg_sbus_rdy, dbg_sbus_err, dbg_sbus_wdata, dbg_sbus_rdata, irq, soft_irq, timer_irq); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:231.11-231.27" *) + wire bus_active_dph_d; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] bus_active_dph_d_SB_LUT4_I1_I3; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:232.11-232.27" *) + wire bus_active_dph_s; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:226.11-226.20" *) + wire bus_gnt_d; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] bus_gnt_d_SB_LUT4_O_I2; + (* onehot = 32'd1 *) + wire [2:0] bus_gnt_ds_prev; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:227.11-227.20" *) + wire bus_gnt_s; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] bus_gnt_s_SB_LUT4_O_I1; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:229.11-229.23" *) + wire bus_hold_aph; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:234.1-242.4" *) + wire bus_hold_aph_SB_DFFR_Q_D; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] bus_hold_aph_SB_LUT4_I2_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_1_I3; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I3; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:16.28-16.31" *) + input clk; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:17.28-17.41" *) + input clk_always_on; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:23.28-23.34" *) + output clk_en; + (* hdlname = "core alu aluop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:13.28-13.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + (* unused_bits = "0 1 2 3" *) + wire [5:0] \core.alu.aluop ; + (* hdlname = "core alu clmul_mul.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:111.10-111.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.clmul_mul.i ; + (* hdlname = "core alu cpop_count.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:101.10-101.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.cpop_count.i ; + (* hdlname = "core alu ctz_priority_encode encode_u encode.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:92.3-95.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_encode.v:20.16-20.17|/home/luke/proj/hazard3/hdl/arith/hazard3_priority_encode.v:32.3-35.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [5:0] \core.alu.ctz_priority_encode.encode_u.encode.i ; + (* hdlname = "core alu ctz_priority_encode priority_u select.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:92.3-95.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority.v:21.10-21.11|/home/luke/proj/hazard3/hdl/arith/hazard3_priority_encode.v:25.3-28.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.ctz_priority_encode.priority_u.select.i ; + (* hdlname = "core alu do_zip_unzip.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:126.10-126.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.do_zip_unzip.i ; + (* hdlname = "core alu funct3_32b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:15.28-15.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [2:0] \core.alu.funct3_32b ; + (* hdlname = "core alu funct7_32b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:14.28-14.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [6:0] \core.alu.funct7_32b ; + (* hdlname = "core alu op_a" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:16.28-16.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.op_a ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_10_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_11_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_12_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_13_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_14_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_15_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_16_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_17_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_18_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_19_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_20_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_21_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_22_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_23_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_24_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_25_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_26_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_27_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_28_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_29_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_2_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_31_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_a_SB_LUT4_O_3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_4_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_5_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_6_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_7_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_8_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_9_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_a_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:29.22-29.23" *) + wire [31:0] \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* hdlname = "core alu op_a_rev" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:76.18-76.26|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.op_a_rev ; + (* hdlname = "core alu op_a_shifted" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:33.19-33.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.op_a_shifted ; + (* hdlname = "core alu op_b_inv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:39.19-39.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.op_b_inv ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_10_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_11_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_12_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_13_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_14_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_15_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_16_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_17_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_19_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_20_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_21_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_22_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_I1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_23_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_24_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_25_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_26_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_2_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_3_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_4_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_5_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_6_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_7_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.op_b_inv_SB_LUT4_O_9_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.op_b_inv_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* hdlname = "core alu rev_op_a.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:78.10-78.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.rev_op_a.i ; + (* hdlname = "core alu shift_rotate" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:63.6-63.18|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire \core.alu.shift_rotate ; + (* hdlname = "core alu shifter din" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:67.3-74.2|/home/luke/proj/hazard3/hdl/arith/hazard3_shift_barrel.v:17.27-17.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.shifter.din ; + (* hdlname = "core alu shifter rotate" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:67.3-74.2|/home/luke/proj/hazard3/hdl/arith/hazard3_shift_barrel.v:20.27-20.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire \core.alu.shifter.rotate ; + (* hdlname = "core alu shifter shift.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:67.3-74.2|/home/luke/proj/hazard3/hdl/arith/hazard3_shift_barrel.v:30.10-30.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.shifter.shift.i ; + (* hdlname = "core alu sub" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:27.6-27.9|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire \core.alu.sub ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [31:0] \core.alu.sub_SB_CARRY_CI_CO ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 ; + (* hdlname = "core alu sum" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.19-41.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.sum ; + (* hdlname = "core alu unzip" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:124.18-124.23|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.unzip ; + (* hdlname = "core alu zip" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:123.18-123.21|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2" *) + wire [31:0] \core.alu.zip ; + (* hdlname = "core bus_aph_excl_d" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:43.29-43.43" *) + wire \core.bus_aph_excl_d ; + (* hdlname = "core bus_aph_panic_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:31.29-31.44" *) + wire \core.bus_aph_panic_i ; + (* hdlname = "core bus_aph_req_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:30.29-30.42" *) + wire \core.bus_aph_req_i ; + (* hdlname = "core bus_dph_err_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:34.29-34.42" *) + wire \core.bus_dph_err_i ; + (* hdlname = "core bus_haddr_d" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:49.29-49.40" *) + wire [31:0] \core.bus_haddr_d ; + (* hdlname = "core bus_haddr_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:36.29-36.40" *) + wire [31:0] \core.bus_haddr_i ; + (* hdlname = "core bus_hsize_d" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:50.29-50.40" *) + (* unused_bits = "0 1" *) + wire [2:0] \core.bus_hsize_d ; + (* hdlname = "core bus_hsize_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:37.29-37.40" *) + wire [2:0] \core.bus_hsize_i ; + (* hdlname = "core bus_priv_d" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:51.29-51.39" *) + wire \core.bus_priv_d ; + (* hdlname = "core bus_priv_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:38.29-38.39" *) + wire \core.bus_priv_i ; + (* hdlname = "core bus_rdata_d" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:54.29-54.40" *) + wire [31:0] \core.bus_rdata_d ; + (* hdlname = "core bus_rdata_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:39.29-39.40" *) + wire [31:0] \core.bus_rdata_i ; + (* hdlname = "core clk" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:14.29-14.32" *) + wire \core.clk ; + (* hdlname = "core clk_always_on" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:15.29-15.42" *) + wire \core.clk_always_on ; + (* hdlname = "core clk_en" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:21.29-21.35" *) + wire \core.clk_en ; + (* hdlname = "core csr_u addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:47.28-47.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [11:0] \core.csr_u.addr ; + (* hdlname = "core csr_u clk" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:21.28-21.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.clk ; + (* hdlname = "core csr_u clk_always_on" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:22.28-22.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.clk_always_on ; + (* hdlname = "core csr_u dbg_data0_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:35.28-35.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [31:0] \core.csr_u.dbg_data0_rdata ; + (* hdlname = "core csr_u dbg_data0_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:36.28-36.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.dbg_data0_wdata ; + (* hdlname = "core csr_u dbg_data0_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:37.28-37.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dbg_data0_wen ; + (* hdlname = "core csr_u dbg_instr_caught_ebreak" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:33.28-33.51|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dbg_instr_caught_ebreak ; + (* hdlname = "core csr_u dbg_instr_caught_exception" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:32.28-32.54|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dbg_instr_caught_exception ; + (* hdlname = "core csr_u dbg_req_halt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:28.28-28.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire \core.csr_u.dbg_req_halt ; + (* hdlname = "core csr_u dbg_req_halt_on_reset" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:29.28-29.49|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire \core.csr_u.dbg_req_halt_on_reset ; + (* hdlname = "core csr_u dbg_req_halt_prev" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1304.5-1304.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dbg_req_halt_prev ; + (* hdlname = "core csr_u dbg_req_resume" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:30.28-30.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire \core.csr_u.dbg_req_resume ; + (* hdlname = "core csr_u dbg_req_resume_prev" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1303.5-1303.24|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dbg_req_resume_prev ; + (* hdlname = "core csr_u dcsr_ebreakm" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:632.5-632.17|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dcsr_ebreakm ; + (* hdlname = "core csr_u dcsr_ebreaku" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:633.5-633.17|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dcsr_ebreaku ; + (* hdlname = "core csr_u dcsr_step" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:634.5-634.14|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.dcsr_step ; + (* hdlname = "core csr_u debug_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:26.28-26.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.debug_mode ; + (* hdlname = "core csr_u debug_suppresses_trap_update" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:166.6-166.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.debug_suppresses_trap_update ; + (* hdlname = "core csr_u dpc" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:663.16-663.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.dpc ; + (* hdlname = "core csr_u eirq_compare.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:477.10-477.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_compare.i ; + (* hdlname = "core csr_u eirq_encode_u encode.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:525.3-528.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_encode.v:20.16-20.17|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [9:0] \core.csr_u.eirq_encode_u.encode.i ; + (* hdlname = "core csr_u eirq_encode_u gnt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:525.3-528.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_encode.v:16.26-16.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3 4" *) + wire [8:0] \core.csr_u.eirq_encode_u.gnt ; + (* hdlname = "core csr_u eirq_highest_priority" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:337.23-337.44|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [3:0] \core.csr_u.eirq_highest_priority ; + (* hdlname = "core csr_u eirq_priority_u active_layer_sel" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:42.25-42.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire [15:0] \core.csr_u.eirq_priority_u.active_layer_sel ; + (* hdlname = "core csr_u eirq_priority_u level_has_req" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:29.24-29.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire [15:0] \core.csr_u.eirq_priority_u.level_has_req ; + (* hdlname = "core csr_u eirq_priority_u mux_reqs_by_layer.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:56.10-56.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.mux_reqs_by_layer.i ; + (* hdlname = "core csr_u eirq_priority_u pri" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:22.37-22.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [127:0] \core.csr_u.eirq_priority_u.pri ; + (* hdlname = "core csr_u eirq_priority_u prisel_layer gnt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority.v:17.26-17.29|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:47.3-50.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire [15:0] \core.csr_u.eirq_priority_u.prisel_layer.gnt ; + (* hdlname = "core csr_u eirq_priority_u prisel_layer req" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority.v:16.26-16.29|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:47.3-50.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0" *) + wire [15:0] \core.csr_u.eirq_priority_u.prisel_layer.req ; + (* hdlname = "core csr_u eirq_priority_u prisel_layer select.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority.v:21.10-21.11|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:47.3-50.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.prisel_layer.select.i ; + (* hdlname = "core csr_u eirq_priority_u prisel_tiebreak select.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority.v:21.10-21.11|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:67.3-70.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.prisel_tiebreak.select.i ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[10]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[10] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[11]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[11] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[12]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[12] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[13]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[13] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[14]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[14] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[15]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[15] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[1]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[1] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[2]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[2] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[3]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[3] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[4]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[4] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[5]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[5] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[6]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[6] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[7]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[7] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[8]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[8] ; + (* hdlname = "core csr_u eirq_priority_u req_stratified[9]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:28.24-28.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.req_stratified[9] ; + (* hdlname = "core csr_u eirq_priority_u stratify.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:32.10-32.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.stratify.i ; + (* hdlname = "core csr_u eirq_priority_u stratify.j" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:506.3-510.2|/home/luke/proj/hazard3/hdl/arith/hazard3_onehot_priority_dynamic.v:32.13-32.14|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.eirq_priority_u.stratify.j ; + (* hdlname = "core csr_u enter_debug_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:147.6-147.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.enter_debug_mode ; + (* hdlname = "core csr_u except" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:97.29-97.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [3:0] \core.csr_u.except ; + (* hdlname = "core csr_u get_highest_eirq_priority.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:513.10-513.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.get_highest_eirq_priority.i ; + (* hdlname = "core csr_u have_just_reset" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1301.5-1301.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.have_just_reset ; + (* hdlname = "core csr_u irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:102.29-102.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.irq ; + (* hdlname = "core csr_u irq_r" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:456.20-456.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.irq_r ; + (* hdlname = "core csr_u irq_software" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:103.29-103.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.irq_software ; + (* hdlname = "core csr_u irq_software_r" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1413.5-1413.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.irq_software_r ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.irq_software_r_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.irq_software_r_SB_LUT4_I3_O ; + (* hdlname = "core csr_u irq_timer" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:104.29-104.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.irq_timer ; + (* hdlname = "core csr_u irq_timer_r" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1414.5-1414.16|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.irq_timer_r ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.irq_timer_r_SB_LUT4_I3_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.irq_timer_r_SB_LUT4_I3_O ; + (* hdlname = "core csr_u irq_vector_enable" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:249.17-249.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.irq_vector_enable ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.irq_vector_enable_SB_LUT4_I3_O ; + (* hdlname = "core csr_u m_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:159.6-159.12|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.m_mode ; + (* hdlname = "core csr_u m_mode_execution" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:92.29-92.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.m_mode_execution ; + (* hdlname = "core csr_u m_mode_loadstore" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:94.29-94.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.m_mode_loadstore ; + (* hdlname = "core csr_u m_mode_trap_entry" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:93.29-93.46|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.m_mode_trap_entry ; + (* hdlname = "core csr_u match_mrw" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:708.6-708.15|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.match_mrw ; + (* hdlname = "core csr_u match_urw" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:710.6-710.15|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.match_urw ; + (* hdlname = "core csr_u mcause_code" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:309.12-309.23|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [3:0] \core.csr_u.mcause_code ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mcause_code_SB_DFFER_Q_1_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mcause_code_SB_DFFER_Q_1_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mcause_code_SB_DFFER_Q_2_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mcause_code_SB_DFFER_Q_3_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mcause_code_SB_DFFER_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_code_SB_DFFER_Q_D_SB_LUT4_O_I0 ; + (* hdlname = "core csr_u mcause_irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:308.12-308.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mcause_irq ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mcause_irq_SB_DFFER_Q_D ; + wire \core.csr_u.mcause_irq_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_irq_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 ; + (* hdlname = "core csr_u mcause_irq_num" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1460.12-1460.26|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3" *) + wire [3:0] \core.csr_u.mcause_irq_num ; + (* hdlname = "core csr_u meicontext_irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:394.11-394.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [8:0] \core.csr_u.meicontext_irq ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_1_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_2_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_3_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_5_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_6_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_7_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_8_D ; + wire \core.csr_u.meicontext_irq_SB_DFFER_Q_D ; + (* hdlname = "core csr_u meicontext_mreteirq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:395.11-395.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meicontext_mreteirq ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meicontext_mreteirq_SB_DFFER_Q_D ; + wire \core.csr_u.meicontext_mreteirq_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_mreteirq_SB_LUT4_I3_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_mreteirq_SB_LUT4_I3_O ; + (* hdlname = "core csr_u meicontext_noirq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:393.11-393.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meicontext_noirq ; + wire \core.csr_u.meicontext_noirq_SB_DFFES_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_noirq_SB_LUT4_I1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_noirq_SB_LUT4_I1_O ; + (* hdlname = "core csr_u meicontext_pppreempt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:390.11-390.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [3:0] \core.csr_u.meicontext_pppreempt ; + (* hdlname = "core csr_u meicontext_ppreempt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:391.11-391.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [3:0] \core.csr_u.meicontext_ppreempt ; + (* hdlname = "core csr_u meicontext_preempt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:392.11-392.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [4:0] \core.csr_u.meicontext_preempt ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meicontext_preempt_SB_DFFER_Q_D ; + wire \core.csr_u.meicontext_preempt_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 ; + (* hdlname = "core csr_u meiea" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:339.23-339.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [511:0] \core.csr_u.meiea ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_10_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_11_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_12_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_13_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_14_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_16_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_17_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_18_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_19_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_20_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_21_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_22_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_23_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_24_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_25_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_26_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_27_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_28_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_29_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_2_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_30_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_31_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_3_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_4_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_5_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_6_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_7_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_8_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_9_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meiea_SB_DFFER_Q_D ; + (* hdlname = "core csr_u meifa" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:340.23-340.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [511:0] \core.csr_u.meifa ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_10_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_11_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_12_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_13_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_14_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_16_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_17_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_18_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_19_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_1_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_20_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_21_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_22_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_23_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_24_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_25_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_26_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_27_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_28_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_29_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_2_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_30_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_31_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_3_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_4_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_4_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_5_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_6_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_6_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_7_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_8_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_8_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_9_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.meifa_SB_DFFR_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.meifa_SB_DFFR_Q_D_SB_LUT4_O_I3 ; + (* hdlname = "core csr_u meinext_irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:335.23-335.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3 4" *) + wire [8:0] \core.csr_u.meinext_irq ; + (* hdlname = "core csr_u meinext_irq_unmasked" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:499.21-499.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3 4" *) + wire [8:0] \core.csr_u.meinext_irq_unmasked ; + (* hdlname = "core csr_u meipa" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:334.23-334.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [511:0] \core.csr_u.meipa ; + (* hdlname = "core csr_u meipra" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:341.23-341.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [2047:0] \core.csr_u.meipra ; + (* hdlname = "core csr_u mepc" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:261.16-261.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.mepc ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_10_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_11_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_12_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_13_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_14_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_16_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_17_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_18_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_19_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_20_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_21_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_22_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_23_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_24_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_25_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_26_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_27_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_28_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_29_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_2_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_3_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_4_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_5_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_6_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_7_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_8_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_9_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mepc_SB_DFFER_Q_D ; + (* hdlname = "core csr_u mepc_in" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:83.29-83.36|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "1 31" *) + wire [31:0] \core.csr_u.mepc_in ; + (* hdlname = "core csr_u mie" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:278.16-278.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.mie ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:283.1-297.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mie_SB_DFFER_Q_1_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:283.1-297.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mie_SB_DFFER_Q_2_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 ; + wire \core.csr_u.mie_SB_DFFER_Q_2_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mie_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 ; + wire \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:353.7-353.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:255.7-255.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:241.7-241.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* hdlname = "core csr_u mip" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:301.17-301.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "11" *) + wire [31:0] \core.csr_u.mip ; + (* hdlname = "core csr_u mscratch" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:235.16-235.24|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.mscratch ; + (* hdlname = "core csr_u msleep_deepsleep" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:537.5-537.21|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.msleep_deepsleep ; + (* hdlname = "core csr_u msleep_powerdown" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:536.5-536.21|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.msleep_powerdown ; + (* hdlname = "core csr_u msleep_sleeponblock" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:535.5-535.24|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.msleep_sleeponblock ; + (* hdlname = "core csr_u mstatus_mie" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:173.5-173.16|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_mie ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:186.1-227.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_mie_SB_DFFER_Q_D ; + wire \core.csr_u.mstatus_mie_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.mstatus_mie_SB_LUT4_I3_O ; + (* hdlname = "core csr_u mstatus_mpie" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:172.5-172.17|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_mpie ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:186.1-227.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_mpie_SB_DFFER_Q_D ; + (* hdlname = "core csr_u mstatus_mpp" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:174.5-174.16|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_mpp ; + (* hdlname = "core csr_u mstatus_mprv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:175.5-175.17|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_mprv ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.mstatus_mprv_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mprv_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 ; + (* hdlname = "core csr_u mstatus_tw" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:176.5-176.15|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.mstatus_tw ; + (* hdlname = "core csr_u mtvec" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:248.17-248.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.mtvec ; + (* hdlname = "core csr_u mtvec_reg" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:247.17-247.26|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.mtvec_reg ; + (* hdlname = "core csr_u pending_dbg_resume" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1307.6-1307.24|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.pending_dbg_resume ; + (* hdlname = "core csr_u pending_dbg_resume_prev" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1305.5-1305.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.pending_dbg_resume_prev ; + (* hdlname = "core csr_u pmp_cfg_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:107.29-107.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [11:0] \core.csr_u.pmp_cfg_addr ; + (* hdlname = "core csr_u pmp_cfg_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:110.29-110.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.pmp_cfg_rdata ; + (* hdlname = "core csr_u pmp_cfg_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:109.29-109.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.pmp_cfg_wdata ; + (* hdlname = "core csr_u pmp_cfg_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:108.29-108.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.pmp_cfg_wen ; + (* hdlname = "core csr_u preempt_level_next" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:397.12-397.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [4:0] \core.csr_u.preempt_level_next ; + (* hdlname = "core csr_u pwr_allow_power_down" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:87.29-87.49|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.pwr_allow_power_down ; + (* hdlname = "core csr_u pwr_allow_sleep" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:86.29-86.44|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.pwr_allow_sleep ; + (* hdlname = "core csr_u pwr_allow_sleep_on_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:88.29-88.53|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.pwr_allow_sleep_on_block ; + (* hdlname = "core csr_u rst_n" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:23.28-23.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.rst_n ; + (* hdlname = "core csr_u standard_irq_num" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1449.12-1449.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3" *) + wire [3:0] \core.csr_u.standard_irq_num ; + (* hdlname = "core csr_u step_halt_req" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1302.5-1302.18|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.step_halt_req ; + (* hdlname = "core csr_u trap_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:69.29-69.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [31:0] \core.csr_u.trap_addr ; + (* hdlname = "core csr_u trap_is_debug_entry" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:71.29-71.48|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.trap_is_debug_entry ; + (* hdlname = "core csr_u trap_wfi" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:120.29-120.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.trap_wfi ; + (* hdlname = "core csr_u trig_cfg_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:113.29-113.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [11:0] \core.csr_u.trig_cfg_addr ; + (* hdlname = "core csr_u trig_cfg_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:116.29-116.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.trig_cfg_rdata ; + (* hdlname = "core csr_u trig_cfg_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:115.29-115.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.trig_cfg_wdata ; + (* hdlname = "core csr_u trig_cfg_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:114.29-114.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.trig_cfg_wen ; + (* hdlname = "core csr_u vector_sel" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1462.12-1462.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + (* unused_bits = "0 1 2 3" *) + wire [3:0] \core.csr_u.vector_sel ; + (* hdlname = "core csr_u want_halt_except" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1367.6-1367.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.want_halt_except ; + (* hdlname = "core csr_u want_halt_irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1389.6-1389.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.want_halt_irq ; + (* hdlname = "core csr_u want_halt_irq_if_no_exception" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1379.6-1379.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire \core.csr_u.want_halt_irq_if_no_exception ; + (* hdlname = "core csr_u wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:48.28-48.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.wdata ; + (* hdlname = "core csr_u wdata_update" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:135.17-135.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2" *) + wire [31:0] \core.csr_u.wdata_update ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_10_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_16_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_17_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_17_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_18_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_18_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_19_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_1_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_20_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_21_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_22_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_24_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_28_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_28_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_30_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_31_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_31_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 ; + (* hdlname = "core d_addr_offs" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:210.22-210.33" *) + wire [31:0] \core.d_addr_offs ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [31:0] \core.d_addr_offs_SB_CARRY_I1_CO ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_addr_offs_SB_LUT4_O_13_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_addr_offs_SB_LUT4_O_8_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_addr_offs_SB_LUT4_O_8_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_addr_offs_SB_LUT4_O_9_I3 ; + (* hdlname = "core d_aluop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:206.22-206.29" *) + (* unused_bits = "0 1 2 3" *) + wire [5:0] \core.d_aluop ; + (* hdlname = "core d_btb_target_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:122.22-122.39" *) + wire [31:0] \core.d_btb_target_addr ; + (* hdlname = "core d_fence_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:217.22-217.31" *) + wire \core.d_fence_i ; + (* hdlname = "core d_funct3_32b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:202.22-202.34" *) + wire [2:0] \core.d_funct3_32b ; + (* hdlname = "core d_funct7_32b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:203.22-203.34" *) + wire [6:0] \core.d_funct7_32b ; + (* hdlname = "core d_memop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:207.22-207.29" *) + (* unused_bits = "0 1 2 4" *) + wire [4:0] \core.d_memop ; + (* hdlname = "core d_memop_is_amo" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:333.6-333.20" *) + wire \core.d_memop_is_amo ; + (* hdlname = "core d_mulop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:208.22-208.29" *) + wire [2:0] \core.d_mulop ; + (* hdlname = "core d_pc" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:212.22-212.26" *) + wire [31:0] \core.d_pc ; + (* hdlname = "core d_rs1_predecoded" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:414.21-414.37" *) + wire [4:0] \core.d_rs1_predecoded ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs1_predecoded_SB_LUT4_I1_3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs1_predecoded_SB_LUT4_I1_4_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs1_predecoded_SB_LUT4_I1_6_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_rs1_predecoded_SB_LUT4_I1_7_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs1_predecoded_SB_LUT4_I1_7_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_rs1_predecoded_SB_LUT4_I1_O ; + (* hdlname = "core d_rs2" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:200.22-200.27" *) + wire [4:0] \core.d_rs2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_SB_LUT4_O_2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_SB_LUT4_O_3_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_rs2_SB_LUT4_O_4_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_SB_LUT4_O_4_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_rs2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* hdlname = "core d_rs2_predecoded" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:415.21-415.37" *) + wire [4:0] \core.d_rs2_predecoded ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.d_rs2_predecoded_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_rs2_predecoded_SB_LUT4_I1_2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_predecoded_SB_LUT4_I1_4_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.d_rs2_predecoded_SB_LUT4_I1_5_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.d_rs2_predecoded_SB_LUT4_I1_O ; + (* hdlname = "core d_sleep_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:215.22-215.35" *) + wire \core.d_sleep_block ; + (* hdlname = "core d_sleep_unblock" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:216.22-216.37" *) + wire \core.d_sleep_unblock ; + (* hdlname = "core dbg_data0_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:63.29-63.44" *) + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [31:0] \core.dbg_data0_rdata ; + (* hdlname = "core dbg_data0_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:64.29-64.44" *) + wire [31:0] \core.dbg_data0_wdata ; + (* hdlname = "core dbg_data0_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:65.29-65.42" *) + wire \core.dbg_data0_wen ; + (* hdlname = "core dbg_halted" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:60.29-60.39" *) + wire \core.dbg_halted ; + (* hdlname = "core dbg_instr_caught_ebreak" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:71.29-71.52" *) + wire \core.dbg_instr_caught_ebreak ; + (* hdlname = "core dbg_instr_caught_exception" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:70.29-70.55" *) + wire \core.dbg_instr_caught_exception ; + (* hdlname = "core dbg_instr_data" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:67.29-67.43" *) + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [31:0] \core.dbg_instr_data ; + (* hdlname = "core dbg_instr_data_rdy" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:69.29-69.47" *) + wire \core.dbg_instr_data_rdy ; + (* hdlname = "core dbg_instr_data_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:68.29-68.47" *) + (* unused_bits = "0" *) + wire \core.dbg_instr_data_vld ; + (* hdlname = "core dbg_req_halt" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:57.29-57.41" *) + (* unused_bits = "0" *) + wire \core.dbg_req_halt ; + (* hdlname = "core dbg_req_halt_on_reset" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:58.29-58.50" *) + (* unused_bits = "0" *) + wire \core.dbg_req_halt_on_reset ; + (* hdlname = "core dbg_req_resume" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:59.29-59.43" *) + (* unused_bits = "0" *) + wire \core.dbg_req_resume ; + (* hdlname = "core dbg_running" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:61.29-61.40" *) + wire \core.dbg_running ; + (* hdlname = "core debug_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:88.6-88.16" *) + wire \core.debug_mode ; + (* hdlname = "core decode_u branch_offs" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:160.19-160.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.branch_offs ; + (* hdlname = "core decode_u cir_lock" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:120.6-120.14|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.cir_lock ; + (* hdlname = "core decode_u cir_lock_prev" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:118.5-118.18|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.cir_lock_prev ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 ; + wire \core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.cir_lock_prev_SB_LUT4_I2_O ; + (* hdlname = "core decode_u clk" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:13.30-13.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.clk ; + (* hdlname = "core decode_u d_addr_offs" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:51.30-51.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_addr_offs ; + (* hdlname = "core decode_u d_aluop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:43.30-43.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + (* unused_bits = "0 1 2 3" *) + wire [5:0] \core.decode_u.d_aluop ; + (* hdlname = "core decode_u d_btb_target_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:33.30-33.47|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_btb_target_addr ; + (* hdlname = "core decode_u d_fence_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:57.30-57.39|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.d_fence_i ; + (* hdlname = "core decode_u d_funct3_32b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:39.30-39.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [2:0] \core.decode_u.d_funct3_32b ; + (* hdlname = "core decode_u d_funct7_32b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:40.30-40.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [6:0] \core.decode_u.d_funct7_32b ; + (* hdlname = "core decode_u d_imm_b" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:86.13-86.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_imm_b ; + (* hdlname = "core decode_u d_imm_i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:84.13-84.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_imm_i ; + (* hdlname = "core decode_u d_imm_j" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:88.13-88.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_imm_j ; + (* hdlname = "core decode_u d_imm_s" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:85.13-85.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_imm_s ; + (* hdlname = "core decode_u d_imm_u" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:87.13-87.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_imm_u ; + (* hdlname = "core decode_u d_instr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:68.13-68.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_instr ; + (* hdlname = "core decode_u d_instr_is_32bit" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:69.13-69.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.d_instr_is_32bit ; + (* hdlname = "core decode_u d_invalid_16bit" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:70.13-70.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.d_invalid_16bit ; + (* hdlname = "core decode_u d_memop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:44.30-44.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + (* unused_bits = "0 1 2 4" *) + wire [4:0] \core.decode_u.d_memop ; + (* hdlname = "core decode_u d_mulop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:45.30-45.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [2:0] \core.decode_u.d_mulop ; + (* hdlname = "core decode_u d_pc" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:22.30-22.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.d_pc ; + (* hdlname = "core decode_u d_rs2" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:37.30-37.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.d_rs2 ; + (* hdlname = "core decode_u d_sleep_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:55.30-55.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.d_sleep_block ; + (* hdlname = "core decode_u d_sleep_unblock" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:56.30-56.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.d_sleep_unblock ; + (* hdlname = "core decode_u debug_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:24.30-24.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.debug_mode ; + (* hdlname = "core decode_u decomp imm_cb" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:52.13-52.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.decomp.imm_cb ; + (* hdlname = "core decode_u decomp imm_ci" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:33.13-33.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.decomp.imm_ci ; + (* hdlname = "core decode_u decomp imm_cj" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:39.13-39.19|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.decomp.imm_cj ; + (* hdlname = "core decode_u decomp instr_in" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:11.20-11.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.decomp.instr_in ; + (* hdlname = "core decode_u decomp instr_is_32bit" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:12.13-12.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.decomp.instr_is_32bit ; + (* hdlname = "core decode_u decomp instr_out" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:13.20-13.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.decomp.instr_out ; + (* hdlname = "core decode_u decomp invalid" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:14.13-14.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.decomp.invalid ; + (* hdlname = "core decode_u decomp rd_l" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:23.22-23.26|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.decomp.rd_l ; + (* hdlname = "core decode_u decomp rd_s" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:26.22-26.26|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.decomp.rd_s ; + (* hdlname = "core decode_u decomp rs1_l" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:24.22-24.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.decomp.rs1_l ; + (* hdlname = "core decode_u decomp rs1_s" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:27.22-27.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.decomp.rs1_s ; + (* hdlname = "core decode_u decomp rs2_l" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:25.22-25.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.decomp.rs2_l ; + (* hdlname = "core decode_u decomp rs2_s" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:76.3-81.2|/home/luke/proj/hazard3/hdl/hazard3_instr_decompress.v:28.22-28.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [4:0] \core.decode_u.decomp.rs2_s ; + (* hdlname = "core decode_u df_cir_use" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:20.30-20.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [1:0] \core.decode_u.df_cir_use ; + (* hdlname = "core decode_u f_jump_target" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:31.30-31.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.f_jump_target ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_10_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_11_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_12_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_13_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_14_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_15_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_16_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_17_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_18_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_19_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_20_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_21_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_22_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_23_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_24_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_25_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_26_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.decode_u.f_jump_target_SB_LUT4_O_27_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_28_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.decode_u.f_jump_target_SB_LUT4_O_28_I2_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_29_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_2_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_4_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_5_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_6_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_7_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_8_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.decode_u.f_jump_target_SB_LUT4_O_9_I2 ; + (* hdlname = "core decode_u fd_cir" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:16.30-16.36|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.fd_cir ; + (* hdlname = "core decode_u fd_cir_err" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:17.30-17.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [1:0] \core.decode_u.fd_cir_err ; + (* hdlname = "core decode_u fd_cir_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:19.30-19.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [1:0] \core.decode_u.fd_cir_vld ; + (* hdlname = "core decode_u m_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:25.30-25.36|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.m_mode ; + (* hdlname = "core decode_u partial_predicted_branch" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:140.6-140.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.partial_predicted_branch ; + (* hdlname = "core decode_u pc" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:131.19-131.21|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire [31:0] \core.decode_u.pc ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_10_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_11_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_12_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_13_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_14_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_16_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_17_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_18_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_19_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_20_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_21_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_22_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_23_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_24_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_25_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_26_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_27_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_28_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_29_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_2_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_30_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_3_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_4_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_5_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_6_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_7_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_8_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.pc_SB_DFFER_Q_9_D ; + (* hdlname = "core decode_u pc_seq_next" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.19-132.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + (* unused_bits = "2 31" *) + wire [31:0] \core.decode_u.pc_seq_next ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [29:0] \core.decode_u.pc_seq_next_SB_LUT4_O_I3 ; + (* hdlname = "core decode_u predicted_branch" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:143.6-143.22|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.predicted_branch ; + (* hdlname = "core decode_u rst_n" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:14.30-14.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.rst_n ; + (* hdlname = "core decode_u trap_wfi" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:26.30-26.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2" *) + wire \core.decode_u.trap_wfi ; + (* hdlname = "core df_cir_use" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:113.22-113.32" *) + wire [1:0] \core.df_cir_use ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.df_cir_use_SB_LUT4_I2_O ; + (* hdlname = "core f_jump_priv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:97.22-97.33" *) + wire \core.f_jump_priv ; + (* hdlname = "core f_jump_target" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:96.22-96.35" *) + wire [31:0] \core.f_jump_target ; + (* hdlname = "core f_mem_size" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:126.6-126.16" *) + wire \core.f_mem_size ; + (* hdlname = "core f_rs1_coarse" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:104.22-104.34" *) + wire [4:0] \core.f_rs1_coarse ; + (* hdlname = "core f_rs1_fine" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:106.22-106.32" *) + wire [4:0] \core.f_rs1_fine ; + (* hdlname = "core f_rs2_coarse" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:105.22-105.34" *) + wire [4:0] \core.f_rs2_coarse ; + (* hdlname = "core f_rs2_fine" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:107.22-107.32" *) + wire [4:0] \core.f_rs2_fine ; + (* hdlname = "core fd_cir" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:109.22-109.28" *) + wire [31:0] \core.fd_cir ; + (* hdlname = "core fd_cir_err" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:110.22-110.32" *) + wire [1:0] \core.fd_cir_err ; + (* hdlname = "core fd_cir_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:112.22-112.32" *) + wire [1:0] \core.fd_cir_vld ; + (* hdlname = "core frontend boundary_conditions.i" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:128.10-128.11|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.boundary_conditions.i ; + (* hdlname = "core frontend btb_match_current_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:252.6-252.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.btb_match_current_addr ; + (* hdlname = "core frontend btb_match_next_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:253.6-253.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.btb_match_next_addr ; + (* hdlname = "core frontend btb_match_word" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:241.6-241.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.btb_match_word ; + (* hdlname = "core frontend btb_set" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:42.27-42.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.btb_set ; + (* hdlname = "core frontend btb_set_src_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:43.27-43.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.btb_set_src_addr ; + (* hdlname = "core frontend btb_set_target_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:45.27-45.46|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.btb_set_target_addr ; + (* hdlname = "core frontend btb_src_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:187.18-187.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.btb_src_addr ; + (* hdlname = "core frontend btb_src_overhanging" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:246.6-246.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.btb_src_overhanging ; + (* hdlname = "core frontend btb_target_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:189.18-189.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.btb_target_addr ; + (* hdlname = "core frontend btb_target_addr_out" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:47.27-47.46|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.btb_target_addr_out ; + (* hdlname = "core frontend btb_valid" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:190.18-190.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.btb_valid ; + (* hdlname = "core frontend buf_level" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:419.11-419.20|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.buf_level ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.buf_level_SB_LUT4_I3_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:150.8-150.49|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.buf_level_SB_LUT4_I3_O ; + (* hdlname = "core frontend buf_level_next" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:495.12-495.26|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.buf_level_next ; + (* hdlname = "core frontend cir" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:53.27-53.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.cir ; + (* hdlname = "core frontend cir_bus_err" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:459.12-459.23|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [2:0] \core.frontend.cir_bus_err ; + (* hdlname = "core frontend cir_bus_err_plus_fetch" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:464.12-464.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [2:0] \core.frontend.cir_bus_err_plus_fetch ; + (* hdlname = "core frontend cir_bus_err_shifted" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:460.12-460.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + (* unused_bits = "0" *) + wire [2:0] \core.frontend.cir_bus_err_shifted ; + (* hdlname = "core frontend cir_err" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:57.27-57.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.cir_err ; + (* hdlname = "core frontend cir_use" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:55.27-55.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.cir_use ; + (* hdlname = "core frontend cir_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:54.27-54.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.cir_vld ; + wire \core.frontend.cir_vld_SB_DFFR_Q_1_D ; + (* hdlname = "core frontend clk" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:11.27-11.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.clk ; + (* hdlname = "core frontend ctr_flush_pending" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:333.12-333.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.ctr_flush_pending ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.ctr_flush_pending_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.ctr_flush_pending_SB_DFFER_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.ctr_flush_pending_SB_DFFER_Q_D_SB_LUT4_O_I0 ; + wire \core.frontend.ctr_flush_pending_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.ctr_flush_pending_SB_LUT4_I1_O ; + (* hdlname = "core frontend dbg_instr_data" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:86.27-86.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [31:0] \core.frontend.dbg_instr_data ; + (* hdlname = "core frontend dbg_instr_data_rdy" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:88.27-88.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.dbg_instr_data_rdy ; + (* hdlname = "core frontend dbg_instr_data_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:87.27-87.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + (* unused_bits = "0" *) + wire \core.frontend.dbg_instr_data_vld ; + (* hdlname = "core frontend debug_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:85.27-85.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.debug_mode ; + (* hdlname = "core frontend fetch_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:235.18-235.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.fetch_addr ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_10_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_11_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_12_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_13_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_14_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_16_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_17_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_18_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_19_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_20_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_21_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_22_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_23_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_24_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_25_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_26_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_27_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_28_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_29_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_2_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_3_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_4_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_5_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_6_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_7_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_8_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_9_D ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" *) + (* unused_bits = "0 29" *) + wire [29:0] \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_addr_SB_DFFER_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [29:0] \core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 ; + (* hdlname = "core frontend fetch_data_hwvld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:423.12-423.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + (* unused_bits = "1" *) + wire [1:0] \core.frontend.fetch_data_hwvld ; + (* hdlname = "core frontend fetch_priv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:236.18-236.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fetch_priv ; + (* hdlname = "core frontend fifo_almost_full" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:121.19-121.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_almost_full ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_almost_full_SB_DFFR_Q_D ; + (* hdlname = "core frontend fifo_dbg_inject" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:125.19-125.34|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_dbg_inject ; + (* hdlname = "core frontend fifo_err[0]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:113.22-113.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_err[0] ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_err[0]_SB_DFFER_Q_D ; + (* hdlname = "core frontend fifo_err[1]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:113.22-113.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_err[1] ; + (* hdlname = "core frontend fifo_err[2]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:113.22-113.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_err[2] ; + (* hdlname = "core frontend fifo_full" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:119.19-119.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_full ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_full_SB_DFFR_Q_D ; + (* hdlname = "core frontend fifo_mem[0]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:112.22-112.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.fifo_mem[0] ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_10_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_11_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_12_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_13_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_14_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_16_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_17_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_18_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_19_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_20_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_21_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_22_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_23_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_24_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_25_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_26_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_27_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_28_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_29_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_2_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_30_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_31_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_3_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_4_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_5_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_6_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_7_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_8_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_9_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_D ; + wire \core.frontend.fifo_mem[0]_SB_DFFER_Q_E ; + (* hdlname = "core frontend fifo_mem[1]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:112.22-112.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.fifo_mem[1] ; + (* hdlname = "core frontend fifo_mem[2]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:112.22-112.30|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.fifo_mem[2] ; + (* hdlname = "core frontend fifo_predbranch[2]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:114.22-114.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.fifo_predbranch[2] ; + (* hdlname = "core frontend fifo_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:118.19-118.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.fifo_rdata ; + (* hdlname = "core frontend fifo_valid[0]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:116.22-116.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_valid[0] ; + (* hdlname = "core frontend fifo_valid[1]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:116.22-116.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_valid[1] ; + (* hdlname = "core frontend fifo_valid[2]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:116.22-116.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_valid[2] ; + (* hdlname = "core frontend fifo_valid_hw[0]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:115.22-115.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.fifo_valid_hw[0] ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E ; + (* hdlname = "core frontend fifo_valid_hw[1]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:115.22-115.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.fifo_valid_hw[1] ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_D ; + wire \core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I3 ; + (* hdlname = "core frontend fifo_valid_hw[2]" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:115.22-115.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.fifo_valid_hw[2] ; + (* hdlname = "core frontend hwbuf" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:420.20-420.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [15:0] \core.frontend.hwbuf ; + (* hdlname = "core frontend instr_data_plus_fetch" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:447.23-447.44|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [47:0] \core.frontend.instr_data_plus_fetch ; + (* hdlname = "core frontend instr_data_shifted" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:435.23-435.41|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + (* unused_bits = "15" *) + wire [47:0] \core.frontend.instr_data_shifted ; + (* hdlname = "core frontend jump_priv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:35.27-35.36|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.jump_priv ; + (* hdlname = "core frontend jump_target" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:34.27-34.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.jump_target ; + (* hdlname = "core frontend level_next_no_fetch" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:440.12-440.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + (* unused_bits = "1" *) + wire [1:0] \core.frontend.level_next_no_fetch ; + (* hdlname = "core frontend mem_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:22.27-22.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.mem_addr ; + (* hdlname = "core frontend mem_addr_hold" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:239.18-239.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_addr_hold ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_addr_hold_SB_DFFR_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.frontend.mem_addr_hold_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O ; + (* hdlname = "core frontend mem_addr_r" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:297.18-297.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.mem_addr_r ; + (* hdlname = "core frontend mem_addr_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:24.27-24.39|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_addr_vld ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* hdlname = "core frontend mem_data" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:26.27-26.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.mem_data ; + (* hdlname = "core frontend mem_data_err" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:27.27-27.39|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_data_err ; + (* hdlname = "core frontend mem_data_hwvld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:102.11-102.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.mem_data_hwvld ; + (* hdlname = "core frontend mem_priv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:23.27-23.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_priv ; + (* hdlname = "core frontend mem_priv_r" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:298.18-298.28|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_priv_r ; + (* hdlname = "core frontend mem_size" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:21.27-21.35|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.mem_size ; + (* hdlname = "core frontend next_instr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:542.13-542.23|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [31:0] \core.frontend.next_instr ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_10_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_11_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_12_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_13_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_14_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_15_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_16_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_7_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_8_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.frontend.next_instr_SB_LUT4_O_9_I3 ; + (* hdlname = "core frontend next_instr_is_32bit" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:543.6-543.25|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.next_instr_is_32bit ; + (* hdlname = "core frontend pending_fetches" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:332.12-332.27|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.pending_fetches ; + (* hdlname = "core frontend pending_fetches_next" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:335.12-335.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [1:0] \core.frontend.pending_fetches_next ; + (* hdlname = "core frontend predecode_rs1_coarse" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:75.27-75.47|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [4:0] \core.frontend.predecode_rs1_coarse ; + (* hdlname = "core frontend predecode_rs1_fine" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:79.27-79.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [4:0] \core.frontend.predecode_rs1_fine ; + (* hdlname = "core frontend predecode_rs2_coarse" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:76.27-76.47|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [4:0] \core.frontend.predecode_rs2_coarse ; + (* hdlname = "core frontend predecode_rs2_fine" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:80.27-80.45|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire [4:0] \core.frontend.predecode_rs2_fine ; + (* hdlname = "core frontend reset_holdoff" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:282.5-282.18|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.reset_holdoff ; + (* hdlname = "core frontend rst_n" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:12.27-12.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2" *) + wire \core.frontend.rst_n ; + (* hdlname = "core irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:74.29-74.32" *) + wire [31:0] \core.irq ; + (* hdlname = "core m_exception_return_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:911.19-911.42" *) + (* unused_bits = "1 31" *) + wire [31:0] \core.m_exception_return_addr ; + (* hdlname = "core m_fast_mul_result" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:641.19-641.36" *) + wire [31:0] \core.m_fast_mul_result ; + (* hdlname = "core m_fast_mul_result_vld" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:356.6-356.27" *) + wire \core.m_fast_mul_result_vld ; + (* hdlname = "core m_mmode_trap_entry" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:306.22-306.40" *) + wire \core.m_mmode_trap_entry ; + (* hdlname = "core m_pwr_allow_power_down" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:942.6-942.28" *) + wire \core.m_pwr_allow_power_down ; + (* hdlname = "core m_pwr_allow_sleep" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:941.6-941.23" *) + wire \core.m_pwr_allow_sleep ; + (* hdlname = "core m_pwr_allow_sleep_on_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:943.6-943.32" *) + wire \core.m_pwr_allow_sleep_on_block ; + (* hdlname = "core m_reg_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1249.6-1249.15" *) + wire \core.m_reg_wen ; + wire \core.m_reg_wen_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_reg_wen_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:358.2-358.21|/usr/local/bin/../share/yosys/ice40/arith_map.v:37.23-37.25" *) + wire [3:0] \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:358.2-358.21|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [3:0] \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:358.2-358.21|/usr/local/bin/../share/yosys/ice40/arith_map.v:49.21-49.23" *) + wire [3:0] \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O_1_I3 ; + (* hdlname = "core m_reg_wen_if_nonzero" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1248.6-1248.26" *) + wire \core.m_reg_wen_if_nonzero ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O ; + (* hdlname = "core m_result" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1114.18-1114.26" *) + wire [31:0] \core.m_result ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_10_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_11_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_12_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_13_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_14_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_15_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_16_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_18_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_18_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_19_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_19_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_20_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_20_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_21_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_21_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_22_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_22_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_23_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_23_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_25_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_26_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_27_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_28_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_29_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_2_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_30_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_31_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_4_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_5_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_6_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_7_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_8_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_9_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.m_result_SB_LUT4_O_I2 ; + (* hdlname = "core m_sleep_stall_release" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:396.6-396.27" *) + wire \core.m_sleep_stall_release ; + (* hdlname = "core m_trap_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:298.22-298.33" *) + (* unused_bits = "2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31" *) + wire [31:0] \core.m_trap_addr ; + (* hdlname = "core m_trap_is_debug_entry" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:300.22-300.43" *) + wire \core.m_trap_is_debug_entry ; + (* hdlname = "core mw_rd" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:283.22-283.27" *) + wire [4:0] \core.mw_rd ; + (* hdlname = "core mw_result" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:284.22-284.31" *) + wire [31:0] \core.mw_result ; + (* hdlname = "core power_ctrl allow_power_down" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:32.27-32.43|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.allow_power_down ; + (* hdlname = "core power_ctrl allow_sleep" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:31.27-31.38|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.allow_sleep ; + (* hdlname = "core power_ctrl allow_sleep_on_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:33.27-33.47|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.allow_sleep_on_block ; + (* hdlname = "core power_ctrl block_wakeup_req_pulse" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:42.27-42.49|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + (* unused_bits = "0" *) + wire \core.power_ctrl.block_wakeup_req_pulse ; + (* hdlname = "core power_ctrl clk_always_on" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:13.27-13.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.clk_always_on ; + (* hdlname = "core power_ctrl clk_en" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:28.27-28.33|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.clk_en ; + (* hdlname = "core power_ctrl pwrup_ack" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:21.27-21.36|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.pwrup_ack ; + (* hdlname = "core power_ctrl pwrup_req" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:20.27-20.36|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.pwrup_req ; + (* hdlname = "core power_ctrl rst_n" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:14.27-14.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.rst_n ; + (* hdlname = "core power_ctrl sleeping_on_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:41.27-41.44|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.sleeping_on_block ; + (* hdlname = "core power_ctrl sleeping_on_wfi" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:39.27-39.42|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.sleeping_on_wfi ; + (* hdlname = "core power_ctrl stall_release" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:43.27-43.40|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2" *) + wire \core.power_ctrl.stall_release ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:0.0-0.0|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:74.3-117.10|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2|/usr/local/bin/../share/yosys/techmap.v:575.21-575.22" *) + wire \core.power_ctrl.stall_release_SB_DFFR_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.power_ctrl.stall_release_SB_LUT4_I2_O ; + (* onehot = 32'd1 *) + wire [3:0] \core.power_ctrl.state ; + wire \core.power_ctrl.state_SB_DFFR_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 ; + wire \core.power_ctrl.state_SB_DFFS_Q_D ; + (* hdlname = "core prev_instr_was_32_bit" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:883.5-883.26" *) + wire \core.prev_instr_was_32_bit ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.prev_instr_was_32_bit_SB_DFFER_Q_E ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:49.21-49.23" *) + wire [30:0] \core.prev_instr_was_32_bit_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [30:0] \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO ; + (* hdlname = "core pwrup_ack" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:20.29-20.38" *) + wire \core.pwrup_ack ; + (* hdlname = "core pwrup_req" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:19.29-19.38" *) + wire \core.pwrup_req ; + (* hdlname = "core regs clk" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:17.13-17.16|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire \core.regs.clk ; + (* hdlname = "core regs raddr1" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:20.26-20.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire [4:0] \core.regs.raddr1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.regs.raddr1_SB_LUT4_O_I1 ; + (* hdlname = "core regs raddr2" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:23.26-23.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire [4:0] \core.regs.raddr2 ; + (* hdlname = "core regs rdata1" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:21.26-21.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire [31:0] \core.regs.rdata1 ; + (* hdlname = "core regs rdata2" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:24.26-24.32|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire [31:0] \core.regs.rdata2 ; + (* hdlname = "core regs rst_n" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:18.13-18.18|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire \core.regs.rst_n ; + (* hdlname = "core regs waddr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:26.26-26.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire [4:0] \core.regs.waddr ; + (* hdlname = "core regs wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:27.26-27.31|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire [31:0] \core.regs.wdata ; + (* hdlname = "core regs wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_regfile_1w2r.v:28.26-28.29|/home/luke/proj/hazard3/hdl/hazard3_core.v:1303.3-1316.2" *) + wire \core.regs.wen ; + (* hdlname = "core rst_n" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:16.29-16.34" *) + wire \core.rst_n ; + (* hdlname = "core soft_irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:75.29-75.37" *) + wire \core.soft_irq ; + (* hdlname = "core timer_irq" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:76.29-76.38" *) + wire \core.timer_irq ; + (* hdlname = "core unblock_in" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:23.29-23.39" *) + (* unused_bits = "0" *) + wire \core.unblock_in ; + (* hdlname = "core unblock_out" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:22.29-22.40" *) + wire \core.unblock_out ; + (* hdlname = "core x_addr_sum" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.19-608.29" *) + wire [31:0] \core.x_addr_sum ; + (* hdlname = "core x_branch_was_predicted" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:745.19-745.41" *) + wire \core.x_branch_was_predicted ; + (* hdlname = "core x_btb_set" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:116.22-116.31" *) + wire \core.x_btb_set ; + (* hdlname = "core x_btb_set_src_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:117.22-117.40" *) + wire [31:0] \core.x_btb_set_src_addr ; + (* hdlname = "core x_btb_set_target_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:119.22-119.43" *) + wire [31:0] \core.x_btb_set_target_addr ; + (* hdlname = "core x_csr_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:875.19-875.30" *) + wire [31:0] \core.x_csr_wdata ; + (* hdlname = "core x_exec_pmp_fail" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:399.6-399.21" *) + wire \core.x_exec_pmp_fail ; + (* hdlname = "core x_jump_misaligned" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:742.19-742.36" *) + wire \core.x_jump_misaligned ; + (* hdlname = "core x_jump_target" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:741.19-741.32" *) + wire [31:0] \core.x_jump_target ; + (* hdlname = "core x_loadstore_pmp_fail" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:398.6-398.26" *) + wire \core.x_loadstore_pmp_fail ; + (* hdlname = "core x_mmode_execution" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:224.22-224.39" *) + wire \core.x_mmode_execution ; + (* hdlname = "core x_mmode_loadstore" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:305.22-305.39" *) + wire \core.x_mmode_loadstore ; + (* hdlname = "core x_muldiv_result" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:640.19-640.34" *) + wire [31:0] \core.x_muldiv_result ; + (* hdlname = "core x_op_a" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:293.22-293.28" *) + wire [31:0] \core.x_op_a ; + (* hdlname = "core x_pmp_cfg_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:791.19-791.33" *) + wire [11:0] \core.x_pmp_cfg_addr ; + (* hdlname = "core x_pmp_cfg_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:794.19-794.34" *) + wire [31:0] \core.x_pmp_cfg_rdata ; + (* hdlname = "core x_pmp_cfg_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:793.19-793.34" *) + wire [31:0] \core.x_pmp_cfg_wdata ; + (* hdlname = "core x_pmp_cfg_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:792.19-792.32" *) + wire \core.x_pmp_cfg_wen ; + (* hdlname = "core x_rdata1" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:287.22-287.30" *) + wire [31:0] \core.x_rdata1 ; + (* hdlname = "core x_rdata2" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:288.22-288.30" *) + wire [31:0] \core.x_rdata2 ; + (* hdlname = "core x_stall_muldiv" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:383.6-383.20" *) + wire \core.x_stall_muldiv ; + (* hdlname = "core x_stall_on_amo" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:350.6-350.20" *) + wire \core.x_stall_on_amo ; + (* hdlname = "core x_stall_on_exclusive_overlap" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:335.6-335.34" *) + wire \core.x_stall_on_exclusive_overlap ; + (* hdlname = "core x_trap_wfi" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:225.22-225.32" *) + wire \core.x_trap_wfi ; + (* hdlname = "core x_trig_break" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:400.6-400.18" *) + wire \core.x_trig_break ; + (* hdlname = "core x_trig_break_d_mode" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:401.6-401.25" *) + wire \core.x_trig_break_d_mode ; + (* hdlname = "core x_trig_cfg_addr" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:835.19-835.34" *) + wire [11:0] \core.x_trig_cfg_addr ; + (* hdlname = "core x_trig_cfg_rdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:838.19-838.35" *) + wire [31:0] \core.x_trig_cfg_rdata ; + (* hdlname = "core x_trig_cfg_wdata" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:837.19-837.35" *) + wire [31:0] \core.x_trig_cfg_wdata ; + (* hdlname = "core x_trig_cfg_wen" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:836.19-836.33" *) + wire \core.x_trig_cfg_wen ; + (* hdlname = "core x_use_fast_mul" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:643.6-643.20" *) + wire \core.x_use_fast_mul ; + (* hdlname = "core xm_addr_align" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:312.22-312.35" *) + wire [1:0] \core.xm_addr_align ; + (* hdlname = "core xm_delay_irq_entry_on_ls_dphase" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:318.22-318.53" *) + wire \core.xm_delay_irq_entry_on_ls_dphase ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:885.1-909.4" *) + wire \core.xm_delay_irq_entry_on_ls_dphase_SB_DFFR_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O ; + (* hdlname = "core xm_except" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:314.22-314.31" *) + wire [3:0] \core.xm_except ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4" *) + wire \core.xm_except_SB_DFFES_Q_1_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4" *) + wire \core.xm_except_SB_DFFES_Q_2_D ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1070.21-1070.42|/usr/local/bin/../share/yosys/ice40/arith_map.v:37.23-37.25" *) + wire [4:0] \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1070.21-1070.42|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [4:0] \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI ; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1070.21-1070.42|/usr/local/bin/../share/yosys/ice40/arith_map.v:49.21-49.23" *) + wire [4:0] \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I3 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4" *) + wire \core.xm_except_SB_DFFES_Q_3_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4" *) + wire \core.xm_except_SB_DFFES_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 ; + (* hdlname = "core xm_memop" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:313.22-313.30" *) + wire [4:0] \core.xm_memop ; + wire \core.xm_memop_SB_DFFER_Q_1_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_memop_SB_DFFER_Q_1_D_SB_LUT4_O_I3 ; + wire \core.xm_memop_SB_DFFER_Q_2_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O ; + wire \core.xm_memop_SB_DFFER_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 ; + wire \core.xm_memop_SB_DFFES_Q_D ; + (* hdlname = "core xm_rd" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:310.22-310.27" *) + wire [4:0] \core.xm_rd ; + wire \core.xm_rd_SB_DFFER_Q_1_D ; + wire \core.xm_rd_SB_DFFER_Q_2_D ; + wire \core.xm_rd_SB_DFFER_Q_3_D ; + wire \core.xm_rd_SB_DFFER_Q_4_D ; + wire \core.xm_rd_SB_DFFER_Q_D ; + (* hdlname = "core xm_result" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:311.22-311.31" *) + wire [31:0] \core.xm_result ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_10_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_11_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_12_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_13_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_14_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_15_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_16_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_17_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_18_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_19_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_1_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_20_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_21_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_22_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_23_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_24_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_25_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_26_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_27_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_28_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_29_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_2_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_30_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_31_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_3_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_4_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_5_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_6_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_7_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_8_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_9_D ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1100.4-1104.58" *) + wire \core.xm_result_SB_DFFER_Q_D ; + (* hdlname = "core xm_rs2" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:309.22-309.28" *) + wire [4:0] \core.xm_rs2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_rs2_SB_LUT4_I0_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_rs2_SB_LUT4_I1_1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_rs2_SB_LUT4_I1_2_O ; + (* hdlname = "core xm_sleep_block" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:317.22-317.36" *) + wire \core.xm_sleep_block ; + (* hdlname = "core xm_sleep_wfi" *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:316.22-316.34" *) + wire \core.xm_sleep_wfi ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4" *) + wire \core.xm_sleep_wfi_SB_DFFER_Q_D ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O ; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 ; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:110.19-110.34" *) + wire core_aph_excl_d; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:97.19-97.33" *) + wire core_aph_req_i; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:100.19-100.33" *) + wire core_dph_err_i; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:116.19-116.31" *) + wire [31:0] core_haddr_d; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:102.19-102.31" *) + wire [31:0] core_haddr_i; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:117.19-117.31" *) + (* unused_bits = "0 1" *) + wire [2:0] core_hsize_d; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:103.19-103.31" *) + wire [2:0] core_hsize_i; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:118.19-118.30" *) + wire core_priv_d; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:104.19-104.30" *) + wire core_priv_i; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:121.19-121.31" *) + wire [31:0] core_rdata_d; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:105.19-105.31" *) + wire [31:0] core_rdata_i; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:46.28-46.35" *) + output [31:0] d_haddr; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:50.28-50.36" *) + output [2:0] d_hburst; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:54.28-54.35" *) + output d_hexcl; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:57.28-57.37" *) + input d_hexokay; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:53.28-53.37" *) + output [7:0] d_hmaster; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:52.28-52.39" *) + output d_hmastlock; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:51.28-51.35" *) + output [3:0] d_hprot; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:59.28-59.36" *) + input [31:0] d_hrdata; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:55.28-55.36" *) + input d_hready; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:56.28-56.35" *) + input d_hresp; + wire d_hresp_SB_LUT4_I1_O; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:49.28-49.35" *) + output [2:0] d_hsize; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hsize_SB_LUT4_O_1_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hsize_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I3; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:48.28-48.36" *) + output [1:0] d_htrans; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:58.28-58.36" *) + output [31:0] d_hwdata; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_10_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_10_I2_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_11_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_12_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_12_I2_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_13_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_13_I2_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_14_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_15_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_19_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_1_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_21_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_22_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_23_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_24_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_25_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_26_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_27_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_28_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [1:0] d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_29_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_2_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_30_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_31_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_4_I0; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_8_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_8_I2_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_9_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] d_hwdata_SB_LUT4_O_9_I2_SB_LUT4_O_I1; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [3:0] d_hwdata_SB_LUT4_O_I0; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:47.28-47.36" *) + output d_hwrite; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:68.28-68.43" *) + input [31:0] dbg_data0_rdata; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:69.28-69.43" *) + output [31:0] dbg_data0_wdata; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] dbg_data0_wdata_SB_LUT4_O_28_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] dbg_data0_wdata_SB_LUT4_O_29_I2; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] dbg_data0_wdata_SB_LUT4_O_31_I2; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:70.28-70.41" *) + output dbg_data0_wen; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:65.28-65.38" *) + output dbg_halted; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:76.28-76.51" *) + output dbg_instr_caught_ebreak; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:75.28-75.54" *) + output dbg_instr_caught_exception; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:72.28-72.42" *) + input [31:0] dbg_instr_data; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:74.28-74.46" *) + output dbg_instr_data_rdy; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:73.28-73.46" *) + input dbg_instr_data_vld; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:62.28-62.40" *) + input dbg_req_halt; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:63.28-63.49" *) + input dbg_req_halt_on_reset; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:64.28-64.42" *) + input dbg_req_resume; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:66.28-66.39" *) + output dbg_running; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:78.28-78.41" *) + input [31:0] dbg_sbus_addr; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:83.28-83.40" *) + output dbg_sbus_err; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:85.28-85.42" *) + output [31:0] dbg_sbus_rdata; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:82.28-82.40" *) + output dbg_sbus_rdy; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:80.28-80.41" *) + input [1:0] dbg_sbus_size; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:81.28-81.40" *) + input dbg_sbus_vld; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:84.28-84.42" *) + input [31:0] dbg_sbus_wdata; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:79.28-79.42" *) + input dbg_sbus_write; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:192.5-192.20" *) + wire dphase_active_i; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] dphase_active_i_SB_LUT4_I3_O; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:32.28-32.35" *) + output [31:0] i_haddr; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:36.28-36.36" *) + output [2:0] i_hburst; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:39.28-39.37" *) + output [7:0] i_hmaster; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:38.28-38.39" *) + output i_hmastlock; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:37.28-37.35" *) + output [3:0] i_hprot; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:43.28-43.36" *) + input [31:0] i_hrdata; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:40.28-40.36" *) + input i_hready; + wire i_hready_SB_LUT4_I2_O; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:29.22-29.23" *) + wire i_hready_SB_LUT4_I3_O; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:51.21-51.22" *) + wire [29:0] i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO; + (* force_downto = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:33.26-33.27" *) + wire [29:0] i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:41.28-41.35" *) + input i_hresp; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:35.28-35.35" *) + output [2:0] i_hsize; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:34.28-34.36" *) + output [1:0] i_htrans; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:42.28-42.36" *) + output [31:0] i_hwdata; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:33.28-33.36" *) + output i_hwrite; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:88.28-88.31" *) + input [31:0] irq; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:22.28-22.37" *) + input pwrup_ack; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:6.21-6.22" *) + wire [2:0] pwrup_ack_SB_LUT4_I1_I3; + wire pwrup_ack_SB_LUT4_I1_O; + wire pwrup_ack_SB_LUT4_I2_O; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:21.28-21.37" *) + output pwrup_req; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:18.28-18.33" *) + input rst_n; + wire rst_n_SB_LUT4_I3_O; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:89.28-89.36" *) + input soft_irq; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:90.28-90.37" *) + input timer_irq; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:25.28-25.38" *) + input unblock_in; + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:24.28-24.39" *) + output unblock_out; + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:250.1-258.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER bus_active_dph_d_SB_DFFER_Q ( + .C(clk), + .D(bus_gnt_d), + .E(d_hready), + .Q(bus_active_dph_d), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) bus_active_dph_d_SB_LUT4_I1 ( + .I0(1'h0), + .I1(bus_active_dph_d), + .I2(d_hready), + .I3(bus_active_dph_d_SB_LUT4_I1_I3[2]), + .O(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) bus_active_dph_d_SB_LUT4_I1_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .O(bus_active_dph_d_SB_LUT4_I1_I3[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:250.1-258.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER bus_active_dph_s_SB_DFFER_Q ( + .C(clk), + .D(bus_gnt_s), + .E(d_hready), + .Q(bus_active_dph_s), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) bus_gnt_d_SB_LUT4_O ( + .I0(1'h0), + .I1(bus_gnt_ds_prev[1]), + .I2(bus_gnt_d_SB_LUT4_O_I2[1]), + .I3(bus_hold_aph), + .O(bus_gnt_d) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) bus_gnt_d_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I3(bus_hold_aph_SB_LUT4_I2_O[1]), + .O(bus_gnt_d_SB_LUT4_O_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR bus_gnt_ds_prev_SB_DFFR_Q ( + .C(clk), + .D(bus_gnt_s), + .Q(bus_gnt_ds_prev[2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR bus_gnt_ds_prev_SB_DFFR_Q_1 ( + .C(clk), + .D(bus_gnt_d), + .Q(bus_gnt_ds_prev[1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf044) + ) bus_gnt_s_SB_LUT4_O ( + .I0(bus_gnt_d_SB_LUT4_O_I2[1]), + .I1(bus_gnt_s_SB_LUT4_O_I1[1]), + .I2(bus_gnt_ds_prev[2]), + .I3(bus_hold_aph), + .O(bus_gnt_s) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:234.1-242.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR bus_hold_aph_SB_DFFR_Q ( + .C(clk), + .D(bus_hold_aph_SB_DFFR_Q_D), + .Q(bus_hold_aph), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) bus_hold_aph_SB_LUT4_I2 ( + .I0(1'h0), + .I1(bus_gnt_ds_prev[1]), + .I2(bus_hold_aph), + .I3(d_hready), + .O(bus_hold_aph_SB_LUT4_I2_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.power_ctrl.stall_release_SB_LUT4_I2_O [1]), + .I1(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[1]), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I3[3]), + .O(bus_hold_aph_SB_LUT4_I2_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7f00) + ) bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [0]), + .I1(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [1]), + .I2(bus_active_dph_d_SB_LUT4_I1_I3[2]), + .I3(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]), + .O(bus_hold_aph_SB_LUT4_I2_O[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[1]), + .I3(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_1_I3[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf800) + ) bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I3(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .O(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h03f7) + ) bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.x_jump_misaligned ), + .I1(\core.frontend.cir [13]), + .I2(\core.frontend.cir [12]), + .I3(\core.bus_haddr_d [0]), + .O(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I3[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc [1]), + .I2(\core.alu.op_a_SB_LUT4_O_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.decode_u.pc [3]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.decode_u.pc [14]), + .I2(\core.alu.op_a_SB_LUT4_O_10_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_10_I2 [1]), + .I2(\core.decode_u.pc [14]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O ( + .I0(\core.xm_result [14]), + .I1(\core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_10_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [14]), + .I2(\core.mw_result [14]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.decode_u.pc [16]), + .I2(\core.alu.op_a_SB_LUT4_O_11_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_11_I2 [1]), + .I2(\core.decode_u.pc [16]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O ( + .I0(\core.xm_result [16]), + .I1(\core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_11_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [16]), + .I2(\core.mw_result [16]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.decode_u.pc [19]), + .I2(\core.alu.op_a_SB_LUT4_O_12_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_12_I2 [1]), + .I2(\core.decode_u.pc [19]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O ( + .I0(\core.xm_result [19]), + .I1(\core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_12_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [19]), + .I2(\core.mw_result [19]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.decode_u.pc [20]), + .I2(\core.alu.op_a_SB_LUT4_O_13_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_13_I2 [0]), + .I2(\core.decode_u.pc [20]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O ( + .I0(\core.xm_result [20]), + .I1(\core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_13_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [20]), + .I2(\core.mw_result [20]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.decode_u.pc [9]), + .I2(\core.alu.op_a_SB_LUT4_O_14_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_14_I2 [1]), + .I2(\core.decode_u.pc [9]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O ( + .I0(\core.xm_result [9]), + .I1(\core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_14_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [9]), + .I2(\core.mw_result [9]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.decode_u.pc [15]), + .I2(\core.alu.op_a_SB_LUT4_O_15_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_15_I2 [1]), + .I2(\core.decode_u.pc [15]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O ( + .I0(\core.xm_result [15]), + .I1(\core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_15_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [15]), + .I2(\core.mw_result [15]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.decode_u.pc [24]), + .I2(\core.alu.op_a_SB_LUT4_O_16_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_16_I2 [1]), + .I2(\core.decode_u.pc [24]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O ( + .I0(\core.xm_result [24]), + .I1(\core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_16_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [24]), + .I2(\core.mw_result [24]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.decode_u.pc [2]), + .I2(\core.alu.op_a_SB_LUT4_O_17_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_17_I2 [1]), + .I2(\core.decode_u.pc [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O ( + .I0(\core.xm_result [2]), + .I1(\core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_17_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [2]), + .I2(\core.mw_result [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.op_a_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.op_a_SB_LUT4_O_18_I3 [1]), + .O(\core.alu.op_a [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .I3(\core.alu.op_a_SB_LUT4_O_18_I3 [1]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O ( + .I0(\core.xm_result [0]), + .I1(\core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_18_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [0]), + .I2(\core.mw_result [0]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.decode_u.pc [30]), + .I2(\core.alu.op_a_SB_LUT4_O_19_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_19_I2 [1]), + .I2(\core.decode_u.pc [30]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O ( + .I0(\core.xm_result [30]), + .I1(\core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_19_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [30]), + .I2(\core.mw_result [30]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.decode_u.pc [18]), + .I2(\core.alu.op_a_SB_LUT4_O_2_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.decode_u.pc [17]), + .I2(\core.alu.op_a_SB_LUT4_O_20_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_20_I2 [1]), + .I2(\core.decode_u.pc [17]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O ( + .I0(\core.xm_result [17]), + .I1(\core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_20_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [17]), + .I2(\core.mw_result [17]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.decode_u.pc [13]), + .I2(\core.alu.op_a_SB_LUT4_O_21_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_21_I2 [1]), + .I2(\core.decode_u.pc [13]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O ( + .I0(\core.xm_result [13]), + .I1(\core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_21_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [13]), + .I2(\core.mw_result [13]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.decode_u.pc [28]), + .I2(\core.alu.op_a_SB_LUT4_O_22_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_22_I2 [0]), + .I2(\core.decode_u.pc [28]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O ( + .I0(\core.xm_result [28]), + .I1(\core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_22_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [28]), + .I2(\core.mw_result [28]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.decode_u.pc [27]), + .I2(\core.alu.op_a_SB_LUT4_O_23_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_23_I2 [0]), + .I2(\core.decode_u.pc [27]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O ( + .I0(\core.xm_result [27]), + .I1(\core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_23_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [27]), + .I2(\core.mw_result [27]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.decode_u.pc [11]), + .I2(\core.alu.op_a_SB_LUT4_O_24_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_24_I2 [1]), + .I2(\core.decode_u.pc [11]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O ( + .I0(\core.xm_result [11]), + .I1(\core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_24_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [11]), + .I2(\core.mw_result [11]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.decode_u.pc [5]), + .I2(\core.alu.op_a_SB_LUT4_O_25_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_25_I2 [1]), + .I2(\core.decode_u.pc [5]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O ( + .I0(\core.xm_result [5]), + .I1(\core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_25_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [5]), + .I2(\core.mw_result [5]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.decode_u.pc [10]), + .I2(\core.alu.op_a_SB_LUT4_O_26_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_26_I2 [1]), + .I2(\core.decode_u.pc [10]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O ( + .I0(\core.xm_result [10]), + .I1(\core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_26_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [10]), + .I2(\core.mw_result [10]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.decode_u.pc [7]), + .I2(\core.alu.op_a_SB_LUT4_O_27_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_27_I2 [1]), + .I2(\core.decode_u.pc [7]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O ( + .I0(\core.xm_result [7]), + .I1(\core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_27_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [7]), + .I2(\core.mw_result [7]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.decode_u.pc [12]), + .I2(\core.alu.op_a_SB_LUT4_O_28_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_28_I2 [1]), + .I2(\core.decode_u.pc [12]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O ( + .I0(\core.xm_result [12]), + .I1(\core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_28_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [12]), + .I2(\core.mw_result [12]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.decode_u.pc [22]), + .I2(\core.alu.op_a_SB_LUT4_O_29_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_29_I2 [0]), + .I2(\core.decode_u.pc [22]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O ( + .I0(\core.xm_result [22]), + .I1(\core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_29_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [22]), + .I2(\core.mw_result [22]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_2_I2 [1]), + .I2(\core.decode_u.pc [18]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O ( + .I0(\core.xm_result [18]), + .I1(\core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_2_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [18]), + .I2(\core.mw_result [18]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.decode_u.pc [23]), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(\core.decode_u.pc [31]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(\core.decode_u.pc [8]), + .I2(\core.alu.op_a_SB_LUT4_O_31_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_31_I2 [1]), + .I2(\core.decode_u.pc [8]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O ( + .I0(\core.xm_result [8]), + .I1(\core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_31_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [8]), + .I2(\core.mw_result [8]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_3_I2_SB_LUT4_O ( + .I0(\core.xm_result [23]), + .I1(\core.d_rs1_predecoded_SB_LUT4_I1_7_O_SB_LUT4_I3_O [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_3_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.decode_u.pc [4]), + .I2(\core.alu.op_a_SB_LUT4_O_4_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_4_I2 [1]), + .I2(\core.decode_u.pc [4]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O ( + .I0(\core.xm_result [4]), + .I1(\core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_4_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [4]), + .I2(\core.mw_result [4]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.decode_u.pc [6]), + .I2(\core.alu.op_a_SB_LUT4_O_5_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_5_I2 [1]), + .I2(\core.decode_u.pc [6]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O ( + .I0(\core.xm_result [6]), + .I1(\core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_5_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [6]), + .I2(\core.mw_result [6]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.decode_u.pc [26]), + .I2(\core.alu.op_a_SB_LUT4_O_6_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_6_I2 [1]), + .I2(\core.decode_u.pc [26]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O ( + .I0(\core.xm_result [26]), + .I1(\core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_6_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [26]), + .I2(\core.mw_result [26]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.decode_u.pc [21]), + .I2(\core.alu.op_a_SB_LUT4_O_7_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_7_I2 [1]), + .I2(\core.decode_u.pc [21]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O ( + .I0(\core.xm_result [21]), + .I1(\core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_7_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [21]), + .I2(\core.mw_result [21]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.decode_u.pc [25]), + .I2(\core.alu.op_a_SB_LUT4_O_8_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_8_I2 [0]), + .I2(\core.decode_u.pc [25]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O ( + .I0(\core.xm_result [25]), + .I1(\core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_8_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [25]), + .I2(\core.mw_result [25]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.decode_u.pc [29]), + .I2(\core.alu.op_a_SB_LUT4_O_9_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_9_I2 [0]), + .I2(\core.decode_u.pc [29]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O ( + .I0(\core.xm_result [29]), + .I1(\core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_9_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [29]), + .I2(\core.mw_result [29]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2 [1]), + .I2(\core.decode_u.pc [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I2(\core.decode_u.pc [31]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_3_I2 [1]), + .I2(\core.decode_u.pc [23]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [0]), + .I2(\core.decode_u.pc [3]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_result [1]), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.alu.op_a_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [1]), + .I2(\core.mw_result [1]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_1_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_10_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0110) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_10_I2 [0]), + .I3(\core.alu.op_a [21]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I3(\core.alu.op_a [30]), + .O(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fe) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [2]), + .I3(\core.alu.op_a [28]), + .O(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000b) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .O(\core.alu.op_b_inv_SB_LUT4_O_10_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h33f0) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [21]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [21]), + .O(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [21]), + .I2(\core.mw_result [21]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_11 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_11_I0 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_11_I0 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [20]), + .O(\core.alu.op_b_inv_SB_LUT4_O_11_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'ha300) + ) \core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1 ( + .I0(\core.xm_result [20]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .O(\core.alu.op_b_inv_SB_LUT4_O_11_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [20]), + .I2(\core.mw_result [20]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_12 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [19]), + .O(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [19]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [19]), + .I2(\core.mw_result [19]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_13_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0007) + ) \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0 [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_13_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [18]), + .O(\core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result [18]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [18]), + .I2(\core.mw_result [18]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_14 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_14_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_14_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_14_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_14_I1 [2]), + .I3(\core.alu.op_a [17]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.op_a [13]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [2]), + .I3(\core.alu.op_a [28]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [17]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [17]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [17]), + .I2(\core.mw_result [17]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_15 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_15_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_15_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h01fe) + ) \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_15_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_15_I1 [2]), + .I3(\core.alu.op_a [16]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [16]), + .O(\core.alu.op_b_inv_SB_LUT4_O_15_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_15_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [16]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [16]), + .I2(\core.mw_result [16]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_16 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_16_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_16_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_16_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_16_I1 [2]), + .I3(\core.alu.op_a [15]), + .O(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [15]), + .O(\core.alu.op_b_inv_SB_LUT4_O_16_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_16_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [15]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [15]), + .I2(\core.mw_result [15]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_17 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [14]), + .O(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [14]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [14]), + .I2(\core.mw_result [14]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_18 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000e) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1 ( + .I0(\core.alu.op_a [12]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_19_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2 [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2 [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [2]), + .I3(\core.alu.op_a [19]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [0]), + .I3(\core.alu.op_a [22]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [3]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_11_I0 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_11_I0 [2]), + .I3(\core.alu.op_a [20]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [12]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [12]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [12]), + .I2(\core.mw_result [12]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ee0) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_1_I2 [0]), + .I1(\core.alu.op_a [30]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .I3(\core.alu.op_a [0]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [3]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_I1_O [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [30]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h33f0) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [30]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [30]), + .I2(\core.mw_result [30]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_2 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_2_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_2_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_20_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .O(\core.alu.op_b_inv_SB_LUT4_O_20_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [11]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [11]), + .I2(\core.mw_result [11]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_21_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0770) + ) \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_I3 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_24_I2 [0]), + .I1(\core.alu.op_a [7]), + .I2(\core.alu.op_a [10]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_21_I2 [0]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_21_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [10]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [30]), + .O(\core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [10]), + .I2(\core.mw_result [10]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_22_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3c00) + ) \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_22_I2 [0]), + .I2(\core.alu.op_a [9]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_I1_I3 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_I1_I3_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_4_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_4_I1 [2]), + .I3(\core.alu.op_a [27]), + .O(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_I1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_22_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [9]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [29]), + .O(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [9]), + .I2(\core.mw_result [9]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_23_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1428) + ) \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_23_I2 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_a [31]), + .I3(\core.alu.op_a [8]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [3]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [8]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [28]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [8]), + .I2(\core.mw_result [8]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_24_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000e) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1 ( + .I0(\core.alu.op_a [7]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_24_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2 [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2 [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [2]), + .I3(\core.alu.op_a [12]), + .O(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fe) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2_SB_LUT4_O_1 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.op_a [22]), + .O(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_24_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [7]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [27]), + .O(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [7]), + .I2(\core.mw_result [7]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_25_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1428) + ) \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_25_I2 [0]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.alu.op_a [4]), + .I3(\core.alu.op_a [6]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_25_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [6]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [26]), + .O(\core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [6]), + .I2(\core.mw_result [6]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_26_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1428) + ) \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_26_I2 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_20_I2 [0]), + .I2(\core.alu.op_a [11]), + .I3(\core.alu.op_a [5]), + .O(\core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fbb) + ) \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [3]), + .I1(\core.frontend.cir [25]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2 [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .O(\core.alu.op_b_inv_SB_LUT4_O_26_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [5]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [5]), + .I2(\core.mw_result [5]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h01fe) + ) \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_2_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_2_I1 [2]), + .I3(\core.alu.op_a [29]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [2]), + .I3(\core.alu.op_a [14]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [29]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [29]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [29]), + .I2(\core.mw_result [29]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_3 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [28]), + .O(\core.alu.op_b_inv_SB_LUT4_O_3_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h33f0) + ) \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [28]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [28]), + .I2(\core.mw_result [28]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_4 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_4_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_4_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [27]), + .O(\core.alu.op_b_inv_SB_LUT4_O_4_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_4_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [27]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [27]), + .I2(\core.mw_result [27]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf30) + ) \core.alu.op_b_inv_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_5_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_5_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [26]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .O(\core.alu.op_b_inv_SB_LUT4_O_5_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hac00) + ) \core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1 ( + .I0(\core.xm_result [26]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1_I1 [1]), + .I2(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .O(\core.alu.op_b_inv_SB_LUT4_O_5_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [26]), + .I2(\core.mw_result [26]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_6 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_6_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_6_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h01fe) + ) \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_6_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_6_I1 [2]), + .I3(\core.alu.op_a [25]), + .O(\core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [25]), + .O(\core.alu.op_b_inv_SB_LUT4_O_6_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_6_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [25]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [25]), + .I2(\core.mw_result [25]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_7_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1428) + ) \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_I1 ( + .I0(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_7_I2 [1]), + .I2(\core.alu.op_a [24]), + .I3(\core.alu.op_a [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0007) + ) \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0 [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_7_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [24]), + .O(\core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result [24]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [24]), + .I2(\core.mw_result [24]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0ff0) + ) \core.alu.op_b_inv_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_b_inv_SB_LUT4_O_8_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1428) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_8_I2 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_13_I2 [0]), + .I2(\core.alu.op_a [18]), + .I3(\core.alu.op_a [23]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_I0 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [3]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [2]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf30) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_5_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_5_I1 [1]), + .I3(\core.alu.op_a [26]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h07f8) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]), + .I3(\core.alu.op_a [1]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf40b) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [0]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.op_a [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fe) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [2]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_17_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.op_a [14]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fe) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_3 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [2]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_12_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.op_a [19]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [21]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [1]), + .I2(\core.mw_result [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0007) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0 [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0 [3]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [23]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result [23]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [23]), + .I2(\core.mw_result [23]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe01) + ) \core.alu.op_b_inv_SB_LUT4_O_9 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.op_b_inv [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [22]), + .O(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_9_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [22]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [22]), + .I2(\core.mw_result [22]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [31]), + .I2(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI ( + .CI(\core.alu.sub ), + .CO(\core.alu.sub_SB_CARRY_CI_CO [1]), + .I0(\core.alu.op_a [0]), + .I1(\core.alu.op_b_inv [0]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [9]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [10]), + .I0(\core.alu.op_a [9]), + .I1(\core.alu.op_b_inv [9]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_1 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [8]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [9]), + .I0(\core.alu.op_a [8]), + .I1(\core.alu.op_b_inv [8]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_10 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [28]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [29]), + .I0(\core.alu.op_a [28]), + .I1(\core.alu.op_b_inv [28]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_11 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [27]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [28]), + .I0(\core.alu.op_a [27]), + .I1(\core.alu.op_b_inv [27]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_12 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [26]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [27]), + .I0(\core.alu.op_a [26]), + .I1(\core.alu.op_b_inv [26]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_13 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [25]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [26]), + .I0(\core.alu.op_a [25]), + .I1(\core.alu.op_b_inv [25]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_14 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [24]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [25]), + .I0(\core.alu.op_a [24]), + .I1(\core.alu.op_b_inv [24]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_15 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [23]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [24]), + .I0(\core.alu.op_a [23]), + .I1(\core.alu.op_b_inv [23]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_16 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [22]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [23]), + .I0(\core.alu.op_a [22]), + .I1(\core.alu.op_b_inv [22]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_17 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [21]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [22]), + .I0(\core.alu.op_a [21]), + .I1(\core.alu.op_b_inv [21]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_18 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [20]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [21]), + .I0(\core.alu.op_a [20]), + .I1(\core.alu.op_b_inv [20]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_19 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [1]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [2]), + .I0(\core.alu.op_a [1]), + .I1(\core.alu.op_b_inv [1]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_2 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [7]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [8]), + .I0(\core.alu.op_a [7]), + .I1(\core.alu.op_b_inv [7]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_20 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [19]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [20]), + .I0(\core.alu.op_a [19]), + .I1(\core.alu.op_b_inv [19]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_21 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [18]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [19]), + .I0(\core.alu.op_a [18]), + .I1(\core.alu.op_b_inv [18]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_22 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [17]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [18]), + .I0(\core.alu.op_a [17]), + .I1(\core.alu.op_b_inv [17]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_23 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [16]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [17]), + .I0(\core.alu.op_a [16]), + .I1(\core.alu.op_b_inv [16]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_24 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [15]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [16]), + .I0(\core.alu.op_a [15]), + .I1(\core.alu.op_b_inv [15]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_25 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [14]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [15]), + .I0(\core.alu.op_a [14]), + .I1(\core.alu.op_b_inv [14]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_26 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [13]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [14]), + .I0(\core.alu.op_a [13]), + .I1(\core.alu.op_b_inv [13]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_27 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [12]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [13]), + .I0(\core.alu.op_a [12]), + .I1(\core.alu.op_b_inv [12]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_28 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [11]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [12]), + .I0(\core.alu.op_a [11]), + .I1(\core.alu.op_b_inv [11]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_29 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [10]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [11]), + .I0(\core.alu.op_a [10]), + .I1(\core.alu.op_b_inv [10]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_3 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [6]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [7]), + .I0(\core.alu.op_a [6]), + .I1(\core.alu.op_b_inv [6]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_4 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [5]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [6]), + .I0(\core.alu.op_a [5]), + .I1(\core.alu.op_b_inv [5]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_5 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [4]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [5]), + .I0(\core.alu.op_a [4]), + .I1(\core.alu.op_b_inv [4]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_6 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [3]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [4]), + .I0(\core.alu.op_a [3]), + .I1(\core.alu.op_b_inv [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_7 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [30]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [31]), + .I0(\core.alu.op_a [30]), + .I1(\core.alu.op_b_inv [30]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_8 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [2]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [3]), + .I0(\core.alu.op_a [2]), + .I1(\core.alu.op_b_inv [2]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.alu.sub_SB_CARRY_CI_CO_SB_CARRY_CO_9 ( + .CI(\core.alu.sub_SB_CARRY_CI_CO [29]), + .CO(\core.alu.sub_SB_CARRY_CI_CO [30]), + .I0(\core.alu.op_a [29]), + .I1(\core.alu.op_b_inv [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub ), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [3]), + .O(\core.alu.sub_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h17b2) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.alu.op_b_inv_SB_LUT4_O_I2 [0]), + .I1(\core.alu.sum [31]), + .I2(\core.alu.op_a [31]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]), + .O(\core.alu.sub_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbf00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2 ( + .I0(\core.frontend.cir [6]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [1]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [4]), + .I3(\core.frontend.cir [5]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2_SB_LUT4_O_1 ( + .I0(\core.frontend.cir [2]), + .I1(\core.frontend.cir [3]), + .I2(\core.frontend.cir [0]), + .I3(\core.frontend.cir [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0 [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [1]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O [3]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0 [1]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [20]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [0]), + .I2(\core.mw_result [0]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [1]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [3]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h53ff) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [2]), + .I2(\core.frontend.cir [14]), + .I3(\core.frontend.cir [13]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [31]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [13]), + .I3(\core.frontend.cir [14]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [12]), + .I1(\core.frontend.cir [6]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h001f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_I0 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [3]), + .O(\core.d_rs2_SB_LUT4_O_4_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h001f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [1]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [25]), + .I2(\core.frontend.cir [26]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1fff) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3 [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [31]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [13]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [13]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [13]), + .I2(\core.mw_result [13]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [3]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h03ff) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [0]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I3_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_1_I1 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [31]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_O_I2 [0]), + .I3(\core.frontend.cir [14]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [25]), + .I2(\core.frontend.cir [13]), + .I3(\core.frontend.cir [26]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h10ff) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .I3(\core.frontend.cir [12]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h03ff) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [1]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [0]), + .I2(\core.alu.op_a [31]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [27]), + .I1(\core.frontend.cir [29]), + .I2(\core.frontend.cir [28]), + .I3(\core.frontend.cir [30]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h07ff) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O_SB_LUT4_O ( + .I0(\core.frontend.cir [5]), + .I1(\core.frontend.cir [31]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2]), + .I3(\core.frontend.cir [4]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.cir [13]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [12]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [6]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [25]), + .I2(\core.frontend.cir [26]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [27]), + .I2(\core.frontend.cir [28]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [30]), + .I3(\core.frontend.cir [29]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf53f) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [1]), + .I1(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I2(\core.frontend.cir [14]), + .I3(\core.frontend.cir [13]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [5]), + .I2(\core.frontend.cir [4]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.cir [5]), + .I2(\core.frontend.cir [4]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2]), + .O(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fff) + ) \core.alu.sub_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]), + .O(\core.alu.sub ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [9]), + .I2(\core.alu.op_b_inv [9]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [9]), + .O(\core.alu.sum [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [8]), + .I2(\core.alu.op_b_inv [8]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [8]), + .O(\core.alu.sum [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.alu.op_a [29]), + .I2(\core.alu.op_b_inv [29]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [29]), + .O(\core.alu.sum [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.alu.op_a [28]), + .I2(\core.alu.op_b_inv [28]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [28]), + .O(\core.alu.sum [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.alu.op_a [27]), + .I2(\core.alu.op_b_inv [27]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [27]), + .O(\core.alu.sum [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.alu.op_a [26]), + .I2(\core.alu.op_b_inv [26]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [26]), + .O(\core.alu.sum [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.alu.op_a [25]), + .I2(\core.alu.op_b_inv [25]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [25]), + .O(\core.alu.sum [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.alu.op_a [24]), + .I2(\core.alu.op_b_inv [24]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [24]), + .O(\core.alu.sum [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.alu.op_a [23]), + .I2(\core.alu.op_b_inv [23]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [23]), + .O(\core.alu.sum [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.alu.op_a [22]), + .I2(\core.alu.op_b_inv [22]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [22]), + .O(\core.alu.sum [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.alu.op_a [21]), + .I2(\core.alu.op_b_inv [21]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [21]), + .O(\core.alu.sum [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.alu.op_a [20]), + .I2(\core.alu.op_b_inv [20]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [20]), + .O(\core.alu.sum [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.alu.op_a [7]), + .I2(\core.alu.op_b_inv [7]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [7]), + .O(\core.alu.sum [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.alu.op_a [1]), + .I2(\core.alu.op_b_inv [1]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [1]), + .O(\core.alu.sum [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.alu.op_a [19]), + .I2(\core.alu.op_b_inv [19]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [19]), + .O(\core.alu.sum [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.alu.op_a [18]), + .I2(\core.alu.op_b_inv [18]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [18]), + .O(\core.alu.sum [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.alu.op_a [17]), + .I2(\core.alu.op_b_inv [17]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [17]), + .O(\core.alu.sum [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.alu.op_a [16]), + .I2(\core.alu.op_b_inv [16]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [16]), + .O(\core.alu.sum [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.alu.op_a [15]), + .I2(\core.alu.op_b_inv [15]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [15]), + .O(\core.alu.sum [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.alu.op_a [14]), + .I2(\core.alu.op_b_inv [14]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [14]), + .O(\core.alu.sum [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.alu.op_a [13]), + .I2(\core.alu.op_b_inv [13]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [13]), + .O(\core.alu.sum [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.alu.op_a [12]), + .I2(\core.alu.op_b_inv [12]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [12]), + .O(\core.alu.sum [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.alu.op_a [11]), + .I2(\core.alu.op_b_inv [11]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [11]), + .O(\core.alu.sum [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.alu.op_a [6]), + .I2(\core.alu.op_b_inv [6]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [6]), + .O(\core.alu.sum [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(\core.alu.op_a [10]), + .I2(\core.alu.op_b_inv [10]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [10]), + .O(\core.alu.sum [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(\core.alu.op_a [0]), + .I2(\core.alu.op_b_inv [0]), + .I3(\core.alu.sub ), + .O(\core.alu.sum [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.alu.op_a [5]), + .I2(\core.alu.op_b_inv [5]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [5]), + .O(\core.alu.sum [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.alu.op_a [4]), + .I2(\core.alu.op_b_inv [4]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [4]), + .O(\core.alu.sum [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.alu.op_a [3]), + .I2(\core.alu.op_b_inv [3]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [3]), + .O(\core.alu.sum [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.alu.op_a [31]), + .I2(\core.alu.op_b_inv [31]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [31]), + .O(\core.alu.sum [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.alu.op_a [30]), + .I2(\core.alu.op_b_inv [30]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [30]), + .O(\core.alu.sum [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/arith/hazard3_alu.v:41.26-41.55|/home/luke/proj/hazard3/hdl/hazard3_core.v:479.3-487.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.alu.sum_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.alu.op_a [2]), + .I2(\core.alu.op_b_inv [2]), + .I3(\core.alu.sub_SB_CARRY_CI_CO [2]), + .O(\core.alu.sum [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.bus_haddr_d_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.x_jump_misaligned ), + .I2(\core.bus_haddr_d [0]), + .I3(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(d_hsize_SB_LUT4_O_1_I1[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.bus_haddr_d_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.d_addr_offs [0]), + .I3(1'h0), + .O(\core.bus_haddr_d [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q ( + .C(clk_always_on), + .D(irq[31]), + .Q(\core.csr_u.irq_r [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_1 ( + .C(clk_always_on), + .D(irq[30]), + .Q(\core.csr_u.irq_r [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_10 ( + .C(clk_always_on), + .D(irq[21]), + .Q(\core.csr_u.irq_r [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_11 ( + .C(clk_always_on), + .D(irq[20]), + .Q(\core.csr_u.irq_r [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_12 ( + .C(clk_always_on), + .D(irq[19]), + .Q(\core.csr_u.irq_r [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_13 ( + .C(clk_always_on), + .D(irq[18]), + .Q(\core.csr_u.irq_r [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_14 ( + .C(clk_always_on), + .D(irq[17]), + .Q(\core.csr_u.irq_r [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_15 ( + .C(clk_always_on), + .D(irq[16]), + .Q(\core.csr_u.irq_r [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_16 ( + .C(clk_always_on), + .D(irq[15]), + .Q(\core.csr_u.irq_r [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_17 ( + .C(clk_always_on), + .D(irq[14]), + .Q(\core.csr_u.irq_r [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_18 ( + .C(clk_always_on), + .D(irq[13]), + .Q(\core.csr_u.irq_r [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_19 ( + .C(clk_always_on), + .D(irq[12]), + .Q(\core.csr_u.irq_r [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_2 ( + .C(clk_always_on), + .D(irq[29]), + .Q(\core.csr_u.irq_r [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_20 ( + .C(clk_always_on), + .D(irq[11]), + .Q(\core.csr_u.irq_r [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_21 ( + .C(clk_always_on), + .D(irq[10]), + .Q(\core.csr_u.irq_r [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_22 ( + .C(clk_always_on), + .D(irq[9]), + .Q(\core.csr_u.irq_r [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_23 ( + .C(clk_always_on), + .D(irq[8]), + .Q(\core.csr_u.irq_r [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_24 ( + .C(clk_always_on), + .D(irq[7]), + .Q(\core.csr_u.irq_r [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_25 ( + .C(clk_always_on), + .D(irq[6]), + .Q(\core.csr_u.irq_r [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_26 ( + .C(clk_always_on), + .D(irq[5]), + .Q(\core.csr_u.irq_r [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_27 ( + .C(clk_always_on), + .D(irq[4]), + .Q(\core.csr_u.irq_r [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_28 ( + .C(clk_always_on), + .D(irq[3]), + .Q(\core.csr_u.irq_r [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_29 ( + .C(clk_always_on), + .D(irq[2]), + .Q(\core.csr_u.irq_r [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_3 ( + .C(clk_always_on), + .D(irq[28]), + .Q(\core.csr_u.irq_r [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_30 ( + .C(clk_always_on), + .D(irq[1]), + .Q(\core.csr_u.irq_r [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_31 ( + .C(clk_always_on), + .D(irq[0]), + .Q(\core.csr_u.irq_r [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_4 ( + .C(clk_always_on), + .D(irq[27]), + .Q(\core.csr_u.irq_r [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_5 ( + .C(clk_always_on), + .D(irq[26]), + .Q(\core.csr_u.irq_r [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_6 ( + .C(clk_always_on), + .D(irq[25]), + .Q(\core.csr_u.irq_r [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_7 ( + .C(clk_always_on), + .D(irq[24]), + .Q(\core.csr_u.irq_r [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_8 ( + .C(clk_always_on), + .D(irq[23]), + .Q(\core.csr_u.irq_r [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:458.1-464.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_r_SB_DFFR_Q_9 ( + .C(clk_always_on), + .D(irq[22]), + .Q(\core.csr_u.irq_r [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1417.1-1425.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_software_r_SB_DFFR_Q ( + .C(clk_always_on), + .D(soft_irq), + .Q(\core.csr_u.irq_software_r ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.irq_software_r_SB_LUT4_I0 ( + .I0(\core.csr_u.irq_software_r ), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [1]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [3]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O [0]), + .I2(\core.csr_u.irq_software_r_SB_LUT4_I0_O [1]), + .I3(\core.csr_u.irq_software_r_SB_LUT4_I0_O [2]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.cir [20]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [3]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mie [3]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [3]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [3]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.irq_software_r_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie [3]), + .I3(\core.csr_u.irq_software_r ), + .O(\core.csr_u.irq_software_r_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:1417.1-1425.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.irq_timer_r_SB_DFFR_Q ( + .C(clk_always_on), + .D(timer_irq), + .Q(\core.csr_u.irq_timer_r ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.irq_timer_r_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [1]), + .I3(\core.csr_u.irq_timer_r ), + .O(\core.csr_u.irq_timer_r_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.irq_timer_r_SB_LUT4_I3_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie [7]), + .I3(\core.csr_u.irq_timer_r ), + .O(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.irq_timer_r_SB_LUT4_I3_1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.irq_software_r_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.irq_software_r_SB_LUT4_I3_O [1]), + .O(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.irq_timer_r_SB_LUT4_I3_O_SB_LUT4_I2 ( + .I0(\core.csr_u.mepc [7]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.irq_timer_r_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.irq_timer_r_SB_LUT4_I3_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.irq_vector_enable_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.wdata_update [0]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.irq_vector_enable ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.irq_vector_enable_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0]), + .I3(\core.csr_u.irq_vector_enable ), + .O(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.irq_vector_enable_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.xm_except [2]), + .I1(\core.xm_except [0]), + .I2(\core.xm_except [1]), + .I3(\core.xm_except [3]), + .O(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mcause_code_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.mcause_code_SB_DFFER_Q_D ), + .E(\core.csr_u.mcause_irq_SB_DFFER_Q_E ), + .Q(\core.csr_u.mcause_code [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mcause_code_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.mcause_code_SB_DFFER_Q_1_D ), + .E(\core.csr_u.mcause_irq_SB_DFFER_Q_E ), + .Q(\core.csr_u.mcause_code [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff30) + ) \core.csr_u.mcause_code_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update [2]), + .I3(\core.csr_u.mcause_code_SB_DFFER_Q_1_D_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hd000) + ) \core.csr_u.mcause_code_SB_DFFER_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [0]), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .I3(\core.xm_except [2]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_1_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mcause_code_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.mcause_code_SB_DFFER_Q_2_D ), + .E(\core.csr_u.mcause_irq_SB_DFFER_Q_E ), + .Q(\core.csr_u.mcause_code [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'heef0) + ) \core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.wdata_update [1]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.xm_except [1]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mcause_code_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.csr_u.mcause_code_SB_DFFER_Q_3_D ), + .E(\core.csr_u.mcause_irq_SB_DFFER_Q_E ), + .Q(\core.csr_u.mcause_code [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'heef0) + ) \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.wdata_update [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.xm_except [0]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.csr_u.mcause_code_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.csr_u.mcause_code_SB_DFFER_Q_D_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [3]), + .I2(\core.csr_u.wdata_update [3]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.mcause_code_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.xm_except [3]), + .O(\core.csr_u.mcause_code_SB_DFFER_Q_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:313.1-325.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mcause_irq_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.mcause_irq_SB_DFFER_Q_D ), + .E(\core.csr_u.mcause_irq_SB_DFFER_Q_E ), + .Q(\core.csr_u.mcause_irq ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mcause_irq_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [31]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mcause_irq_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffc0) + ) \core.csr_u.mcause_irq_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mcause_irq_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mcause_irq_SB_LUT4_I1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.mcause_irq ), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [31]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hd000) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I1(\core.csr_u.mcause_irq_SB_LUT4_I1_O [1]), + .I2(\core.csr_u.mcause_irq_SB_LUT4_I1_O [2]), + .I3(\core.csr_u.mcause_irq_SB_LUT4_I1_O [3]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0]), + .I3(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O [2]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [31]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [1]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [31]), + .I1(\core.alu.op_b_inv [31]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [31]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [31]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [0]), + .I1(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [1]), + .I2(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [2]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meifa [15]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meiea [15]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meifa [31]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meiea [31]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_1_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update [11]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_2_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update [10]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_3_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update [9]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update [8]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hd000) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1 ( + .I0(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2 [2]), + .I3(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2 [3]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.csr_u.meicontext_irq [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [6]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [6]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [6]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0d00) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.sum [6]), + .I1(\core.alu.sub_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [25]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [0]), + .I3(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [9]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mscratch [25]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [25]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [25]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf800) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [25]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfac0) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.irq_r [25]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [25]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [9]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [9]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6dc4) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv [25]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.op_a [25]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [6]), + .I1(\core.alu.op_b_inv [6]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_5_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.wdata_update [7]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_6_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.wdata_update [6]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_7_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [1]), + .I2(\core.csr_u.wdata_update [5]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_irq_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.csr_u.meicontext_irq_SB_DFFER_Q_8_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_irq [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update [4]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meicontext_irq_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update [12]), + .O(\core.csr_u.meicontext_irq_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_mreteirq_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.meicontext_mreteirq_SB_DFFER_Q_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_DFFER_Q_E ), + .Q(\core.csr_u.meicontext_mreteirq ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h44f0) + ) \core.csr_u.meicontext_mreteirq_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I1(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.wdata_update [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meicontext_mreteirq_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) \core.csr_u.meicontext_mreteirq_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meicontext_mreteirq_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_mreteirq ), + .I2(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2 [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf800) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.csr_u.wdata_update [0]), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .O(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0]), + .I3(\core.csr_u.irq_software_r_SB_LUT4_I3_O [0]), + .O(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I3 ( + .I0(\core.csr_u.meicontext_mreteirq_SB_LUT4_I3_I0 [0]), + .I1(\core.csr_u.mscratch [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.meicontext_mreteirq ), + .O(\core.csr_u.meicontext_mreteirq_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I3_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meicontext_mreteirq_SB_LUT4_I3_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.meicontext_mreteirq_SB_LUT4_I3_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.irq_vector_enable ), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.meicontext_mreteirq_SB_LUT4_I3_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_31_I0_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" *) + SB_DFFES \core.csr_u.meicontext_noirq_SB_DFFES_Q ( + .C(clk), + .D(\core.csr_u.meicontext_noirq_SB_DFFES_Q_D ), + .E(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .Q(\core.csr_u.meicontext_noirq ), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meicontext_noirq_SB_DFFES_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0]), + .I2(\core.csr_u.wdata_update [15]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_noirq_SB_DFFES_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.meicontext_noirq_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_noirq ), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.meicontext_noirq_SB_LUT4_I1_I3 [2]), + .O(\core.csr_u.meicontext_noirq_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_noirq_SB_LUT4_I1_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [15]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [15]), + .O(\core.csr_u.meicontext_noirq_SB_LUT4_I1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:401.1-445.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meicontext_preempt_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.meicontext_preempt_SB_DFFER_Q_D ), + .E(\core.csr_u.meicontext_preempt_SB_DFFER_Q_E ), + .Q(\core.csr_u.meicontext_preempt [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7077) + ) \core.csr_u.meicontext_preempt_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I2(\core.csr_u.wdata_update [20]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meicontext_preempt_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000e) + ) \core.csr_u.meicontext_preempt_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [1]), + .I2(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [2]), + .I3(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [3]), + .O(\core.csr_u.meicontext_preempt_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1 ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.csr_u.meicontext_preempt [4]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [20]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hef00) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_1 ( + .I0(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0]), + .I1(\core.csr_u.meicontext_preempt [4]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [1]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_20_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O ( + .I0(\core.csr_u.mepc [11]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [0]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [11]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [11]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_irq [7]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffc0) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.mie [11]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h70ff) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.csr_u.meiea [4]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [20]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [20]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [20]), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [20]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [20]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.irq_r [4]), + .I2(\core.csr_u.meifa [4]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I2 ( + .I0(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [0]), + .I1(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1]), + .I2(\core.csr_u.meicontext_preempt [4]), + .I3(\core.csr_u.mie [11]), + .O(\core.csr_u.irq_software_r_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O ( + .I0(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [3]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [3]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [28]), + .I2(\core.csr_u.meifa [28]), + .I3(\core.csr_u.meiea [28]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [29]), + .I2(\core.csr_u.meifa [29]), + .I3(\core.csr_u.meiea [29]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [2]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_1_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_10_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_10_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [21]), + .I2(\core.csr_u.wdata_update [21]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_11_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_11_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [20]), + .I2(\core.csr_u.wdata_update [20]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_12_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_12_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [19]), + .I2(\core.csr_u.wdata_update [19]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_13_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_13_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [18]), + .I2(\core.csr_u.wdata_update [18]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_14_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_14_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [17]), + .I2(\core.csr_u.wdata_update [17]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_15_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_15_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [16]), + .I2(\core.csr_u.wdata_update [16]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_16_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_16_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [15]), + .I2(\core.csr_u.wdata_update [31]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_17_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_17_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [14]), + .I2(\core.csr_u.wdata_update [30]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_18_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_18_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [13]), + .I2(\core.csr_u.wdata_update [29]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_19_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_19_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [12]), + .I2(\core.csr_u.wdata_update [28]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [30]), + .I2(\core.csr_u.wdata_update [30]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_2_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_20_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_20_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [11]), + .I2(\core.csr_u.wdata_update [27]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_21_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_21_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [10]), + .I2(\core.csr_u.wdata_update [26]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_22_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_22_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [9]), + .I2(\core.csr_u.wdata_update [25]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_23_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_23_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [8]), + .I2(\core.csr_u.wdata_update [24]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_24_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_24_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [7]), + .I2(\core.csr_u.wdata_update [23]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_25_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_25_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [6]), + .I2(\core.csr_u.wdata_update [22]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_26_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_26_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [5]), + .I2(\core.csr_u.wdata_update [21]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_27_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_27_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [4]), + .I2(\core.csr_u.wdata_update [20]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_28_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_28_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [3]), + .I2(\core.csr_u.wdata_update [19]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_29_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_29_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [2]), + .I2(\core.csr_u.wdata_update [18]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [29]), + .I2(\core.csr_u.wdata_update [29]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_3_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_30 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_30_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_30_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [1]), + .I2(\core.csr_u.wdata_update [17]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_30_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_31 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_31_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_31_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [0]), + .I2(\core.csr_u.wdata_update [16]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_31_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [28]), + .I2(\core.csr_u.wdata_update [28]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_4_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [27]), + .I2(\core.csr_u.wdata_update [27]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_5_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [26]), + .I2(\core.csr_u.wdata_update [26]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_6_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [25]), + .I2(\core.csr_u.wdata_update [25]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_7_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [24]), + .I2(\core.csr_u.wdata_update [24]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_8_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [23]), + .I2(\core.csr_u.wdata_update [23]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.meiea_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.csr_u.meiea_SB_DFFER_Q_9_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ), + .Q(\core.csr_u.meiea [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_9_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [22]), + .I2(\core.csr_u.wdata_update [22]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.meiea_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [31]), + .I2(\core.csr_u.wdata_update [31]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meiea_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_D ), + .Q(\core.csr_u.meifa [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_1 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_1_D ), + .Q(\core.csr_u.meifa [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_10 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_10_D ), + .Q(\core.csr_u.meifa [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [0]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [21]), + .I1(\core.csr_u.meifa [21]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [1]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [2]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [3]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [19]), + .I2(\core.csr_u.meifa [19]), + .I3(\core.csr_u.meiea [19]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [20]), + .I2(\core.csr_u.meifa [20]), + .I3(\core.csr_u.meiea [20]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [21]), + .I2(\core.csr_u.meifa [21]), + .I3(\core.csr_u.meiea [21]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0_SB_LUT4_O_3 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_11 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_11_D ), + .Q(\core.csr_u.meifa [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [20]), + .I1(\core.csr_u.wdata_update [20]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [2]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [3]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [16]), + .I2(\core.csr_u.meifa [16]), + .I3(\core.csr_u.meiea [16]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [17]), + .I2(\core.csr_u.meifa [17]), + .I3(\core.csr_u.meiea [17]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [18]), + .I2(\core.csr_u.meifa [18]), + .I3(\core.csr_u.meiea [18]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I1 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [2]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_12 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_12_D ), + .Q(\core.csr_u.meifa [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [1]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [1]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [2]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [3]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [3]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [19]), + .I1(\core.csr_u.meifa [19]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_13 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_13_D ), + .Q(\core.csr_u.meifa [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [18]), + .I1(\core.csr_u.wdata_update [18]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_14 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_14_D ), + .Q(\core.csr_u.meifa [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [17]), + .I1(\core.csr_u.wdata_update [17]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_15 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_15_D ), + .Q(\core.csr_u.meifa [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_15_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [16]), + .I1(\core.csr_u.wdata_update [16]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_16 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_16_D ), + .Q(\core.csr_u.meifa [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000e) + ) \core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [15]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [31]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_17 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_17_D ), + .Q(\core.csr_u.meifa [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [14]), + .I1(\core.csr_u.wdata_update [30]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I0 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [0]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [2]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_18 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_18_D ), + .Q(\core.csr_u.meifa [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [13]), + .I1(\core.csr_u.wdata_update [29]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_19 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_19_D ), + .Q(\core.csr_u.meifa [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [12]), + .I1(\core.csr_u.wdata_update [28]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [30]), + .I1(\core.csr_u.wdata_update [30]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00cf) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [3]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1_SB_LUT4_I0 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [24]), + .I2(\core.csr_u.meifa [24]), + .I3(\core.csr_u.meiea [24]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [25]), + .I2(\core.csr_u.meifa [25]), + .I3(\core.csr_u.meiea [25]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_2 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_2_D ), + .Q(\core.csr_u.meifa [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_20 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_20_D ), + .Q(\core.csr_u.meifa [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [11]), + .I1(\core.csr_u.wdata_update [27]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_21 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_21_D ), + .Q(\core.csr_u.meifa [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [10]), + .I1(\core.csr_u.wdata_update [26]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_22 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_22_D ), + .Q(\core.csr_u.meifa [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [9]), + .I1(\core.csr_u.wdata_update [25]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_23 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_23_D ), + .Q(\core.csr_u.meifa [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [8]), + .I1(\core.csr_u.wdata_update [24]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_24 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_24_D ), + .Q(\core.csr_u.meifa [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [7]), + .I1(\core.csr_u.wdata_update [23]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_25 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_25_D ), + .Q(\core.csr_u.meifa [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [6]), + .I1(\core.csr_u.wdata_update [22]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [2]), + .I2(\core.csr_u.meifa [2]), + .I3(\core.csr_u.meiea [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [3]), + .I2(\core.csr_u.meifa [3]), + .I3(\core.csr_u.meiea [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [6]), + .I2(\core.csr_u.meifa [6]), + .I3(\core.csr_u.meiea [6]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [4]), + .I2(\core.csr_u.meifa [4]), + .I3(\core.csr_u.meiea [4]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [5]), + .I2(\core.csr_u.meifa [5]), + .I3(\core.csr_u.meiea [5]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [1]), + .I2(\core.csr_u.meifa [1]), + .I3(\core.csr_u.meiea [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [0]), + .I2(\core.csr_u.meifa [0]), + .I3(\core.csr_u.meiea [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_26 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_26_D ), + .Q(\core.csr_u.meifa [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [5]), + .I1(\core.csr_u.wdata_update [21]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_27 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_27_D ), + .Q(\core.csr_u.meifa [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000e) + ) \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [4]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [20]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_28 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_28_D ), + .Q(\core.csr_u.meifa [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [3]), + .I1(\core.csr_u.wdata_update [19]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_29 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_29_D ), + .Q(\core.csr_u.meifa [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [2]), + .I1(\core.csr_u.wdata_update [18]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [29]), + .I1(\core.csr_u.wdata_update [29]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_3 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_3_D ), + .Q(\core.csr_u.meifa [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_30 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_30_D ), + .Q(\core.csr_u.meifa [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.meifa_SB_DFFR_Q_30_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_30_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_31 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_31_D ), + .Q(\core.csr_u.meifa [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_31_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [0]), + .I1(\core.csr_u.wdata_update [16]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_31_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa [28]), + .I1(\core.csr_u.wdata_update [28]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3 [0]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3 [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [1]), + .O(\core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_4 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_4_D ), + .Q(\core.csr_u.meifa [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_4_D_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [27]), + .I1(\core.csr_u.meifa [27]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_4_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_5 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_5_D ), + .Q(\core.csr_u.meifa [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h007f) + ) \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [0]), + .I1(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I3 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [27]), + .I2(\core.csr_u.meifa [27]), + .I3(\core.csr_u.meiea [27]), + .O(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [26]), + .I2(\core.csr_u.meifa [26]), + .I3(\core.csr_u.meiea [26]), + .O(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [26]), + .I1(\core.csr_u.meifa [26]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_6 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_6_D ), + .Q(\core.csr_u.meifa [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_6_D_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_6_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [25]), + .I1(\core.csr_u.meifa [25]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_6_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_7 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_7_D ), + .Q(\core.csr_u.meifa [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [0]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [24]), + .I1(\core.csr_u.meifa [24]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_8 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_8_D ), + .Q(\core.csr_u.meifa [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_8_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_8_D_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_8_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [23]), + .I1(\core.csr_u.meifa [23]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_8_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:343.1-388.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.csr_u.meifa_SB_DFFR_Q_9 ( + .C(clk), + .D(\core.csr_u.meifa_SB_DFFR_Q_9_D ), + .Q(\core.csr_u.meifa [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h007f) + ) \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [0]), + .I1(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I3 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [23]), + .I2(\core.csr_u.meifa [23]), + .I3(\core.csr_u.meiea [23]), + .O(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [22]), + .I2(\core.csr_u.meifa [22]), + .I3(\core.csr_u.meiea [22]), + .O(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_O_1_I0 [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [22]), + .I1(\core.csr_u.meifa [22]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.meifa_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_D_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h5333) + ) \core.csr_u.meifa_SB_DFFR_Q_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [31]), + .I1(\core.csr_u.meifa [31]), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.meifa_SB_DFFR_Q_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_1_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_10_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_10_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [21]), + .I2(\core.csr_u.mepc_in [21]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_11_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_11_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [20]), + .I2(\core.csr_u.mepc_in [20]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_12_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_12_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [19]), + .I2(\core.csr_u.mepc_in [19]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_13_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_13_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [18]), + .I2(\core.csr_u.wdata_update [18]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_14_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_14_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [17]), + .I2(\core.csr_u.mepc_in [17]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_15_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_15_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [16]), + .I2(\core.csr_u.wdata_update [16]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_16_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_16_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [15]), + .I2(\core.csr_u.mepc_in [15]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_17_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_17_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [14]), + .I2(\core.csr_u.mepc_in [14]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_18_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_18_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [13]), + .I2(\core.csr_u.mepc_in [13]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_19_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_19_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [12]), + .I2(\core.csr_u.mepc_in [12]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [30]), + .I2(\core.csr_u.mepc_in [30]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_2_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_20_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_20_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [11]), + .I2(\core.csr_u.mepc_in [11]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_21_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_21_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [10]), + .I2(\core.csr_u.mepc_in [10]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_22_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_22_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [9]), + .I2(\core.csr_u.mepc_in [9]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_23_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_23_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [8]), + .I2(\core.csr_u.mepc_in [8]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_24_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_24_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [7]), + .I2(\core.csr_u.mepc_in [7]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_25_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_25_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [6]), + .I2(\core.csr_u.wdata_update [6]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_26_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_26_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [5]), + .I2(\core.csr_u.wdata_update [5]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_27_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_27_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [4]), + .I2(\core.csr_u.wdata_update [4]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_28_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_28_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [3]), + .I2(\core.csr_u.wdata_update [3]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_29_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_29_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [2]), + .I2(\core.csr_u.wdata_update [2]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [29]), + .I2(\core.csr_u.wdata_update [29]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_3_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [28]), + .I2(\core.csr_u.mepc_in [28]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_4_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [27]), + .I2(\core.csr_u.wdata_update [27]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_5_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [26]), + .I2(\core.csr_u.wdata_update [26]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_6_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [25]), + .I2(\core.csr_u.wdata_update [25]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_7_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mepc_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc_in [24]), + .I2(\core.csr_u.wdata_update [24]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_8_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [23]), + .I2(\core.csr_u.mepc_in [23]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:265.1-275.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mepc_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.csr_u.mepc_SB_DFFER_Q_9_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ), + .Q(\core.csr_u.mepc [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.csr_u.mepc_SB_DFFER_Q_9_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [22]), + .I2(\core.csr_u.mepc_in [22]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mepc_SB_DFFER_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca3a) + ) \core.csr_u.mepc_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [31]), + .I1(\core.decode_u.pc [31]), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [30]), + .O(\core.csr_u.mepc_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc [10]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [9]), + .O(\core.csr_u.mepc_in [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.decode_u.pc [9]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [8]), + .O(\core.csr_u.mepc_in [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.decode_u.pc [28]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [27]), + .O(\core.csr_u.mepc_in [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.decode_u.pc [27]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [26]), + .O(\core.csr_u.mepc_in [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.decode_u.pc [26]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [25]), + .O(\core.csr_u.mepc_in [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.decode_u.pc [25]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [24]), + .O(\core.csr_u.mepc_in [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.decode_u.pc [24]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [23]), + .O(\core.csr_u.mepc_in [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.decode_u.pc [23]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [22]), + .O(\core.csr_u.mepc_in [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.decode_u.pc [22]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [21]), + .O(\core.csr_u.mepc_in [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.decode_u.pc [21]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [20]), + .O(\core.csr_u.mepc_in [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.decode_u.pc [2]), + .I2(\core.prev_instr_was_32_bit_SB_LUT4_I3_O [1]), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [1]), + .O(\core.csr_u.mepc_in [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.decode_u.pc [20]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [19]), + .O(\core.csr_u.mepc_in [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.decode_u.pc [8]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [7]), + .O(\core.csr_u.mepc_in [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.decode_u.pc [19]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [18]), + .O(\core.csr_u.mepc_in [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.decode_u.pc [18]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [17]), + .O(\core.csr_u.mepc_in [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.decode_u.pc [17]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [16]), + .O(\core.csr_u.mepc_in [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.decode_u.pc [16]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [15]), + .O(\core.csr_u.mepc_in [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.decode_u.pc [15]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [14]), + .O(\core.csr_u.mepc_in [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.decode_u.pc [14]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [13]), + .O(\core.csr_u.mepc_in [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.decode_u.pc [13]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [12]), + .O(\core.csr_u.mepc_in [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.decode_u.pc [12]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [11]), + .O(\core.csr_u.mepc_in [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.decode_u.pc [11]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [10]), + .O(\core.csr_u.mepc_in [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.decode_u.pc [7]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [6]), + .O(\core.csr_u.mepc_in [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.decode_u.pc [6]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [5]), + .O(\core.csr_u.mepc_in [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.decode_u.pc [5]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [4]), + .O(\core.csr_u.mepc_in [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.decode_u.pc [4]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [3]), + .O(\core.csr_u.mepc_in [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.decode_u.pc [3]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [2]), + .O(\core.csr_u.mepc_in [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.decode_u.pc [30]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [29]), + .O(\core.csr_u.mepc_in [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.csr_u.mepc_in_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.decode_u.pc [29]), + .I2(1'h1), + .I3(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [28]), + .O(\core.csr_u.mepc_in [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:283.1-297.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mie_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.wdata_update [11]), + .E(\core.csr_u.mie_SB_DFFER_Q_E [0]), + .Q(\core.csr_u.mie [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:283.1-297.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mie_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.mie_SB_DFFER_Q_1_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_2_E ), + .Q(\core.csr_u.mie [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0b) + ) \core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [3]), + .I1(\core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .I3(\core.csr_u.mie_SB_DFFER_Q_E [0]), + .O(\core.csr_u.mie_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update [7]), + .I2(\core.csr_u.mie [7]), + .I3(\core.csr_u.mie_SB_DFFER_Q_E [0]), + .O(\core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:283.1-297.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mie_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.mie_SB_DFFER_Q_2_D ), + .E(\core.csr_u.mie_SB_DFFER_Q_2_E ), + .Q(\core.csr_u.mie [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf011) + ) \core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(\core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update [3]), + .I3(\core.csr_u.mie_SB_DFFER_Q_E [0]), + .O(\core.csr_u.mie_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [2]), + .O(\core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000d) + ) \core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.mie [3]), + .O(\core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) \core.csr_u.mie_SB_DFFER_Q_2_E_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .O(\core.csr_u.mie_SB_DFFER_Q_2_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mie_SB_DFFER_Q_E [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffc0) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I1_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .O(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_1_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .O(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .O(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .O(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.wdata_update [31]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.wdata_update [30]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.csr_u.wdata_update [21]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.csr_u.wdata_update [20]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.csr_u.wdata_update [19]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.csr_u.wdata_update [18]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.csr_u.wdata_update [17]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.csr_u.wdata_update [16]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.csr_u.wdata_update [15]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.csr_u.wdata_update [14]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.csr_u.wdata_update [13]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.csr_u.wdata_update [12]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.wdata_update [29]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.csr_u.wdata_update [11]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.csr_u.wdata_update [10]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.csr_u.wdata_update [9]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.csr_u.wdata_update [8]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.csr_u.wdata_update [7]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.csr_u.wdata_update [6]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.csr_u.wdata_update [5]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.csr_u.wdata_update [4]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.csr_u.wdata_update [3]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.csr_u.wdata_update [2]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.csr_u.wdata_update [28]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_30 ( + .C(clk), + .D(\core.csr_u.wdata_update [1]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_31 ( + .C(clk), + .D(\core.csr_u.wdata_update [0]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.csr_u.wdata_update [27]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.csr_u.wdata_update [26]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.csr_u.wdata_update [25]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.csr_u.wdata_update [24]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.csr_u.wdata_update [23]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:237.1-244.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mscratch_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.csr_u.wdata_update [22]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_3_O ), + .Q(\core.csr_u.mscratch [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:186.1-227.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mstatus_mie_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.mstatus_mie_SB_DFFER_Q_D ), + .E(\core.csr_u.mstatus_mie_SB_DFFER_Q_E ), + .Q(\core.csr_u.mstatus_mie ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) \core.csr_u.mstatus_mie_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mprv_SB_DFFER_Q_E [0]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.csr_u.mstatus_mie_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [0]), + .I2(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [1]), + .I3(\core.csr_u.mstatus_mie ), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.mcause_code [3]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.mstatus_mie ), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [20]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3 [1]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [20]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I3(\core.frontend.cir [21]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [22]), + .I3(\core.frontend.cir [23]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf800) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_I3 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I1(\core.frontend.cir [20]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3 [1]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [2]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [1]), + .I2(\core.frontend.cir [30]), + .I3(\core.frontend.cir [31]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2 ( + .I0(\core.frontend.cir [24]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_I1 [1]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [2]), + .I3(\core.frontend.cir [26]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_I1_SB_LUT4_O ( + .I0(\core.frontend.cir [30]), + .I1(\core.frontend.cir [27]), + .I2(\core.frontend.cir [25]), + .I3(\core.frontend.cir [31]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf088) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [1]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [2]), + .I3(\core.frontend.cir [20]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.frontend.cir [30]), + .I2(\core.frontend.cir [31]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [2]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.frontend.cir [27]), + .I1(\core.frontend.cir [25]), + .I2(\core.frontend.cir [24]), + .I3(\core.frontend.cir [26]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.cir [20]), + .I2(\core.frontend.cir [21]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [29]), + .I3(\core.frontend.cir [28]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [27]), + .I1(\core.frontend.cir [25]), + .I2(\core.frontend.cir [26]), + .I3(\core.frontend.cir [24]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [2]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.csr_u.mstatus_mie_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.xm_except [3]), + .I1(\core.xm_except [2]), + .I2(\core.xm_except [1]), + .I3(\core.xm_except [0]), + .O(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:186.1-227.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mstatus_mpie_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.mstatus_mpie_SB_DFFER_Q_D ), + .E(\core.csr_u.mstatus_mie_SB_DFFER_Q_E ), + .Q(\core.csr_u.mstatus_mpie ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'heef0) + ) \core.csr_u.mstatus_mpie_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I1(\core.csr_u.mstatus_mie ), + .I2(\core.csr_u.wdata_update [7]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.csr_u.mstatus_mpie_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h88f0) + ) \core.csr_u.mstatus_mpie_SB_LUT4_I1 ( + .I0(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I1(\core.csr_u.mstatus_mpie ), + .I2(\core.csr_u.wdata_update [3]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.csr_u.mstatus_mie_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mstatus_mpie_SB_LUT4_I3 ( + .I0(\core.csr_u.mtvec_reg [7]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.mstatus_mpie ), + .O(\core.csr_u.irq_timer_r_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:186.1-227.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mstatus_mprv_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.wdata_update [17]), + .E(\core.csr_u.mstatus_mprv_SB_DFFER_Q_E [0]), + .Q(\core.csr_u.mstatus_mprv ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mprv_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .O(\core.csr_u.mstatus_mprv_SB_DFFER_Q_E [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [17]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.mstatus_mprv ), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2 ( + .I0(\core.csr_u.mtvec_reg [17]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O [3]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0 ( + .I0(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I3(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [17]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [3]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [17]), + .I1(\core.alu.op_b_inv [17]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h53ff) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.csr_u.meiea [17]), + .I1(\core.csr_u.meiea [1]), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [17]), + .I2(\core.csr_u.irq_r [1]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa [17]), + .I2(\core.csr_u.meifa [1]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [17]), + .O(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q ( + .C(clk), + .D(\core.csr_u.wdata_update [31]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.csr_u.wdata_update [30]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.csr_u.wdata_update [21]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.csr_u.wdata_update [20]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.csr_u.wdata_update [19]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.csr_u.wdata_update [18]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.csr_u.wdata_update [17]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.csr_u.wdata_update [16]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.csr_u.wdata_update [15]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.csr_u.wdata_update [14]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.csr_u.wdata_update [13]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.csr_u.wdata_update [12]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.csr_u.wdata_update [29]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.csr_u.wdata_update [11]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.csr_u.wdata_update [10]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.csr_u.wdata_update [9]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.csr_u.wdata_update [8]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.csr_u.wdata_update [7]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.csr_u.wdata_update [6]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.csr_u.wdata_update [5]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.csr_u.wdata_update [4]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.csr_u.wdata_update [3]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.csr_u.wdata_update [2]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.csr_u.wdata_update [28]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.csr_u.wdata_update [27]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.csr_u.wdata_update [26]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.csr_u.wdata_update [25]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.csr_u.wdata_update [24]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.csr_u.wdata_update [23]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_csr.v:251.1-258.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:949.3-1021.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.csr_u.mtvec_reg_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.csr_u.wdata_update [22]), + .E(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_2_O ), + .Q(\core.csr_u.mtvec_reg [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O ( + .I0(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[31]), + .O(\core.csr_u.wdata_update [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_1 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[30]), + .O(\core.csr_u.wdata_update [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_10 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[21]), + .O(\core.csr_u.wdata_update [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [21]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [21]), + .I1(\core.alu.op_b_inv [21]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_2 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h53ff) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.meiea [21]), + .I1(\core.csr_u.meiea [5]), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.mscratch [21]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [21]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [21]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [21]), + .I2(\core.csr_u.irq_r [5]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa [21]), + .I2(\core.csr_u.meifa [5]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_11 ( + .I0(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[20]), + .O(\core.csr_u.wdata_update [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_12 ( + .I0(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[19]), + .O(\core.csr_u.wdata_update [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_13 ( + .I0(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[18]), + .O(\core.csr_u.wdata_update [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_14 ( + .I0(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[17]), + .O(\core.csr_u.wdata_update [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_15 ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[16]), + .O(\core.csr_u.wdata_update [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_16 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_16_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[15]), + .O(\core.csr_u.wdata_update [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_16_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mscratch [15]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.meicontext_noirq_SB_LUT4_I1_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_16_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_17 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_17_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[14]), + .O(\core.csr_u.wdata_update [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_17_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [14]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_17_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_17_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_17_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [14]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [14]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_17_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_18 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_18_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[13]), + .O(\core.csr_u.wdata_update [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_18_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [13]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_18_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_18_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_18_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [13]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [13]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_18_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_19 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_19_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[12]), + .O(\core.csr_u.wdata_update [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_19_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [12]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [12]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.csr_u.meicontext_irq [8]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [12]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [30]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [30]), + .I1(\core.alu.op_b_inv [30]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_2 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_2_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[29]), + .O(\core.csr_u.wdata_update [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_20 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_20_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[11]), + .O(\core.csr_u.wdata_update [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_21 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_21_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[10]), + .O(\core.csr_u.wdata_update [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2 [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_21_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.csr_u.meicontext_irq [6]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [10]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [10]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [10]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_21_I0_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_22 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_22_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[9]), + .O(\core.csr_u.wdata_update [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2 [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_22_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.csr_u.meicontext_irq [5]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [9]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [9]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [9]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_22_I0_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_23 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_23_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[8]), + .O(\core.csr_u.wdata_update [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O ( + .I0(\core.csr_u.mepc [8]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.csr_u.mscratch [8]), + .I1(\core.csr_u.meicontext_mreteirq_SB_LUT4_I3_I0 [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.meicontext_irq [4]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [8]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2 ( + .I0(\core.csr_u.mepc [30]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_I3 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1 ( + .I0(\core.csr_u.mepc [23]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_I3 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [23]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [23]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h53ff) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_1 ( + .I0(\core.csr_u.meiea [23]), + .I1(\core.csr_u.meiea [7]), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_2 ( + .I0(dbg_data0_wdata[1]), + .I1(dbg_data0_wdata[3]), + .I2(dbg_data0_wdata[2]), + .I3(dbg_data0_wdata[4]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hee0f) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(\core.csr_u.irq_r [23]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0]), + .I3(\core.csr_u.meiea [7]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [8]), + .I2(\core.csr_u.meifa [8]), + .I3(\core.csr_u.meiea [8]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [9]), + .I2(\core.csr_u.meifa [9]), + .I3(\core.csr_u.meiea [9]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O_SB_LUT4_O_2 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa [7]), + .I3(\core.csr_u.irq_r [7]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.frontend.cir [21]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I2(\core.frontend.cir [20]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa [23]), + .I2(\core.csr_u.meifa [7]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [30]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [30]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0b00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_I0 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.csr_u.meifa [14]), + .I1(\core.csr_u.irq_r [14]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [30]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [30]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [30]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meifa [14]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meiea [14]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [21]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I2(\core.frontend.cir [20]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_24 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_24_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[7]), + .O(\core.csr_u.wdata_update [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O ( + .I0(\core.csr_u.meicontext_irq [3]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_24_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [7]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mie [7]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_25 ( + .I0(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[6]), + .O(\core.csr_u.wdata_update [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_26 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_26_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[5]), + .O(\core.csr_u.wdata_update [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0b00) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [0]), + .I1(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mepc [5]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [5]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.csr_u.meicontext_irq [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mscratch [5]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_27 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_27_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[4]), + .O(\core.csr_u.wdata_update [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [1]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 [0]), + .I3(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.mtvec_reg [4]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_irq [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [4]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [4]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_28 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_28_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[1]), + .O(\core.csr_u.wdata_update [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_28_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mscratch [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_28_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_28_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.csr_u.wdata_update_SB_LUT4_O_28_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mcause_code [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_28_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff30) + ) \core.csr_u.wdata_update_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.csr_u.wdata_update [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(\core.csr_u.mepc [29]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [29]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [29]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [29]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [29]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [29]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I3(\core.csr_u.meiea [13]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I0 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [3]), + .O(\core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [14]), + .I2(\core.csr_u.meifa [14]), + .I3(\core.csr_u.meiea [14]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [0]), + .I3(\core.csr_u.meiea [15]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3500) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1 [0]), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1 [0]), + .I3(\core.csr_u.meiea [31]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [1]), + .O(\core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [30]), + .I2(\core.csr_u.meifa [30]), + .I3(\core.csr_u.meiea [30]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa [31]), + .I3(\core.csr_u.irq_r [31]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa [15]), + .I3(\core.csr_u.irq_r [15]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_2 ( + .I0(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa [13]), + .I3(\core.csr_u.irq_r [13]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meifa [13]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meiea [13]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_3 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_3_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[28]), + .O(\core.csr_u.wdata_update [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_30 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_30_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[3]), + .O(\core.csr_u.wdata_update [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O ( + .I0(\core.csr_u.mie [7]), + .I1(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(\core.csr_u.mie [3]), + .I1(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mscratch [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mcause_code [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(dbg_data0_wdata[2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .I2(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [1]), + .I3(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_31 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_31_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[0]), + .O(\core.csr_u.wdata_update [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.wdata_update_SB_LUT4_O_31_I0_SB_LUT4_O ( + .I0(\core.csr_u.mcause_code [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_31_I0_SB_LUT4_O_I3 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_31_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.mepc [28]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2 [3]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [28]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [28]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3500) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0 [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0 [1]), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [28]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meiea [12]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [12]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [12]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [28]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [28]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [28]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6dc4) + ) \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv [28]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.op_a [28]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_4 ( + .I0(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[27]), + .O(\core.csr_u.wdata_update [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_5 ( + .I0(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[26]), + .O(\core.csr_u.wdata_update [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_6 ( + .I0(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[25]), + .O(\core.csr_u.wdata_update [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_7 ( + .I0(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[24]), + .O(\core.csr_u.wdata_update [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_8 ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[23]), + .O(\core.csr_u.wdata_update [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.csr_u.wdata_update_SB_LUT4_O_9 ( + .I0(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(dbg_data0_wdata[22]), + .O(\core.csr_u.wdata_update [22]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [4]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [5]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [4]), + .I1(\core.d_addr_offs [4]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_1 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [3]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [4]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I1(\core.d_addr_offs [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_10 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [13]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [14]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [13]), + .I1(\core.d_addr_offs [13]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_11 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [12]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [13]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [12]), + .I1(\core.d_addr_offs [12]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_12 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [11]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [12]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [11]), + .I1(\core.d_addr_offs [11]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_13 ( + .CI(1'h0), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [1]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I1(\core.d_addr_offs [0]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_2 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [2]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [3]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I1(\core.d_addr_offs [2]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_3 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [1]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [2]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I1(\core.d_addr_offs [1]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_4 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [19]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [20]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [19]), + .I1(\core.d_addr_offs [19]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_5 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [18]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [19]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [18]), + .I1(\core.d_addr_offs [18]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_6 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [17]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [18]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [17]), + .I1(\core.d_addr_offs [17]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_7 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [16]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [17]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [16]), + .I1(\core.d_addr_offs [16]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_8 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [15]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [16]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [15]), + .I1(\core.d_addr_offs [15]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_9 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [14]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [15]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [14]), + .I1(\core.d_addr_offs [14]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [9]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [10]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [9]), + .I1(\core.frontend.cir [29]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_1 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [8]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [9]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [8]), + .I1(\core.frontend.cir [28]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_10 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [25]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [26]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [25]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_11 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [24]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [25]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [24]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_12 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [23]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [24]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [23]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_13 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [22]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [23]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [22]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_14 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [21]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [22]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [21]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_15 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [20]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [21]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [20]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_16 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [10]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [11]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [10]), + .I1(\core.frontend.cir [30]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_2 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [7]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [8]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [7]), + .I1(\core.frontend.cir [27]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_3 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [6]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [7]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [6]), + .I1(\core.frontend.cir [26]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_4 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [5]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [6]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [5]), + .I1(\core.frontend.cir [25]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_5 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [30]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [31]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [30]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_6 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [29]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [30]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [29]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_7 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [28]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [29]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [28]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_8 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [27]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [28]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [27]), + .I1(\core.frontend.cir [31]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.d_addr_offs_SB_CARRY_I1_CO_SB_CARRY_CO_9 ( + .CI(\core.d_addr_offs_SB_CARRY_I1_CO [26]), + .CO(\core.d_addr_offs_SB_CARRY_I1_CO [27]), + .I0(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [26]), + .I1(\core.frontend.cir [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [19]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [18]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.frontend.cir [23]), + .I2(\core.frontend.cir [10]), + .I3(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .O(\core.d_addr_offs [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.frontend.cir [22]), + .I2(\core.frontend.cir [9]), + .I3(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .O(\core.d_addr_offs [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.frontend.cir [21]), + .I2(\core.frontend.cir [8]), + .I3(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .O(\core.d_addr_offs [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff30) + ) \core.d_addr_offs_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.d_addr_offs_SB_LUT4_O_13_I1 [0]), + .I2(\core.frontend.cir [20]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1 [2]), + .O(\core.d_addr_offs [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1 [0]), + .O(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [6]), + .I2(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .I3(\core.frontend.cir [7]), + .O(\core.d_addr_offs_SB_LUT4_O_13_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf3f5) + ) \core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [1]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I2(\core.frontend.cir [3]), + .I3(\core.frontend.cir [2]), + .O(\core.d_addr_offs_SB_LUT4_O_13_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [17]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [16]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [15]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [14]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [13]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.frontend.cir [12]), + .I3(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .O(\core.d_addr_offs [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc0ff) + ) \core.d_addr_offs_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2]), + .I2(\core.frontend.cir [20]), + .I3(\core.d_addr_offs_SB_LUT4_O_8_I3 [2]), + .O(\core.d_addr_offs [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h007f) + ) \core.d_addr_offs_SB_LUT4_O_8_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [7]), + .I1(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .I2(\core.frontend.cir [6]), + .I3(\core.d_addr_offs_SB_LUT4_O_8_I3_SB_LUT4_O_I3 [3]), + .O(\core.d_addr_offs_SB_LUT4_O_8_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4f00) + ) \core.d_addr_offs_SB_LUT4_O_8_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [6]), + .I1(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .I2(\core.d_addr_offs_SB_LUT4_O_13_I1 [0]), + .I3(\core.frontend.cir [31]), + .O(\core.d_addr_offs_SB_LUT4_O_8_I3_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_addr_offs_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.frontend.cir [24]), + .I2(\core.frontend.cir [11]), + .I3(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]), + .O(\core.d_addr_offs [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.d_addr_offs_SB_LUT4_O_9_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [2]), + .I2(\core.frontend.cir [3]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]), + .O(\core.d_addr_offs_SB_LUT4_O_9_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs1_predecoded_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.next_instr [19]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs1_predecoded [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs1_predecoded_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.next_instr [18]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs1_predecoded [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs1_predecoded_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.frontend.next_instr [17]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs1_predecoded [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs1_predecoded_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.frontend.next_instr [16]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs1_predecoded [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs1_predecoded_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.frontend.next_instr [15]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs1_predecoded [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.d_rs1_predecoded_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.d_rs1_predecoded [2]), + .I2(\core.d_rs1_predecoded [3]), + .I3(\core.d_rs1_predecoded [4]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.d_rs1_predecoded_SB_LUT4_I1_1 ( + .I0(1'h0), + .I1(\core.d_rs1_predecoded [0]), + .I2(\core.d_rs1_predecoded [1]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_O [2]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs1_predecoded_SB_LUT4_I1_2 ( + .I0(\core.xm_rd [0]), + .I1(\core.d_rs1_predecoded [0]), + .I2(\core.xm_rd [1]), + .I3(\core.d_rs1_predecoded [1]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs1_predecoded_SB_LUT4_I1_3 ( + .I0(\core.xm_rd [2]), + .I1(\core.d_rs1_predecoded [2]), + .I2(\core.xm_rd [4]), + .I3(\core.d_rs1_predecoded [4]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9000) + ) \core.d_rs1_predecoded_SB_LUT4_I1_4 ( + .I0(\core.xm_rd [3]), + .I1(\core.d_rs1_predecoded [3]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_3_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_3_O [3]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_rs1_predecoded_SB_LUT4_I1_4_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [31]), + .I2(\core.mw_result [31]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs1_predecoded_SB_LUT4_I1_5 ( + .I0(\core.mw_rd [0]), + .I1(\core.d_rs1_predecoded [0]), + .I2(\core.mw_rd [2]), + .I3(\core.d_rs1_predecoded [2]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_6_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs1_predecoded_SB_LUT4_I1_6 ( + .I0(\core.mw_rd [1]), + .I1(\core.d_rs1_predecoded [1]), + .I2(\core.mw_rd [4]), + .I3(\core.d_rs1_predecoded [4]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_6_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9000) + ) \core.d_rs1_predecoded_SB_LUT4_I1_7 ( + .I0(\core.mw_rd [3]), + .I1(\core.d_rs1_predecoded [3]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_6_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_6_O [3]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_rs1_predecoded_SB_LUT4_I1_7_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.regs.rdata1 [23]), + .I2(\core.mw_result [23]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.d_rs1_predecoded_SB_LUT4_I1_7_O_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.d_rs2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [23]), + .O(\core.d_rs2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.d_rs2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [21]), + .O(\core.d_rs2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.d_rs2_SB_LUT4_O_2 ( + .I0(\core.d_rs2_SB_LUT4_O_4_I0 [0]), + .I1(\core.d_rs2_SB_LUT4_O_4_I0 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.d_rs2_SB_LUT4_O_2_I3 [3]), + .O(\core.d_rs2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.d_rs2_SB_LUT4_O_2_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I3(\core.frontend.cir [22]), + .O(\core.d_rs2_SB_LUT4_O_2_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.d_rs2_SB_LUT4_O_3 ( + .I0(\core.d_rs2_SB_LUT4_O_4_I0 [0]), + .I1(\core.d_rs2_SB_LUT4_O_4_I0 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.d_rs2_SB_LUT4_O_3_I3 [3]), + .O(\core.d_rs2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.d_rs2_SB_LUT4_O_3_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I3(\core.frontend.cir [20]), + .O(\core.d_rs2_SB_LUT4_O_3_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.d_rs2_SB_LUT4_O_4 ( + .I0(\core.d_rs2_SB_LUT4_O_4_I0 [0]), + .I1(\core.d_rs2_SB_LUT4_O_4_I0 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.d_rs2_SB_LUT4_O_4_I3 [3]), + .O(\core.d_rs2 [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.d_rs2_SB_LUT4_O_4_I0_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [3]), + .O(\core.d_rs2_SB_LUT4_O_4_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.d_rs2_SB_LUT4_O_4_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I3(\core.frontend.cir [24]), + .O(\core.d_rs2_SB_LUT4_O_4_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h807f) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0 ( + .I0(\core.d_rs2_SB_LUT4_O_I1 [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [21]), + .I3(\core.xm_rd [1]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h807f) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_1 ( + .I0(\core.d_rs2_SB_LUT4_O_I1 [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [23]), + .I3(\core.xm_rd [3]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.d_rs2 [0]), + .I1(\core.xm_rd [0]), + .I2(\core.d_rs2 [2]), + .I3(\core.xm_rd [2]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb00b) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [0]), + .I1(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [1]), + .I2(\core.d_rs2 [4]), + .I3(\core.xm_rd [4]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]), + .O(\core.d_rs2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3 [1]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [2]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [0]), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [2]), + .I3(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [3]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs2_predecoded_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.next_instr [24]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs2_predecoded [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs2_predecoded_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.next_instr [23]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs2_predecoded [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs2_predecoded_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.frontend.next_instr [22]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs2_predecoded [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs2_predecoded_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.frontend.next_instr [21]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs2_predecoded [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:417.1-425.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.d_rs2_predecoded_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.frontend.next_instr [20]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .Q(\core.d_rs2_predecoded [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.d_rs2_predecoded_SB_LUT4_I0 ( + .I0(\core.d_rs2_predecoded [0]), + .I1(\core.d_rs2_predecoded [1]), + .I2(\core.d_rs2_predecoded [2]), + .I3(\core.d_rs2_predecoded [4]), + .O(\core.d_rs2_predecoded_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs2_predecoded_SB_LUT4_I1 ( + .I0(\core.xm_rd [3]), + .I1(\core.d_rs2_predecoded [3]), + .I2(\core.xm_rd [4]), + .I3(\core.d_rs2_predecoded [4]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs2_predecoded_SB_LUT4_I1_1 ( + .I0(\core.xm_rd [0]), + .I1(\core.d_rs2_predecoded [0]), + .I2(\core.xm_rd [1]), + .I3(\core.d_rs2_predecoded [1]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9000) + ) \core.d_rs2_predecoded_SB_LUT4_I1_2 ( + .I0(\core.xm_rd [2]), + .I1(\core.d_rs2_predecoded [2]), + .I2(\core.d_rs2_predecoded_SB_LUT4_I1_O [2]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_O [3]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.d_rs2_predecoded_SB_LUT4_I1_2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [31]), + .I2(\core.mw_result [31]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs2_predecoded_SB_LUT4_I1_3 ( + .I0(\core.mw_rd [0]), + .I1(\core.d_rs2_predecoded [0]), + .I2(\core.mw_rd [3]), + .I3(\core.d_rs2_predecoded [3]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_4_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.d_rs2_predecoded_SB_LUT4_I1_4 ( + .I0(\core.mw_rd [1]), + .I1(\core.d_rs2_predecoded [1]), + .I2(\core.mw_rd [4]), + .I3(\core.d_rs2_predecoded [4]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_4_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9000) + ) \core.d_rs2_predecoded_SB_LUT4_I1_5 ( + .I0(\core.mw_rd [2]), + .I1(\core.d_rs2_predecoded [2]), + .I2(\core.d_rs2_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.d_rs2_predecoded_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.d_rs2_predecoded [3]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I0_O [1]), + .O(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f4) + ) \core.decode_u.cir_lock_SB_LUT4_O ( + .I0(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I2(\core.decode_u.cir_lock_prev ), + .I3(\core.df_cir_use [1]), + .O(\core.decode_u.cir_lock ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:123.1-129.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.decode_u.cir_lock_prev_SB_DFFR_Q ( + .C(clk), + .D(\core.decode_u.cir_lock ), + .Q(\core.decode_u.cir_lock_prev ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.decode_u.cir_lock_prev ), + .I2(bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hac00) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [2]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [3]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f44) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [1]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I3 [3]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [0]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [2]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [31]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [1]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [6]), + .I2(\core.frontend.cir [12]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .I3(\core.frontend.cir [14]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.frontend.cir [12]), + .I2(\core.frontend.cir [15]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [14]), + .I3(\core.frontend.cir [13]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .I3(\core.frontend.cir [12]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [1]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [2]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [3]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffc0) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.df_cir_use [1]), + .I2(\core.decode_u.cir_lock_prev ), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [0]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [0]), + .I3(\core.df_cir_use [1]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.df_cir_use [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.decode_u.f_jump_target_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I3(\core.x_jump_misaligned ), + .O(\core.decode_u.f_jump_target [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.x_addr_sum [31]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.x_addr_sum [22]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_10_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_10_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [22]), + .I2(\core.csr_u.mepc [22]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_10_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.x_addr_sum [21]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_11_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_11_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [21]), + .I2(\core.csr_u.mepc [21]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_11_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.x_addr_sum [20]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_12_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_12_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [20]), + .I2(\core.csr_u.mepc [20]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_12_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.x_addr_sum [19]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_13_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_13_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [19]), + .I2(\core.csr_u.mepc [19]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_13_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.x_addr_sum [18]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_14_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_14_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [18]), + .I2(\core.csr_u.mepc [18]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_14_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.x_addr_sum [17]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_15_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_15_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [17]), + .I2(\core.csr_u.mepc [17]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_15_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.x_addr_sum [16]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_16_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_16_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [16]), + .I2(\core.csr_u.mepc [16]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_16_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.x_addr_sum [15]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_17_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_17_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [15]), + .I2(\core.csr_u.mepc [15]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_17_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.x_addr_sum [14]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_18_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_18_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [14]), + .I2(\core.csr_u.mepc [14]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_18_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.x_addr_sum [13]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_19_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_19_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [13]), + .I2(\core.csr_u.mepc [13]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_19_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [31]), + .I2(\core.csr_u.mepc [31]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.x_addr_sum [30]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_2_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.x_addr_sum [12]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_20_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_20_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [12]), + .I2(\core.csr_u.mepc [12]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_20_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.x_addr_sum [11]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_21_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_21_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [11]), + .I2(\core.csr_u.mepc [11]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_21_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.x_addr_sum [10]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_22_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_22_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [10]), + .I2(\core.csr_u.mepc [10]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_22_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.x_addr_sum [9]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_23_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_23_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [9]), + .I2(\core.csr_u.mepc [9]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_23_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.x_addr_sum [8]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_24_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_24_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [8]), + .I2(\core.csr_u.mepc [8]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_24_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.x_addr_sum [7]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_25_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_25_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [7]), + .I2(\core.csr_u.mepc [7]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_25_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.x_addr_sum [6]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_26_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_26_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [6]), + .I2(\core.csr_u.mepc [6]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_26_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h11f0) + ) \core.decode_u.f_jump_target_SB_LUT4_O_27 ( + .I0(\core.decode_u.f_jump_target_SB_LUT4_O_27_I0 [0]), + .I1(\core.decode_u.f_jump_target_SB_LUT4_O_27_I0 [1]), + .I2(\core.x_addr_sum [5]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.decode_u.f_jump_target_SB_LUT4_O_27_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mepc [5]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_27_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0007) + ) \core.decode_u.f_jump_target_SB_LUT4_O_27_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.irq_vector_enable ), + .I1(\core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2 [0]), + .I2(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I3(\core.csr_u.mtvec_reg [5]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_27_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.x_addr_sum [4]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_28_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0ee) + ) \core.decode_u.f_jump_target_SB_LUT4_O_28_I2_SB_LUT4_O ( + .I0(\core.decode_u.f_jump_target_SB_LUT4_O_28_I2_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.mtvec_reg [4]), + .I2(\core.csr_u.mepc [4]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_28_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.decode_u.f_jump_target_SB_LUT4_O_28_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.irq_vector_enable ), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_28_I2_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.x_addr_sum [3]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_29_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0ee) + ) \core.decode_u.f_jump_target_SB_LUT4_O_29_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [3]), + .I2(\core.csr_u.mepc [3]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_29_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_2_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [30]), + .I2(\core.csr_u.mepc [30]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_2_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.x_addr_sum [29]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_3_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(\core.x_addr_sum [2]), + .I2(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_3_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [29]), + .I2(\core.csr_u.mepc [29]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_3_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.x_addr_sum [28]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_4_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_4_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [28]), + .I2(\core.csr_u.mepc [28]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_4_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.x_addr_sum [27]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_5_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_5_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [27]), + .I2(\core.csr_u.mepc [27]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_5_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.x_addr_sum [26]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_6_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_6_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [26]), + .I2(\core.csr_u.mepc [26]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_6_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.x_addr_sum [25]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_7_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_7_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [25]), + .I2(\core.csr_u.mepc [25]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_7_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.x_addr_sum [24]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_8_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_8_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [24]), + .I2(\core.csr_u.mepc [24]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_8_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.decode_u.f_jump_target_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.x_addr_sum [23]), + .I2(\core.decode_u.f_jump_target_SB_LUT4_O_9_I2 [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.decode_u.f_jump_target [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.decode_u.f_jump_target_SB_LUT4_O_9_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [23]), + .I2(\core.csr_u.mepc [23]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.decode_u.f_jump_target_SB_LUT4_O_9_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q ( + .C(clk), + .D(\core.decode_u.f_jump_target [1]), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .Q(\core.decode_u.pc [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_1_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_10_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_10_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [22]), + .I2(\core.decode_u.f_jump_target [22]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_11_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_11_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [21]), + .I2(\core.decode_u.f_jump_target [21]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_12_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_12_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [20]), + .I2(\core.decode_u.f_jump_target [20]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_13_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_13_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [19]), + .I2(\core.decode_u.f_jump_target [19]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_14_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_14_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [18]), + .I2(\core.decode_u.f_jump_target [18]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_15_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_15_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [17]), + .I2(\core.decode_u.f_jump_target [17]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_16_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_16_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [16]), + .I2(\core.decode_u.f_jump_target [16]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_17_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_17_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [15]), + .I2(\core.decode_u.f_jump_target [15]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_18_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_18_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [14]), + .I2(\core.decode_u.f_jump_target [14]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_19_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_19_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [13]), + .I2(\core.decode_u.f_jump_target [13]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8bb8) + ) \core.decode_u.pc_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(\core.decode_u.f_jump_target [31]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .I2(\core.decode_u.pc [31]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [29]), + .O(\core.decode_u.pc_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_2_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_20_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_20_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [12]), + .I2(\core.decode_u.f_jump_target [12]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_21_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_21_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [11]), + .I2(\core.decode_u.f_jump_target [11]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_22_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_22_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [10]), + .I2(\core.decode_u.f_jump_target [10]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_23_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_23_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [9]), + .I2(\core.decode_u.f_jump_target [9]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_24_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_24_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [8]), + .I2(\core.decode_u.f_jump_target [8]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_25_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_25_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [7]), + .I2(\core.decode_u.f_jump_target [7]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_26_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_26_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [6]), + .I2(\core.decode_u.f_jump_target [6]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_27_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_27_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [5]), + .I2(\core.decode_u.f_jump_target [5]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_28_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_28_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [4]), + .I2(\core.decode_u.f_jump_target [4]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_29_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_29_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [3]), + .I2(\core.decode_u.f_jump_target [3]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [30]), + .I2(\core.decode_u.f_jump_target [30]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_3_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_30 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_30_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.decode_u.pc_SB_DFFER_Q_30_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc [2]), + .I2(\core.decode_u.f_jump_target [2]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_30_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [29]), + .I2(\core.decode_u.f_jump_target [29]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_4_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [28]), + .I2(\core.decode_u.f_jump_target [28]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_5_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [27]), + .I2(\core.decode_u.f_jump_target [27]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_6_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [26]), + .I2(\core.decode_u.f_jump_target [26]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_7_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [25]), + .I2(\core.decode_u.f_jump_target [25]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_8_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [24]), + .I2(\core.decode_u.f_jump_target [24]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:145.1-158.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.decode_u.pc_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.decode_u.pc_SB_DFFER_Q_9_D ), + .E(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3_SB_LUT4_I2_O ), + .Q(\core.decode_u.pc [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.decode_u.pc_SB_DFFER_Q_9_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.pc_seq_next [23]), + .I2(\core.decode_u.f_jump_target [23]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_O [2]), + .O(\core.decode_u.pc_SB_DFFER_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [11]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [9]), + .O(\core.decode_u.pc_seq_next [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [10]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [8]), + .O(\core.decode_u.pc_seq_next [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [28]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [26]), + .O(\core.decode_u.pc_seq_next [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [27]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [25]), + .O(\core.decode_u.pc_seq_next [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [26]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [24]), + .O(\core.decode_u.pc_seq_next [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [25]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [23]), + .O(\core.decode_u.pc_seq_next [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [24]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [22]), + .O(\core.decode_u.pc_seq_next [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [23]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [21]), + .O(\core.decode_u.pc_seq_next [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [22]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [20]), + .O(\core.decode_u.pc_seq_next [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [3]), + .I3(\core.decode_u.pc [2]), + .O(\core.decode_u.pc_seq_next [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [21]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [19]), + .O(\core.decode_u.pc_seq_next [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [20]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [18]), + .O(\core.decode_u.pc_seq_next [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [9]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [7]), + .O(\core.decode_u.pc_seq_next [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [19]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [17]), + .O(\core.decode_u.pc_seq_next [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [18]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [16]), + .O(\core.decode_u.pc_seq_next [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [17]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [15]), + .O(\core.decode_u.pc_seq_next [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [16]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [14]), + .O(\core.decode_u.pc_seq_next [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [15]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [13]), + .O(\core.decode_u.pc_seq_next [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [14]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [12]), + .O(\core.decode_u.pc_seq_next [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [13]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [11]), + .O(\core.decode_u.pc_seq_next [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [12]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [10]), + .O(\core.decode_u.pc_seq_next [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [8]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [6]), + .O(\core.decode_u.pc_seq_next [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [7]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [5]), + .O(\core.decode_u.pc_seq_next [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [6]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [4]), + .O(\core.decode_u.pc_seq_next [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [5]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [3]), + .O(\core.decode_u.pc_seq_next [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [4]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [2]), + .O(\core.decode_u.pc_seq_next [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [30]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [28]), + .O(\core.decode_u.pc_seq_next [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.decode_u.pc_seq_next_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.pc [29]), + .I3(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [27]), + .O(\core.decode_u.pc_seq_next [29]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [9]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [10]), + .I0(1'h0), + .I1(\core.decode_u.pc [11]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_1 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [8]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [9]), + .I0(1'h0), + .I1(\core.decode_u.pc [10]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_10 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [26]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [27]), + .I0(1'h0), + .I1(\core.decode_u.pc [28]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_11 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [25]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [26]), + .I0(1'h0), + .I1(\core.decode_u.pc [27]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_12 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [24]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [25]), + .I0(1'h0), + .I1(\core.decode_u.pc [26]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_13 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [23]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [24]), + .I0(1'h0), + .I1(\core.decode_u.pc [25]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_14 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [22]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [23]), + .I0(1'h0), + .I1(\core.decode_u.pc [24]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_15 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [21]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [22]), + .I0(1'h0), + .I1(\core.decode_u.pc [23]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_16 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [20]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [21]), + .I0(1'h0), + .I1(\core.decode_u.pc [22]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_17 ( + .CI(\core.decode_u.pc [2]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [2]), + .I0(1'h0), + .I1(\core.decode_u.pc [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_18 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [19]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [20]), + .I0(1'h0), + .I1(\core.decode_u.pc [21]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_19 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [18]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [19]), + .I0(1'h0), + .I1(\core.decode_u.pc [20]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_2 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [7]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [8]), + .I0(1'h0), + .I1(\core.decode_u.pc [9]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_20 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [17]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [18]), + .I0(1'h0), + .I1(\core.decode_u.pc [19]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_21 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [16]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [17]), + .I0(1'h0), + .I1(\core.decode_u.pc [18]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_22 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [15]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [16]), + .I0(1'h0), + .I1(\core.decode_u.pc [17]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_23 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [14]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [15]), + .I0(1'h0), + .I1(\core.decode_u.pc [16]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_24 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [13]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [14]), + .I0(1'h0), + .I1(\core.decode_u.pc [15]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_25 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [12]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [13]), + .I0(1'h0), + .I1(\core.decode_u.pc [14]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_26 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [11]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [12]), + .I0(1'h0), + .I1(\core.decode_u.pc [13]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_27 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [10]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [11]), + .I0(1'h0), + .I1(\core.decode_u.pc [12]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_3 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [6]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [7]), + .I0(1'h0), + .I1(\core.decode_u.pc [8]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_4 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [5]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [6]), + .I0(1'h0), + .I1(\core.decode_u.pc [7]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_5 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [4]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [5]), + .I0(1'h0), + .I1(\core.decode_u.pc [6]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_6 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [3]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [4]), + .I0(1'h0), + .I1(\core.decode_u.pc [5]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_7 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [2]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [3]), + .I0(1'h0), + .I1(\core.decode_u.pc [4]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_8 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [28]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [29]), + .I0(1'h0), + .I1(\core.decode_u.pc [30]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_decode.v:132.33-132.72|/home/luke/proj/hazard3/hdl/hazard3_core.v:229.3-275.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.decode_u.pc_seq_next_SB_LUT4_O_I3_SB_CARRY_CO_9 ( + .CI(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [27]), + .CO(\core.decode_u.pc_seq_next_SB_LUT4_O_I3 [28]), + .I0(1'h0), + .I1(\core.decode_u.pc [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.df_cir_use_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.df_cir_use [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .O(\core.df_cir_use_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.df_cir_use_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .I2(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(\core.df_cir_use_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.df_cir_use_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I1(\core.frontend.cir_vld [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir_vld [1]), + .O(\core.df_cir_use [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.buf_level_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.buf_level_next [0]), + .Q(\core.frontend.buf_level [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.frontend.buf_level_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.frontend.fifo_valid_hw[0] [1]), + .I2(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I3(\core.frontend.buf_level [0]), + .O(\core.frontend.buf_level_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff30) + ) \core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.frontend.fifo_full ), + .I2(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [1]), + .I3(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .O(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I3(\core.frontend.fifo_almost_full ), + .O(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fc) + ) \core.frontend.buf_level_next_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.buf_level_SB_LUT4_I3_O [0]), + .I2(\core.frontend.buf_level_SB_LUT4_I3_O [1]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [0]), + .O(\core.frontend.buf_level_next [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0b04) + ) \core.frontend.buf_level_next_SB_LUT4_O_1 ( + .I0(\core.frontend.fifo_valid_hw[0] [1]), + .I1(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.frontend.buf_level [0]), + .O(\core.frontend.buf_level_next [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.next_instr [14]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.next_instr [13]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.frontend.next_instr [4]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.frontend.next_instr [3]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.frontend.next_instr [2]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.frontend.next_instr [1]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.frontend.next_instr [0]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.frontend.next_instr [31]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.frontend.next_instr [30]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.frontend.next_instr [29]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.frontend.next_instr [28]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.frontend.next_instr [27]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.frontend.next_instr [12]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.frontend.next_instr [26]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.frontend.next_instr [25]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.frontend.next_instr [11]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.frontend.next_instr [10]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.frontend.next_instr [9]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.frontend.next_instr [8]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.frontend.next_instr [7]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.frontend.next_instr [6]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.frontend.next_instr [5]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.next_instr [24]), + .Q(\core.frontend.cir [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_1 ( + .C(clk), + .D(\core.frontend.next_instr [23]), + .Q(\core.frontend.cir [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_2 ( + .C(clk), + .D(\core.frontend.next_instr [22]), + .Q(\core.frontend.cir [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_3 ( + .C(clk), + .D(\core.frontend.next_instr [21]), + .Q(\core.frontend.cir [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_4 ( + .C(clk), + .D(\core.frontend.next_instr [20]), + .Q(\core.frontend.cir [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_5 ( + .C(clk), + .D(\core.frontend.next_instr [19]), + .Q(\core.frontend.cir [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_6 ( + .C(clk), + .D(\core.frontend.next_instr [18]), + .Q(\core.frontend.cir [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_7 ( + .C(clk), + .D(\core.frontend.next_instr [17]), + .Q(\core.frontend.cir [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_8 ( + .C(clk), + .D(\core.frontend.next_instr [16]), + .Q(\core.frontend.cir [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_SB_DFFR_Q_9 ( + .C(clk), + .D(\core.frontend.next_instr [15]), + .Q(\core.frontend.cir [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_bus_err_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.cir_bus_err_plus_fetch [1]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir_bus_err [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.cir_bus_err_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.cir_bus_err_plus_fetch [0]), + .E(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .Q(\core.frontend.cir_bus_err [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hac00) + ) \core.frontend.cir_bus_err_plus_fetch_SB_LUT4_O ( + .I0(\core.frontend.fifo_err[0] ), + .I1(\core.frontend.mem_data_err ), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.cir_bus_err_plus_fetch [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff40) + ) \core.frontend.cir_bus_err_plus_fetch_SB_LUT4_O_1 ( + .I0(\core.df_cir_use [1]), + .I1(\core.frontend.cir_vld [1]), + .I2(\core.frontend.cir_bus_err [1]), + .I3(\core.frontend.cir_bus_err_plus_fetch [1]), + .O(\core.frontend.cir_bus_err_plus_fetch [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_vld_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.buf_level_next [1]), + .Q(\core.frontend.cir_vld [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:499.1-520.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.cir_vld_SB_DFFR_Q_1 ( + .C(clk), + .D(\core.frontend.cir_vld_SB_DFFR_Q_1_D ), + .Q(\core.frontend.cir_vld [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf100) + ) \core.frontend.cir_vld_SB_DFFR_Q_1_D_SB_LUT4_O ( + .I0(\core.frontend.buf_level_SB_LUT4_I3_O [1]), + .I1(\core.frontend.buf_level_SB_LUT4_I3_O [0]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [0]), + .I3(\core.frontend.buf_level_next [0]), + .O(\core.frontend.cir_vld_SB_DFFR_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.ctr_flush_pending_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.ctr_flush_pending_SB_DFFER_Q_D ), + .E(\core.frontend.ctr_flush_pending_SB_DFFER_Q_E ), + .Q(\core.frontend.ctr_flush_pending [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.ctr_flush_pending_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.ctr_flush_pending_SB_DFFER_Q_1_D ), + .E(\core.frontend.ctr_flush_pending_SB_DFFER_Q_E ), + .Q(\core.frontend.ctr_flush_pending [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3c55) + ) \core.frontend.ctr_flush_pending_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(\core.frontend.ctr_flush_pending [0]), + .I1(dphase_active_i_SB_LUT4_I3_O[1]), + .I2(\core.frontend.pending_fetches [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.ctr_flush_pending_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h55c3) + ) \core.frontend.ctr_flush_pending_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.frontend.ctr_flush_pending_SB_DFFER_Q_D_SB_LUT4_O_I0 [0]), + .I1(\core.frontend.ctr_flush_pending [1]), + .I2(\core.frontend.ctr_flush_pending [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.ctr_flush_pending_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30cf) + ) \core.frontend.ctr_flush_pending_SB_DFFER_Q_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.pending_fetches [0]), + .I2(dphase_active_i_SB_LUT4_I3_O[1]), + .I3(\core.frontend.pending_fetches [1]), + .O(\core.frontend.ctr_flush_pending_SB_DFFER_Q_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffe0) + ) \core.frontend.ctr_flush_pending_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(\core.frontend.ctr_flush_pending [1]), + .I1(\core.frontend.ctr_flush_pending [0]), + .I2(dphase_active_i_SB_LUT4_I3_O[1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.ctr_flush_pending_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.frontend.ctr_flush_pending_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending [1]), + .I2(\core.frontend.ctr_flush_pending [0]), + .I3(dphase_active_i_SB_LUT4_I3_O[1]), + .O(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h10ff) + ) \core.frontend.ctr_flush_pending_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.frontend.cir_vld [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir_vld [1]), + .O(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_CI ( + .CI(\core.frontend.fetch_addr [2]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [2]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [9]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [10]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [11]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_1 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [8]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [9]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [10]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_10 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [26]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [27]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [28]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_11 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [25]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [26]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [27]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_12 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [24]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [25]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [26]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_13 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [23]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [24]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [25]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_14 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [22]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [23]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [24]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_15 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [21]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [22]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [23]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_16 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [20]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [21]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [22]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_17 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [19]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [20]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [21]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_18 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [18]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [19]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [20]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_19 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [17]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [18]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [19]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_2 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [7]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [8]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [9]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_20 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [16]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [17]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [18]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_21 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [15]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [16]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [17]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_22 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [14]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [15]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [16]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_23 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [13]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [14]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [15]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_24 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [12]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [13]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [14]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_25 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [11]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [12]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [13]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_26 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [10]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [11]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [12]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_3 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [6]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [7]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [8]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_4 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [5]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [6]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [7]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_5 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [4]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [5]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [6]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_6 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [3]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [4]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [5]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_7 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [2]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [3]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [4]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_8 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [28]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [29]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [30]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.frontend.fetch_addr_SB_CARRY_I1_9 ( + .CI(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [27]), + .CO(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [28]), + .I0(1'h0), + .I1(\core.frontend.fetch_addr [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_1_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_10_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_10_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [19]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[19]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_11_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_11_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [18]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[18]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_12_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_12_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [17]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[17]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_13_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_13_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [16]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[16]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_14_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_14_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [15]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[15]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_15_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_15_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [14]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[14]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_16_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_16_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [13]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[13]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_17_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_17_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [12]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[12]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_18_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_18_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [11]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[11]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_19_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_19_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [10]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[10]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [28]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[28]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_2_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_20_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_20_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [9]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[9]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_21_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_21_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [8]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[8]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_22_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_22_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [7]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[7]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_23_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_23_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [6]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[6]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_24_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_24_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [5]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[5]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_25_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_25_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [4]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[4]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_26_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_26_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [3]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[3]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_27_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_27_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [2]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_28_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_28_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [1]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_29_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.frontend.fetch_addr_SB_DFFER_Q_29_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [2]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [27]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[27]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_3_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [26]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[26]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_4_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [25]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[25]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_5_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [24]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[24]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_6_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [23]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[23]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_7_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [22]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[22]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_8_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [21]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[21]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:257.1-278.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fetch_addr_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.frontend.fetch_addr_SB_DFFER_Q_9_D ), + .E(i_hready_SB_LUT4_I2_O), + .Q(\core.frontend.fetch_addr [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [20]), + .I2(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[20]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [11]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [9]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [10]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [8]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [28]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [26]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [27]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [25]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [26]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [24]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [25]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [23]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [24]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [22]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [23]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [21]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [22]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [20]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [3]), + .I3(\core.frontend.fetch_addr [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [21]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [19]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [20]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [18]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [9]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [7]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [19]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [17]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [18]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [16]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [17]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [15]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [16]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [14]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [15]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [13]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [14]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [12]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [13]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [11]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [12]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [10]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [8]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [6]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [7]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [5]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [6]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [4]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [5]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [3]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [4]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [2]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [30]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [28]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fetch_addr [29]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [27]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_9_D_SB_LUT4_O_I1 [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:273.19-273.37|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8bb8) + ) \core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[29]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I2(\core.frontend.fetch_addr [31]), + .I3(\core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [29]), + .O(\core.frontend.fetch_addr_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.fifo_almost_full_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.fifo_almost_full_SB_DFFR_Q_D ), + .Q(\core.frontend.fifo_almost_full ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fe) + ) \core.frontend.fifo_almost_full_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [0]), + .I1(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [1]), + .I2(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.frontend.fifo_almost_full_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf00c) + ) \core.frontend.fifo_almost_full_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2]), + .I2(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I3(\core.frontend.fifo_almost_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_err[0]_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.fifo_err[0]_SB_DFFER_Q_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_err[0] ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_err[1]_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.mem_data_err ), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_err[1] ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.frontend.fifo_err[1]_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.frontend.fifo_err[1] ), + .I2(\core.frontend.mem_data_err ), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_err[0]_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.fifo_full_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.fifo_full_SB_DFFR_Q_D ), + .Q(\core.frontend.fifo_full ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h004f) + ) \core.frontend.fifo_full_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I1(\core.frontend.fifo_full ), + .I2(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E [2]), + .I3(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E [3]), + .O(\core.frontend.fifo_full_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_1_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_10_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_10_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[21]), + .I2(\core.frontend.fifo_mem[1] [21]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_11_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_11_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[20]), + .I2(\core.frontend.fifo_mem[1] [20]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_12_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_12_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[19]), + .I2(\core.frontend.fifo_mem[1] [19]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_13_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_13_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[18]), + .I2(\core.frontend.fifo_mem[1] [18]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_14_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_14_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[17]), + .I2(\core.frontend.fifo_mem[1] [17]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_15_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_15_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[16]), + .I2(\core.frontend.fifo_mem[1] [16]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_16_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_16_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[15]), + .I2(\core.frontend.fifo_mem[1] [15]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_17_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_17_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[14]), + .I2(\core.frontend.fifo_mem[1] [14]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_18_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_18_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[13]), + .I2(\core.frontend.fifo_mem[1] [13]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_19_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_19_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[12]), + .I2(\core.frontend.fifo_mem[1] [12]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[30]), + .I2(\core.frontend.fifo_mem[1] [30]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_2_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_20_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_20_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[11]), + .I2(\core.frontend.fifo_mem[1] [11]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_21_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_21_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[10]), + .I2(\core.frontend.fifo_mem[1] [10]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_22_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_22_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[9]), + .I2(\core.frontend.fifo_mem[1] [9]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_23_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_23_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[8]), + .I2(\core.frontend.fifo_mem[1] [8]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_24_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_24_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[7]), + .I2(\core.frontend.fifo_mem[1] [7]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_25_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_25_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[6]), + .I2(\core.frontend.fifo_mem[1] [6]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_26_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_26_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[5]), + .I2(\core.frontend.fifo_mem[1] [5]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_27_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_27_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[4]), + .I2(\core.frontend.fifo_mem[1] [4]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_28_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_28_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[3]), + .I2(\core.frontend.fifo_mem[1] [3]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_29_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_29_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[2]), + .I2(\core.frontend.fifo_mem[1] [2]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[29]), + .I2(\core.frontend.fifo_mem[1] [29]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_3_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_30 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_30_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_30_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[1]), + .I2(\core.frontend.fifo_mem[1] [1]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_30_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_31 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_31_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_31_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[0]), + .I2(\core.frontend.fifo_mem[1] [0]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_31_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[28]), + .I2(\core.frontend.fifo_mem[1] [28]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_4_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[27]), + .I2(\core.frontend.fifo_mem[1] [27]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_5_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[26]), + .I2(\core.frontend.fifo_mem[1] [26]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_6_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[25]), + .I2(\core.frontend.fifo_mem[1] [25]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_7_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[24]), + .I2(\core.frontend.fifo_mem[1] [24]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_8_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[23]), + .I2(\core.frontend.fifo_mem[1] [23]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[0]_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.frontend.fifo_mem[0]_SB_DFFER_Q_9_D ), + .E(\core.frontend.fifo_mem[0]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_mem[0] [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_9_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[22]), + .I2(\core.frontend.fifo_mem[1] [22]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.frontend.fifo_mem[0]_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(i_hrdata[31]), + .I2(\core.frontend.fifo_mem[1] [31]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_mem[0]_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q ( + .C(clk), + .D(i_hrdata[31]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_1 ( + .C(clk), + .D(i_hrdata[30]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_10 ( + .C(clk), + .D(i_hrdata[21]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_11 ( + .C(clk), + .D(i_hrdata[20]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_12 ( + .C(clk), + .D(i_hrdata[19]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_13 ( + .C(clk), + .D(i_hrdata[18]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_14 ( + .C(clk), + .D(i_hrdata[17]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_15 ( + .C(clk), + .D(i_hrdata[16]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_16 ( + .C(clk), + .D(i_hrdata[15]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_17 ( + .C(clk), + .D(i_hrdata[14]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_18 ( + .C(clk), + .D(i_hrdata[13]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_19 ( + .C(clk), + .D(i_hrdata[12]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_2 ( + .C(clk), + .D(i_hrdata[29]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_20 ( + .C(clk), + .D(i_hrdata[11]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_21 ( + .C(clk), + .D(i_hrdata[10]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_22 ( + .C(clk), + .D(i_hrdata[9]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_23 ( + .C(clk), + .D(i_hrdata[8]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_24 ( + .C(clk), + .D(i_hrdata[7]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_25 ( + .C(clk), + .D(i_hrdata[6]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_26 ( + .C(clk), + .D(i_hrdata[5]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_27 ( + .C(clk), + .D(i_hrdata[4]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_28 ( + .C(clk), + .D(i_hrdata[3]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_29 ( + .C(clk), + .D(i_hrdata[2]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_3 ( + .C(clk), + .D(i_hrdata[28]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_30 ( + .C(clk), + .D(i_hrdata[1]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_31 ( + .C(clk), + .D(i_hrdata[0]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_4 ( + .C(clk), + .D(i_hrdata[27]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_5 ( + .C(clk), + .D(i_hrdata[26]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_6 ( + .C(clk), + .D(i_hrdata[25]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_7 ( + .C(clk), + .D(i_hrdata[24]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_8 ( + .C(clk), + .D(i_hrdata[23]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_mem[1]_SB_DFFER_Q_9 ( + .C(clk), + .D(i_hrdata[22]), + .E(\core.frontend.buf_level_SB_LUT4_I3_I2_SB_LUT4_I3_O ), + .Q(\core.frontend.fifo_mem[1] [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_valid_hw[0]_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_D ), + .E(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E [2]), + .Q(\core.frontend.fifo_valid_hw[0] [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fifo_full ), + .I2(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2]), + .O(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0ff) + ) \core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [2]), + .O(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hacff) + ) \core.frontend.fifo_valid_hw[0]_SB_LUT4_I0 ( + .I0(\core.frontend.fifo_valid_hw[0] [1]), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.buf_level_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:139.1-180.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.frontend.fifo_valid_hw[1]_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_D ), + .E(\core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_E ), + .Q(\core.frontend.fifo_valid_hw[1] [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0e00) + ) \core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [0]), + .I1(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [2]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2]), + .O(\core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfcff) + ) \core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_valid_hw[1]_SB_DFFER_Q_E ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0 ( + .I0(\core.frontend.fifo_valid_hw[1] [1]), + .I1(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I3 [3]), + .O(\core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.fifo_full ), + .O(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.fifo_almost_full ), + .I2(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2]), + .O(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I3(\core.frontend.fifo_almost_full ), + .O(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I3(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [0]), + .O(\core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.mem_addr_hold_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.mem_addr_hold_SB_DFFR_Q_D ), + .Q(\core.frontend.mem_addr_hold ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.frontend.mem_addr_hold_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(i_hready), + .I3(\core.frontend.mem_addr_vld ), + .O(\core.frontend.mem_addr_hold_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.frontend.mem_addr_hold_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold ), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .I3(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]), + .O(\core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .O(\core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ef) + ) \core.frontend.mem_addr_vld_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I0 [0]), + .I1(\core.frontend.mem_addr_hold ), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2 [0]), + .I3(\core.frontend.reset_holdoff ), + .O(\core.frontend.mem_addr_vld ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0007) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.frontend.pending_fetches [0]), + .I1(\core.frontend.fifo_almost_full ), + .I2(\core.frontend.fifo_full ), + .I3(\core.frontend.pending_fetches [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2 [0]), + .I3(\core.frontend.mem_addr_hold ), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00cf) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.x_jump_misaligned ), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf400) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(\core.x_jump_misaligned ), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_hold ), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [3]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbf00) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(bus_hold_aph_SB_LUT4_I2_O[0]), + .I1(bus_hold_aph_SB_LUT4_I2_O[1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I3(bus_hold_aph_SB_LUT4_I2_O[3]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0b00) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.frontend.cir [13]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.frontend.cir [15]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf400) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [1]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [0]), + .I2(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I3(\core.frontend.cir [13]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [3]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [2]), + .I3(\core.frontend.cir [13]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [2]), + .I3(\core.frontend.cir [12]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.x_jump_misaligned ), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.frontend.cir_vld [0]), + .I1(\core.frontend.cir_bus_err [0]), + .I2(\core.frontend.cir_bus_err [1]), + .I3(\core.frontend.cir_vld [1]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00cf) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[0]), + .I2(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[1]), + .I3(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[2]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc300) + ) \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O [0]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O [1]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O [2]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.frontend.mem_data_err_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(dphase_active_i_SB_LUT4_I3_O[1]), + .I3(i_hresp), + .O(\core.frontend.mem_data_err ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O ( + .I0(i_hrdata[31]), + .I1(\core.frontend.fifo_mem[0] [31]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_1 ( + .I0(i_hrdata[30]), + .I1(\core.frontend.fifo_mem[0] [30]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc0ff) + ) \core.frontend.next_instr_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I2(\core.frontend.fifo_mem[0] [21]), + .I3(\core.frontend.next_instr_SB_LUT4_O_10_I3 [2]), + .O(\core.frontend.next_instr [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbb0f) + ) \core.frontend.next_instr_SB_LUT4_O_10_I3_SB_LUT4_O ( + .I0(\core.frontend.fifo_almost_full ), + .I1(i_hrdata[21]), + .I2(\core.frontend.cir [21]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_10_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc0ff) + ) \core.frontend.next_instr_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I2(\core.frontend.fifo_mem[0] [20]), + .I3(\core.frontend.next_instr_SB_LUT4_O_11_I3 [2]), + .O(\core.frontend.next_instr [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbb0f) + ) \core.frontend.next_instr_SB_LUT4_O_11_I3_SB_LUT4_O ( + .I0(\core.frontend.fifo_almost_full ), + .I1(i_hrdata[20]), + .I2(\core.frontend.cir [20]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_11_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.frontend.next_instr_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [19]), + .I3(\core.frontend.next_instr_SB_LUT4_O_12_I3 [2]), + .O(\core.frontend.next_instr [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h35ff) + ) \core.frontend.next_instr_SB_LUT4_O_12_I3_SB_LUT4_O ( + .I0(i_hrdata[19]), + .I1(\core.frontend.fifo_mem[0] [19]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_12_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.frontend.next_instr_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [18]), + .I3(\core.frontend.next_instr_SB_LUT4_O_13_I3 [2]), + .O(\core.frontend.next_instr [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h35ff) + ) \core.frontend.next_instr_SB_LUT4_O_13_I3_SB_LUT4_O ( + .I0(i_hrdata[18]), + .I1(\core.frontend.fifo_mem[0] [18]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_13_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc0ff) + ) \core.frontend.next_instr_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I2(\core.frontend.fifo_mem[0] [17]), + .I3(\core.frontend.next_instr_SB_LUT4_O_14_I3 [2]), + .O(\core.frontend.next_instr [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbb0f) + ) \core.frontend.next_instr_SB_LUT4_O_14_I3_SB_LUT4_O ( + .I0(\core.frontend.fifo_almost_full ), + .I1(i_hrdata[17]), + .I2(\core.frontend.cir [17]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_14_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.frontend.next_instr_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [16]), + .I3(\core.frontend.next_instr_SB_LUT4_O_15_I3 [2]), + .O(\core.frontend.next_instr [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h35ff) + ) \core.frontend.next_instr_SB_LUT4_O_15_I3_SB_LUT4_O ( + .I0(i_hrdata[16]), + .I1(\core.frontend.fifo_mem[0] [16]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_15_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.frontend.next_instr_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [15]), + .I3(\core.frontend.next_instr_SB_LUT4_O_16_I3 [2]), + .O(\core.frontend.next_instr [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h35ff) + ) \core.frontend.next_instr_SB_LUT4_O_16_I3_SB_LUT4_O ( + .I0(i_hrdata[15]), + .I1(\core.frontend.fifo_mem[0] [15]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_16_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_17 ( + .I0(i_hrdata[14]), + .I1(\core.frontend.fifo_mem[0] [14]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_18 ( + .I0(i_hrdata[13]), + .I1(\core.frontend.fifo_mem[0] [13]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_19 ( + .I0(i_hrdata[12]), + .I1(\core.frontend.fifo_mem[0] [12]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_2 ( + .I0(i_hrdata[29]), + .I1(\core.frontend.fifo_mem[0] [29]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_20 ( + .I0(i_hrdata[11]), + .I1(\core.frontend.fifo_mem[0] [11]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_21 ( + .I0(i_hrdata[10]), + .I1(\core.frontend.fifo_mem[0] [10]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_22 ( + .I0(i_hrdata[9]), + .I1(\core.frontend.fifo_mem[0] [9]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_23 ( + .I0(i_hrdata[8]), + .I1(\core.frontend.fifo_mem[0] [8]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_24 ( + .I0(i_hrdata[7]), + .I1(\core.frontend.fifo_mem[0] [7]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_25 ( + .I0(i_hrdata[6]), + .I1(\core.frontend.fifo_mem[0] [6]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_26 ( + .I0(i_hrdata[5]), + .I1(\core.frontend.fifo_mem[0] [5]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_27 ( + .I0(i_hrdata[4]), + .I1(\core.frontend.fifo_mem[0] [4]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_28 ( + .I0(i_hrdata[3]), + .I1(\core.frontend.fifo_mem[0] [3]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_29 ( + .I0(i_hrdata[2]), + .I1(\core.frontend.fifo_mem[0] [2]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_3 ( + .I0(i_hrdata[28]), + .I1(\core.frontend.fifo_mem[0] [28]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_30 ( + .I0(i_hrdata[1]), + .I1(\core.frontend.fifo_mem[0] [1]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_31 ( + .I0(i_hrdata[0]), + .I1(\core.frontend.fifo_mem[0] [0]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_4 ( + .I0(i_hrdata[27]), + .I1(\core.frontend.fifo_mem[0] [27]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_5 ( + .I0(i_hrdata[26]), + .I1(\core.frontend.fifo_mem[0] [26]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.frontend.next_instr_SB_LUT4_O_6 ( + .I0(i_hrdata[25]), + .I1(\core.frontend.fifo_mem[0] [25]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.frontend.next_instr_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [24]), + .I3(\core.frontend.next_instr_SB_LUT4_O_7_I3 [2]), + .O(\core.frontend.next_instr [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h35ff) + ) \core.frontend.next_instr_SB_LUT4_O_7_I3_SB_LUT4_O ( + .I0(i_hrdata[24]), + .I1(\core.frontend.fifo_mem[0] [24]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_7_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.frontend.next_instr_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [23]), + .I3(\core.frontend.next_instr_SB_LUT4_O_8_I3 [2]), + .O(\core.frontend.next_instr [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h35ff) + ) \core.frontend.next_instr_SB_LUT4_O_8_I3_SB_LUT4_O ( + .I0(i_hrdata[23]), + .I1(\core.frontend.fifo_mem[0] [23]), + .I2(\core.frontend.fifo_almost_full ), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_8_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc0ff) + ) \core.frontend.next_instr_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.frontend.buf_level_SB_LUT4_I3_I2 [1]), + .I2(\core.frontend.fifo_mem[0] [22]), + .I3(\core.frontend.next_instr_SB_LUT4_O_9_I3 [2]), + .O(\core.frontend.next_instr [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbb0f) + ) \core.frontend.next_instr_SB_LUT4_O_9_I3_SB_LUT4_O ( + .I0(\core.frontend.fifo_almost_full ), + .I1(i_hrdata[22]), + .I2(\core.frontend.cir [22]), + .I3(\core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1]), + .O(\core.frontend.next_instr_SB_LUT4_O_9_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.pending_fetches_SB_DFFR_Q ( + .C(clk), + .D(\core.frontend.pending_fetches_next [1]), + .Q(\core.frontend.pending_fetches [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:352.1-371.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.frontend.pending_fetches_SB_DFFR_Q_1 ( + .C(clk), + .D(\core.frontend.pending_fetches_next [0]), + .Q(\core.frontend.pending_fetches [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hd2b4) + ) \core.frontend.pending_fetches_next_SB_LUT4_O ( + .I0(dphase_active_i_SB_LUT4_I3_O[0]), + .I1(dphase_active_i_SB_LUT4_I3_O[1]), + .I2(\core.frontend.pending_fetches [1]), + .I3(\core.frontend.pending_fetches [0]), + .O(\core.frontend.pending_fetches_next [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc33c) + ) \core.frontend.pending_fetches_next_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(dphase_active_i_SB_LUT4_I3_O[0]), + .I2(dphase_active_i_SB_LUT4_I3_O[1]), + .I3(\core.frontend.pending_fetches [0]), + .O(\core.frontend.pending_fetches_next [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:283.1-295.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" *) + SB_DFFS \core.frontend.reset_holdoff_SB_DFFS_Q ( + .C(clk), + .D(1'h0), + .Q(\core.frontend.reset_holdoff ), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ff) + ) \core.m_reg_wen_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(1'h0), + .I3(\core.m_reg_wen ), + .O(\core.m_reg_wen_SB_LUT4_I3_O ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.m_reg_wen_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.m_reg_wen_SB_LUT4_O_I2 [0]), + .I3(\core.m_reg_wen_if_nonzero ), + .O(\core.m_reg_wen ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.m_reg_wen_SB_LUT4_O_I2 [0]), + .I2(\core.m_reg_wen_SB_LUT4_O_I2 [1]), + .I3(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3 [3]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:358.2-358.21|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO ( + .CI(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI [3]), + .CO(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3 [3]), + .I0(1'h0), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:358.2-358.21|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI_SB_CARRY_CO ( + .CI(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [0]), + .CO(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI [3]), + .I0(1'h1), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ff) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(1'h0), + .I3(\core.xm_memop [2]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ff) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(1'h0), + .I3(\core.xm_memop [4]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ff) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(1'h0), + .I3(\core.xm_memop [1]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [0]), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [1]), + .I2(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [2]), + .I3(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [3]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h40bf) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.frontend.cir [15]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.xm_rd [0]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_2 ( + .I0(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [0]), + .I1(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [1]), + .I2(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [2]), + .I3(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_I0_O [3]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h400f) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.xm_rd [4]), + .I3(\core.frontend.cir [19]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h40bf) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [16]), + .I3(\core.xm_rd [1]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h40bf) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [17]), + .I3(\core.xm_rd [2]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbf40) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_3 ( + .I0(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.frontend.cir [18]), + .I3(\core.xm_rd [3]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_memop [4]), + .I1(\core.xm_memop [1]), + .I2(\core.xm_memop [2]), + .I3(\core.xm_memop [0]), + .O(\core.m_reg_wen_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_rd [0]), + .I2(\core.xm_rd [1]), + .I3(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .O(\core.m_reg_wen_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_rd [2]), + .I2(\core.xm_rd [3]), + .I3(\core.xm_rd [4]), + .O(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.m_reg_wen_if_nonzero_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2 [3]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .O(\core.m_reg_wen_if_nonzero ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000d) + ) \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3 ( + .I0(\core.frontend.mem_addr_hold ), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I2(\core.power_ctrl.stall_release_SB_LUT4_I2_O [1]), + .I3(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2 [3]), + .O(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [7]), + .I2(\core.m_result_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result [31]), + .I2(\core.m_result_SB_LUT4_O_1_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.xm_result [22]), + .I2(\core.m_result_SB_LUT4_O_10_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_10_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[22]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_10_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.xm_result [21]), + .I2(\core.m_result_SB_LUT4_O_11_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_11_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[21]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_11_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.xm_result [20]), + .I2(\core.m_result_SB_LUT4_O_12_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_12_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[20]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_12_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.xm_result [19]), + .I2(\core.m_result_SB_LUT4_O_13_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_13_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[19]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_13_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.xm_result [18]), + .I2(\core.m_result_SB_LUT4_O_14_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_14_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[18]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_14_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.xm_result [17]), + .I2(\core.m_result_SB_LUT4_O_15_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_15_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[17]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_15_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.xm_result [16]), + .I2(\core.m_result_SB_LUT4_O_16_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_16_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[16]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_16_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf077) + ) \core.m_result_SB_LUT4_O_17 ( + .I0(\core.m_result_SB_LUT4_O_17_I0 [0]), + .I1(\core.m_result_SB_LUT4_O_17_I1 [3]), + .I2(\core.xm_result [15]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0bbb) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0 [2]), + .I1(d_hrdata[15]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(d_hrdata[31]), + .O(\core.m_result_SB_LUT4_O_17_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0 [2]), + .O(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1 ( + .I0(1'h0), + .I1(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O_I2 [2]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0 [2]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(d_hrdata[8]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [2]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.xm_memop [2]), + .I1(\core.xm_memop [0]), + .I2(\core.xm_memop [1]), + .I3(\core.xm_memop [4]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[24]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbcff) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_addr_align [1]), + .I1(\core.xm_memop [0]), + .I2(\core.xm_memop [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]), + .I2(\core.xm_addr_align [1]), + .I3(\core.xm_memop [0]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_addr_align [0]), + .I3(\core.xm_addr_align [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_memop [0]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]), + .I3(\core.xm_memop [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1fff) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1 ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I2(\core.xm_addr_align [0]), + .I3(\core.xm_addr_align [1]), + .O(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h001f) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1 ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2 [2]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_addr_align [0]), + .I3(\core.xm_addr_align [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf1ff) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2 ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I2(\core.xm_addr_align [1]), + .I3(\core.xm_addr_align [0]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000b) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hca00) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(d_hrdata[15]), + .I1(d_hrdata[31]), + .I2(\core.xm_addr_align [1]), + .I3(\core.xm_addr_align [0]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.xm_memop [0]), + .I1(\core.xm_memop [4]), + .I2(\core.xm_memop [1]), + .I3(\core.xm_memop [2]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fff) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2 [0]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc0a) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O ( + .I0(d_hrdata[7]), + .I1(d_hrdata[23]), + .I2(\core.xm_addr_align [0]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3 [3]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcfa0) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(d_hrdata[15]), + .I1(d_hrdata[31]), + .I2(\core.xm_addr_align [0]), + .I3(\core.xm_addr_align [1]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(d_hrdata[7]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf800) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2 [2]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(d_hrdata[23]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_memop [2]), + .I3(\core.xm_memop [4]), + .O(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbf00) + ) \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3 ( + .I0(\core.xm_memop [1]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I2(d_hrdata[31]), + .I3(\core.m_result_SB_LUT4_O_17_I1 [3]), + .O(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_memop [0]), + .I2(\core.xm_memop [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]), + .O(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7f00) + ) \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O ( + .I0(d_hrdata[15]), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O_I2 [2]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_17_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.xm_result [14]), + .I2(\core.m_result_SB_LUT4_O_18_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_18_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[14]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_18_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_18_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_18_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[30]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_18_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.xm_result [13]), + .I2(\core.m_result_SB_LUT4_O_19_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_19_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[13]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_19_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_19_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_19_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[29]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_19_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[31]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.xm_result [30]), + .I2(\core.m_result_SB_LUT4_O_2_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.xm_result [12]), + .I2(\core.m_result_SB_LUT4_O_20_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_20_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[12]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_20_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_20_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_20_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[28]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_20_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.xm_result [11]), + .I2(\core.m_result_SB_LUT4_O_21_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_21_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[11]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_21_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_21_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_21_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[27]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_21_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.xm_result [10]), + .I2(\core.m_result_SB_LUT4_O_22_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_22_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[10]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_22_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_22_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_22_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[26]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_22_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.xm_result [9]), + .I2(\core.m_result_SB_LUT4_O_23_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_23_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[9]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1]), + .I3(\core.m_result_SB_LUT4_O_23_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_23_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_23_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[25]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.m_result_SB_LUT4_O_23_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.xm_result [8]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.xm_result [6]), + .I2(\core.m_result_SB_LUT4_O_25_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[6]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_25_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[14]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(\core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[22]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(d_hrdata[30]), + .O(\core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.xm_result [5]), + .I2(\core.m_result_SB_LUT4_O_26_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[5]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_26_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[29]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[21]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(d_hrdata[13]), + .O(\core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.xm_result [4]), + .I2(\core.m_result_SB_LUT4_O_27_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[4]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_27_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[28]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[20]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(d_hrdata[12]), + .O(\core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.xm_result [3]), + .I2(\core.m_result_SB_LUT4_O_28_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_28_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[3]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [2]), + .O(\core.m_result_SB_LUT4_O_28_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.xm_result [2]), + .I2(\core.m_result_SB_LUT4_O_29_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[2]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_29_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[26]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[18]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(d_hrdata[10]), + .O(\core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_2_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[30]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_2_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.xm_result [29]), + .I2(\core.m_result_SB_LUT4_O_3_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(\core.xm_result [1]), + .I2(\core.m_result_SB_LUT4_O_30_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[1]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_30_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[25]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[17]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(d_hrdata[9]), + .O(\core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(\core.xm_result [0]), + .I2(\core.m_result_SB_LUT4_O_31_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[0]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_31_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[27]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]), + .O(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .O(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[24]), + .I2(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]), + .O(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[19]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(d_hrdata[11]), + .O(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [0]), + .I1(d_hrdata[16]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2]), + .I3(d_hrdata[8]), + .O(\core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_3_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[29]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_3_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.xm_result [28]), + .I2(\core.m_result_SB_LUT4_O_4_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_4_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[28]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_4_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.xm_result [27]), + .I2(\core.m_result_SB_LUT4_O_5_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_5_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[27]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_5_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.xm_result [26]), + .I2(\core.m_result_SB_LUT4_O_6_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_6_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[26]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_6_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.xm_result [25]), + .I2(\core.m_result_SB_LUT4_O_7_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_7_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[25]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_7_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.xm_result [24]), + .I2(\core.m_result_SB_LUT4_O_8_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_8_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[24]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_8_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.m_result_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.xm_result [23]), + .I2(\core.m_result_SB_LUT4_O_9_I2 [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .O(\core.m_result [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.m_result_SB_LUT4_O_9_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hrdata[23]), + .I2(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_9_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.m_result_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [0]), + .I2(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [2]), + .O(\core.m_result_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1284.1-1297.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_rd_SB_DFFER_Q ( + .C(clk), + .D(\core.xm_rd [4]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_rd [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1284.1-1297.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_rd_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.xm_rd [3]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_rd [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1284.1-1297.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_rd_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.xm_rd [2]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_rd [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1284.1-1297.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_rd_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.xm_rd [1]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_rd [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1284.1-1297.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_rd_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.xm_rd [0]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_rd [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q ( + .C(clk), + .D(\core.m_result [31]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.m_result [30]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.m_result [21]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.m_result [20]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.m_result [19]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.m_result [18]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.m_result [17]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.m_result [16]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.m_result [15]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.m_result [14]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.m_result [13]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.m_result [12]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.m_result [29]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.m_result [11]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.m_result [10]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.m_result [9]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.m_result [8]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.m_result [7]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.m_result [6]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.m_result [5]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.m_result [4]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.m_result [3]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.m_result [2]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.m_result [28]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_30 ( + .C(clk), + .D(\core.m_result [1]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_31 ( + .C(clk), + .D(\core.m_result [0]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.m_result [27]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.m_result [26]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.m_result [25]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.m_result [24]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.m_result [23]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1275.1-1282.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.mw_result_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.m_result [22]), + .E(\core.m_reg_wen_if_nonzero ), + .Q(\core.mw_result [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_power_ctrl.v:66.1-119.4|/home/luke/proj/hazard3/hdl/hazard3_core.v:1145.20-1164.2|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.power_ctrl.stall_release_SB_DFFR_Q ( + .C(clk_always_on), + .D(\core.power_ctrl.stall_release_SB_DFFR_Q_D ), + .Q(\core.power_ctrl.stall_release ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff40) + ) \core.power_ctrl.stall_release_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(\core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [1]), + .I1(\core.power_ctrl.stall_release_SB_LUT4_I2_O [1]), + .I2(\core.power_ctrl.state [0]), + .I3(\core.power_ctrl.state [3]), + .O(\core.power_ctrl.stall_release_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.power_ctrl.stall_release_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.power_ctrl.stall_release ), + .I3(\core.xm_sleep_wfi ), + .O(\core.power_ctrl.stall_release_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.power_ctrl.state_SB_DFFR_Q ( + .C(clk_always_on), + .D(\core.power_ctrl.state_SB_DFFR_Q_D ), + .Q(\core.power_ctrl.state [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.power_ctrl.state_SB_DFFR_Q_1 ( + .C(clk_always_on), + .D(pwrup_ack_SB_LUT4_I2_O), + .Q(\core.power_ctrl.state [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.power_ctrl.state_SB_DFFR_Q_2 ( + .C(clk_always_on), + .D(pwrup_ack_SB_LUT4_I1_O), + .Q(\core.power_ctrl.state [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [1]), + .I2(\core.xm_sleep_wfi ), + .I3(\core.power_ctrl.state [1]), + .O(\core.power_ctrl.state_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [1]), + .I3(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [0]), + .O(\core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/ff_map.v:10.57-10.103" *) + SB_DFFS \core.power_ctrl.state_SB_DFFS_Q ( + .C(clk_always_on), + .D(\core.power_ctrl.state_SB_DFFS_Q_D ), + .Q(\core.power_ctrl.state [0]), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) \core.power_ctrl.state_SB_DFFS_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.power_ctrl.state [3]), + .I3(\core.power_ctrl.state [0]), + .O(\core.power_ctrl.state_SB_DFFS_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:885.1-909.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.prev_instr_was_32_bit_SB_DFFER_Q ( + .C(clk), + .D(\core.df_cir_use [1]), + .E(\core.prev_instr_was_32_bit_SB_DFFER_Q_E [0]), + .Q(\core.prev_instr_was_32_bit ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfcff) + ) \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.prev_instr_was_32_bit_SB_DFFER_Q_E [0]), + .I2(\core.frontend.cir_vld [0]), + .I3(\core.frontend.cir_vld [1]), + .O(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [16]), + .O(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E [0]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E [1]), + .O(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'haccc) + ) \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update [17]), + .I1(\core.csr_u.meifa [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .O(\core.prev_instr_was_32_bit_SB_DFFER_Q_E [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_O_1 ( + .I0(\core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .I3(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .O(\core.prev_instr_was_32_bit_SB_DFFER_Q_E [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0ff) + ) \core.prev_instr_was_32_bit_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.prev_instr_was_32_bit ), + .O(\core.prev_instr_was_32_bit_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) \core.prev_instr_was_32_bit_SB_LUT4_I3_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .I3(\core.prev_instr_was_32_bit ), + .O(\core.prev_instr_was_32_bit_SB_LUT4_I3_O [0]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [1]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [2]), + .I0(\core.decode_u.pc [2]), + .I1(\core.prev_instr_was_32_bit_SB_LUT4_I3_O [1]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_1 ( + .CI(1'h1), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [1]), + .I0(\core.decode_u.pc [1]), + .I1(\core.prev_instr_was_32_bit_SB_LUT4_I3_O [0]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [9]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [10]), + .I0(\core.decode_u.pc [10]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_1 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [8]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [9]), + .I0(\core.decode_u.pc [9]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_10 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [27]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [28]), + .I0(\core.decode_u.pc [28]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_11 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [26]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [27]), + .I0(\core.decode_u.pc [27]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_12 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [25]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [26]), + .I0(\core.decode_u.pc [26]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_13 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [24]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [25]), + .I0(\core.decode_u.pc [25]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_14 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [23]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [24]), + .I0(\core.decode_u.pc [24]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_15 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [22]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [23]), + .I0(\core.decode_u.pc [23]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_16 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [21]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [22]), + .I0(\core.decode_u.pc [22]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_17 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [20]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [21]), + .I0(\core.decode_u.pc [21]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_18 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [19]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [20]), + .I0(\core.decode_u.pc [20]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_19 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [18]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [19]), + .I0(\core.decode_u.pc [19]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_2 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [7]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [8]), + .I0(\core.decode_u.pc [8]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_20 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [17]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [18]), + .I0(\core.decode_u.pc [18]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_21 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [16]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [17]), + .I0(\core.decode_u.pc [17]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_22 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [15]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [16]), + .I0(\core.decode_u.pc [16]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_23 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [14]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [15]), + .I0(\core.decode_u.pc [15]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_24 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [13]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [14]), + .I0(\core.decode_u.pc [14]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_25 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [12]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [13]), + .I0(\core.decode_u.pc [13]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_26 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [11]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [12]), + .I0(\core.decode_u.pc [12]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_27 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [10]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [11]), + .I0(\core.decode_u.pc [11]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_3 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [6]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [7]), + .I0(\core.decode_u.pc [7]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_4 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [5]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [6]), + .I0(\core.decode_u.pc [6]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_5 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [4]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [5]), + .I0(\core.decode_u.pc [5]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_6 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [3]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [4]), + .I0(\core.decode_u.pc [4]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_7 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [2]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [3]), + .I0(\core.decode_u.pc [3]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_8 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [29]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [30]), + .I0(\core.decode_u.pc [30]), + .I1(1'h1) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1140.34-1143.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO_SB_CARRY_CO_9 ( + .CI(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [28]), + .CO(\core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [29]), + .I0(\core.decode_u.pc [29]), + .I1(1'h1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.raddr1_SB_LUT4_O_I1 [0]), + .I2(\core.frontend.next_instr [19]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr1 [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(dbg_data0_wdata_SB_LUT4_O_29_I2[0]), + .I2(\core.frontend.next_instr [18]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr1_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(dbg_data0_wdata_SB_LUT4_O_28_I2[0]), + .I2(\core.frontend.next_instr [17]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr1_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [0]), + .I2(\core.frontend.next_instr [16]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr1_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(dbg_data0_wdata_SB_LUT4_O_31_I2[0]), + .I2(\core.frontend.next_instr [15]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.regs.raddr1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [19]), + .O(\core.regs.raddr1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2 [4]), + .I2(\core.frontend.next_instr [24]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr2 [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.d_rs2 [3]), + .I2(\core.frontend.next_instr [23]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr2_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.d_rs2 [2]), + .I2(\core.frontend.next_instr [22]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr2_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.d_rs2 [1]), + .I2(\core.frontend.next_instr [21]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.regs.raddr2_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.d_rs2 [0]), + .I2(\core.frontend.next_instr [20]), + .I3(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2]), + .O(\core.regs.raddr2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/brams_map.v:212.4-224.3|/usr/local/bin/../share/yosys/ice40/brams_map.v:54.7-66.6" *) + SB_RAM40_4K #( + .INIT_0(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_1(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_2(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_3(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .READ_MODE(2'h0), + .WRITE_MODE(2'h0) + ) \core.regs.real_dualport_noreset.mem.0.0.0 ( + .MASK({ \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O }), + .RADDR({ 6'h00, \core.regs.raddr2 }), + .RCLK(clk), + .RCLKE(1'h1), + .RDATA(\core.regs.rdata2 [15:0]), + .RE(1'h1), + .WADDR({ 6'h00, \core.xm_rd }), + .WCLK(clk), + .WCLKE(\core.m_reg_wen ), + .WDATA(\core.m_result [15:0]), + .WE(1'h1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/brams_map.v:212.4-224.3|/usr/local/bin/../share/yosys/ice40/brams_map.v:54.7-66.6" *) + SB_RAM40_4K #( + .INIT_0(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_1(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_2(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_3(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .READ_MODE(2'h0), + .WRITE_MODE(2'h0) + ) \core.regs.real_dualport_noreset.mem.0.0.1 ( + .MASK({ \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O }), + .RADDR({ 6'h00, \core.regs.raddr1 }), + .RCLK(clk), + .RCLKE(1'h1), + .RDATA(\core.regs.rdata1 [15:0]), + .RE(1'h1), + .WADDR({ 6'h00, \core.xm_rd }), + .WCLK(clk), + .WCLKE(\core.m_reg_wen ), + .WDATA(\core.m_result [15:0]), + .WE(1'h1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/brams_map.v:212.4-224.3|/usr/local/bin/../share/yosys/ice40/brams_map.v:54.7-66.6" *) + SB_RAM40_4K #( + .INIT_0(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_1(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_2(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_3(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .READ_MODE(2'h0), + .WRITE_MODE(2'h0) + ) \core.regs.real_dualport_noreset.mem.1.0.0 ( + .MASK({ \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O }), + .RADDR({ 6'h00, \core.regs.raddr2 }), + .RCLK(clk), + .RCLKE(1'h1), + .RDATA(\core.regs.rdata2 [31:16]), + .RE(1'h1), + .WADDR({ 6'h00, \core.xm_rd }), + .WCLK(clk), + .WCLKE(\core.m_reg_wen ), + .WDATA(\core.m_result [31:16]), + .WE(1'h1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/brams_map.v:212.4-224.3|/usr/local/bin/../share/yosys/ice40/brams_map.v:54.7-66.6" *) + SB_RAM40_4K #( + .INIT_0(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_1(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_2(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_3(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx), + .READ_MODE(2'h0), + .WRITE_MODE(2'h0) + ) \core.regs.real_dualport_noreset.mem.1.0.1 ( + .MASK({ \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O , \core.m_reg_wen_SB_LUT4_I3_O }), + .RADDR({ 6'h00, \core.regs.raddr1 }), + .RCLK(clk), + .RCLKE(1'h1), + .RDATA(\core.regs.rdata1 [31:16]), + .RE(1'h1), + .WADDR({ 6'h00, \core.xm_rd }), + .WCLK(clk), + .WCLKE(\core.m_reg_wen ), + .WDATA(\core.m_result [31:16]), + .WE(1'h1) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [9]), + .I2(\core.frontend.cir [29]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [9]), + .O(\core.x_addr_sum [9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [8]), + .I2(\core.frontend.cir [28]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [8]), + .O(\core.x_addr_sum [8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [29]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [29]), + .O(\core.x_addr_sum [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [28]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [28]), + .O(\core.x_addr_sum [28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [27]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [27]), + .O(\core.x_addr_sum [27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [26]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [26]), + .O(\core.x_addr_sum [26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [25]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [25]), + .O(\core.x_addr_sum [25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [24]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [24]), + .O(\core.x_addr_sum [24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [23]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [23]), + .O(\core.x_addr_sum [23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [22]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [22]), + .O(\core.x_addr_sum [22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [21]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [21]), + .O(\core.x_addr_sum [21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [20]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [20]), + .O(\core.x_addr_sum [20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [7]), + .I2(\core.frontend.cir [27]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [7]), + .O(\core.x_addr_sum [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [19]), + .I2(\core.d_addr_offs [19]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [19]), + .O(\core.x_addr_sum [19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [18]), + .I2(\core.d_addr_offs [18]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [18]), + .O(\core.x_addr_sum [18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [17]), + .I2(\core.d_addr_offs [17]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [17]), + .O(\core.x_addr_sum [17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [16]), + .I2(\core.d_addr_offs [16]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [16]), + .O(\core.x_addr_sum [16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [15]), + .I2(\core.d_addr_offs [15]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [15]), + .O(\core.x_addr_sum [15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [14]), + .I2(\core.d_addr_offs [14]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [14]), + .O(\core.x_addr_sum [14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [13]), + .I2(\core.d_addr_offs [13]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [13]), + .O(\core.x_addr_sum [13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [12]), + .I2(\core.d_addr_offs [12]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [12]), + .O(\core.x_addr_sum [12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [11]), + .I2(\core.d_addr_offs [11]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [11]), + .O(\core.x_addr_sum [11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [10]), + .I2(\core.frontend.cir [30]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [10]), + .O(\core.x_addr_sum [10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [6]), + .I2(\core.frontend.cir [26]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [6]), + .O(\core.x_addr_sum [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [5]), + .I2(\core.frontend.cir [25]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [5]), + .O(\core.x_addr_sum [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [4]), + .I2(\core.d_addr_offs [4]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [4]), + .O(\core.x_addr_sum [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I2(\core.d_addr_offs [3]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [3]), + .O(\core.x_addr_sum [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [31]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [31]), + .O(\core.x_addr_sum [31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [30]), + .I2(\core.frontend.cir [31]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [30]), + .O(\core.x_addr_sum [30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_addr_sum_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I2(\core.d_addr_offs [2]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [2]), + .O(\core.x_addr_sum [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:608.32-608.87|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) \core.x_jump_misaligned_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.d_addr_offs [1]), + .I3(\core.d_addr_offs_SB_CARRY_I1_CO [1]), + .O(\core.x_jump_misaligned ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_addr_align_SB_DFFER_Q ( + .C(clk), + .D(\core.x_jump_misaligned ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_addr_align [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_addr_align_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.bus_haddr_d [0]), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_addr_align [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:885.1-909.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:9.57-9.103" *) + SB_DFFR \core.xm_delay_irq_entry_on_ls_dphase_SB_DFFR_Q ( + .C(clk), + .D(\core.xm_delay_irq_entry_on_ls_dphase_SB_DFFR_Q_D ), + .Q(\core.xm_delay_irq_entry_on_ls_dphase ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_delay_irq_entry_on_ls_dphase_SB_DFFR_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(bus_hold_aph_SB_LUT4_I2_O[0]), + .I3(bus_gnt_d_SB_LUT4_O_I2[1]), + .O(\core.xm_delay_irq_entry_on_ls_dphase_SB_DFFR_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.power_ctrl.stall_release_SB_LUT4_I2_O [1]), + .I3(\core.xm_delay_irq_entry_on_ls_dphase ), + .O(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h80ff) + ) \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1 ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2]), + .I1(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [0]), + .I2(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]), + .O(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0ee) + ) \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [2]), + .I2(\core.csr_u.mepc [2]), + .I3(\core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3]), + .O(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfe00) + ) \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.csr_u.irq_software_r_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.irq_software_r_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [1]), + .I3(\core.csr_u.mstatus_mie ), + .O(\core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" *) + SB_DFFES \core.xm_except_SB_DFFES_Q ( + .C(clk), + .D(\core.xm_except_SB_DFFES_Q_D ), + .E(d_hresp_SB_LUT4_I1_O), + .Q(\core.xm_except [3]), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" *) + SB_DFFES \core.xm_except_SB_DFFES_Q_1 ( + .C(clk), + .D(\core.xm_except_SB_DFFES_Q_1_D ), + .E(d_hresp_SB_LUT4_I1_O), + .Q(\core.xm_except [2]), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [0]), + .I2(\core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2 [1]), + .I3(\core.df_cir_use_SB_LUT4_I2_O [0]), + .O(\core.xm_except_SB_DFFES_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f8) + ) \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [3]), + .I2(\core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2 [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .O(\core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir_vld [1]), + .I2(\core.frontend.cir_vld [0]), + .I3(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[2]), + .O(\core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" *) + SB_DFFES \core.xm_except_SB_DFFES_Q_2 ( + .C(clk), + .D(\core.xm_except_SB_DFFES_Q_2_D ), + .E(d_hresp_SB_LUT4_I1_O), + .Q(\core.xm_except [1]), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f1) + ) \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O ( + .I0(\core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1 [4]), + .I2(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .I3(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I3 [3]), + .O(\core.xm_except_SB_DFFES_Q_2_D ) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1070.21-1070.42|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO ( + .CI(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [4]), + .CO(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1 [4]), + .I0(1'h0), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1070.21-1070.42|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO ( + .CI(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [2]), + .CO(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [4]), + .I0(1'h1), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [1]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1070.21-1070.42|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1 ( + .CI(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI [0]), + .CO(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [2]), + .I0(1'h0), + .I1(\core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ff) + ) \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(1'h0), + .I3(\core.xm_memop [0]), + .O(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hd000) + ) \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I3(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(\core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" *) + SB_DFFES \core.xm_except_SB_DFFES_Q_3 ( + .C(clk), + .D(\core.xm_except_SB_DFFES_Q_3_D ), + .E(d_hresp_SB_LUT4_I1_O), + .Q(\core.xm_except [0]), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h30ff) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [0]), + .I2(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [1]), + .I3(\core.df_cir_use_SB_LUT4_I2_O [0]), + .O(\core.xm_except_SB_DFFES_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I3(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1 [2]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I1(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .I3(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [3]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2]), + .I1(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2]), + .I2(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]), + .I3(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [3]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'heaac) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [1]), + .I2(\core.frontend.cir [20]), + .I3(\core.frontend.cir [21]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]), + .I3(\core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1 [0]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I3(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(\core.xm_except_SB_DFFES_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1 [0]), + .I3(\core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2 [1]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h33f0) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I1_O [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [0]), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h008f) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [2]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2 [2]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.frontend.cir [21]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I2(\core.frontend.cir [20]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_memop_SB_DFFER_Q ( + .C(clk), + .D(\core.xm_memop_SB_DFFER_Q_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_memop [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_memop_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.xm_memop_SB_DFFER_Q_1_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_memop [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_memop_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I3(\core.xm_memop_SB_DFFER_Q_1_D_SB_LUT4_O_I3 [2]), + .O(\core.xm_memop_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_memop_SB_DFFER_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .O(\core.xm_memop_SB_DFFER_Q_1_D_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_memop_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.xm_memop_SB_DFFER_Q_2_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_memop [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .I1(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .O(\core.xm_memop_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [0]), + .O(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h007f) + ) \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3]), + .O(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .O(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [14]), + .I3(\core.frontend.cir [13]), + .O(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [14]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 [2]), + .O(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I3(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [1]), + .O(\core.xm_memop_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [0]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .O(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .O(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:15.63-15.116" *) + SB_DFFES \core.xm_memop_SB_DFFES_Q ( + .C(clk), + .D(\core.xm_memop_SB_DFFES_Q_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_memop [4]), + .S(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3fff) + ) \core.xm_memop_SB_DFFES_Q_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I3(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_memop_SB_DFFES_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_memop_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_memop [4]), + .I2(\core.xm_memop [2]), + .I3(\core.xm_memop [1]), + .O(d_hwdata_SB_LUT4_O_27_I2[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rd_SB_DFFER_Q ( + .C(clk), + .D(\core.xm_rd_SB_DFFER_Q_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rd [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rd_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.xm_rd_SB_DFFER_Q_1_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rd [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_rd_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [10]), + .O(\core.xm_rd_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rd_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.xm_rd_SB_DFFER_Q_2_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rd [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_rd_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [9]), + .O(\core.xm_rd_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rd_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.xm_rd_SB_DFFER_Q_3_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rd [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_rd_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [8]), + .O(\core.xm_rd_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rd_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.xm_rd_SB_DFFER_Q_4_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rd [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_rd_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [7]), + .O(\core.xm_rd_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_rd_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.df_cir_use_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [11]), + .O(\core.xm_rd_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [31]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_1_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [30]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_10 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_10_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [21]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_10_D_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_10_I0 [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_10_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_11 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_11_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [20]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_11_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_11_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_12 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_12_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [19]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_12_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_12_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_13 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_13_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [18]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_13_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_13_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_14 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_14_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [17]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_14_D_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [0]), + .I1(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [1]), + .I2(\core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_14_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_15 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_15_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [16]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_15_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_15_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_16 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_16_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [15]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fbb) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_16_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [15]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [15]), + .I1(\core.alu.op_b_inv [15]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [16]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [0]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mtvec_reg [16]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [16]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [16]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [16]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [16]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [16]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [0]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [0]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [16]), + .I1(\core.alu.op_b_inv [16]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1 [1]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6cd4) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv [0]), + .I2(\core.alu.op_a [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h03ff) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0 [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [1]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_17 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_17_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [14]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fbb) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_17_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [3]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [0]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [14]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6dc4) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv [14]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.op_a [14]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [30]), + .I2(\core.alu.op_a [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [0]), + .I2(\core.alu.op_a [31]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I0 ( + .I0(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .O(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h10ff) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [12]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [1]), + .I1(\core.alu.op_b_inv [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fee) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff80) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0 ( + .I0(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_18 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_18_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [13]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_18_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [13]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0 ( + .I0(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [18]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1f00) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(\core.csr_u.meifa [2]), + .I1(\core.csr_u.irq_r [2]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 [3]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(\core.csr_u.mscratch [18]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [3]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mtvec_reg [18]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [18]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [18]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [18]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [18]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meifa [2]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meiea [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [18]), + .I1(\core.alu.op_b_inv [18]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [13]), + .I1(\core.alu.op_b_inv [13]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_19 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_19_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [12]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fbb) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_19_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [12]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3 [3]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6dc4) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv [12]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.op_a [12]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [19]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.mtvec_reg [19]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hef00) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [3]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [19]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [19]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h7000) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.meiea [19]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I2(dbg_data0_wdata[0]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [3]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [19]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [19]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(\core.csr_u.meiea [3]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I2(dbg_data0_wdata[0]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [3]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [3]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [3]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [19]), + .I1(\core.alu.op_b_inv [19]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [3]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [3]), + .I1(\core.alu.op_b_inv [3]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_1_D_SB_LUT4_O ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_1_I0 [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_1_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_2_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [29]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_20 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_20_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [11]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_20_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [11]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0 ( + .I0(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [0]), + .I1(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [1]), + .I2(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [2]), + .I3(\core.csr_u.meicontext_preempt_SB_LUT4_I1_O [3]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [20]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [20]), + .I1(\core.alu.op_b_inv [20]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3500) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6cd4) + ) \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.alu.op_b_inv [11]), + .I2(\core.alu.op_a [11]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_21 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_21_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [10]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_21_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_21_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [10]), + .I2(\core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [10]), + .I1(\core.alu.op_b_inv [10]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_22 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_22_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [9]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_22_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [9]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [3]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [22]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [22]), + .I1(\core.alu.op_b_inv [22]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h53ff) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.csr_u.meiea [22]), + .I1(\core.csr_u.meiea [6]), + .I2(dbg_data0_wdata[0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.csr_u.mepc [22]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [22]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [22]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [22]), + .I2(\core.csr_u.irq_r [6]), + .I3(dbg_data0_wdata[0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.meifa [22]), + .I2(\core.csr_u.meifa [6]), + .I3(dbg_data0_wdata[0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h03ff) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [9]), + .I1(\core.alu.op_b_inv [9]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_23 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_23_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [8]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_23_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [8]), + .I2(\core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [8]), + .I1(\core.alu.op_b_inv [8]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_24 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_24_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [7]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_24_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [7]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [24]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [8]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mtvec_reg [24]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [24]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I3(\core.csr_u.mepc [24]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [24]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [24]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [24]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [8]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [8]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [24]), + .I1(\core.alu.op_b_inv [24]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf033) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [7]), + .I1(\core.alu.op_b_inv [7]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_25 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_25_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [6]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_25_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O [0]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_25_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_26 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_26_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [5]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_26_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [5]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [5]), + .I1(\core.alu.op_b_inv [5]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [26]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [26]), + .I1(\core.alu.op_b_inv [26]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0ff) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.csr_u.mepc [26]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [26]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [26]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h70ff) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2 ( + .I0(\core.csr_u.meiea [26]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.irq_r [26]), + .I2(\core.csr_u.meifa [26]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]), + .I3(\core.csr_u.meiea [10]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [11]), + .I2(\core.csr_u.meifa [11]), + .I3(\core.csr_u.meiea [11]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.csr_u.irq_r [12]), + .I2(\core.csr_u.meifa [12]), + .I3(\core.csr_u.meiea [12]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0100) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_2 ( + .I0(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [0]), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.meifa [10]), + .I3(\core.csr_u.irq_r [10]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I1(\core.csr_u.meifa [10]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.csr_u.meiea [10]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [4]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [24]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [4]), + .I2(\core.mw_result [4]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [14]), + .I2(\core.alu.op_a [17]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [15]), + .I2(\core.alu.op_a [16]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [4]), + .I2(\core.alu.op_a [27]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [26]), + .I2(\core.alu.op_a [5]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [25]), + .I2(\core.alu.op_a [6]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [24]), + .I2(\core.alu.op_a [7]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [19]), + .I2(\core.alu.op_a [12]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [18]), + .I2(\core.alu.op_a [13]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [8]), + .I2(\core.alu.op_a [23]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [22]), + .I2(\core.alu.op_a [9]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [21]), + .I2(\core.alu.op_a [10]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [11]), + .I2(\core.alu.op_a [20]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [15]), + .I2(\core.alu.op_a [16]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [14]), + .I2(\core.alu.op_a [17]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [18]), + .I2(\core.alu.op_a [13]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [19]), + .I2(\core.alu.op_a [12]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [11]), + .I2(\core.alu.op_a [20]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [21]), + .I2(\core.alu.op_a [10]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [22]), + .I2(\core.alu.op_a [9]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [8]), + .I2(\core.alu.op_a [23]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_27 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_27_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_27_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0d00) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.sum [4]), + .I1(\core.alu.sub_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [3]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0 ( + .I0(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [3]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [27]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.meiea [11]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(\core.csr_u.mepc [27]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [3]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0777) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mscratch [27]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]), + .I3(\core.csr_u.mtvec_reg [27]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8f00) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1]), + .I1(\core.csr_u.meiea [27]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]), + .I3(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [27]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [27]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h035f) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.csr_u.irq_r [11]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.csr_u.meifa [11]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [27]), + .I1(\core.alu.op_b_inv [27]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [4]), + .I1(\core.alu.op_b_inv [4]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_28 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_28_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_30_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_28_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfc00) + ) \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]), + .O(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h11f0) + ) \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_29 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_29_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_29_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0d00) + ) \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.sum [2]), + .I1(\core.alu.sub_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [3]), + .O(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [3]), + .O(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [2]), + .I1(\core.alu.op_b_inv [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_2_I0 [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.alu.sub_SB_LUT4_I2_O [0]), + .I3(\core.alu.sum [29]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he0ee) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [1]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [3]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h11f0) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3500) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [1]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00cf) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_result [3]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0e00) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [3]), + .I2(\core.mw_result [3]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [23]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [24]), + .I2(\core.alu.op_a [7]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [25]), + .I2(\core.alu.op_a [6]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [0]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hccf0) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [2]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h008f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I1(\core.frontend.cir [22]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata2 [2]), + .I2(\core.mw_result [2]), + .I3(\core.d_rs2_predecoded_SB_LUT4_I1_5_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [26]), + .I2(\core.alu.op_a [5]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]), + .I2(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [28]), + .I2(\core.alu.op_a [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [29]), + .I2(\core.alu.op_a [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [4]), + .I2(\core.alu.op_a [27]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [29]), + .I2(\core.alu.op_a [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.alu.op_a [28]), + .I2(\core.alu.op_a [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [0]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.op_a [30]), + .I2(\core.alu.op_a [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(\core.alu.op_a [29]), + .I1(\core.alu.op_b_inv [29]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_3_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [28]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_30 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_30_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_28_I0 [0]), + .I2(\core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O_I2 [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_30_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcf00) + ) \core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_31 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_31_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_31_I0 [0]), + .I2(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2 [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_31_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'he000) + ) \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]), + .I2(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [2]), + .I3(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [3]), + .O(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb0bb) + ) \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [3]), + .O(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O [3]), + .O(\core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_3_D_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.csr_u.wdata_update_SB_LUT4_O_3_I0 [0]), + .I2(\core.csr_u.wdata_update_SB_LUT4_O_3_I0 [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_3_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_4_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [27]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_4_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_4_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_5 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_5_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [26]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_5_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_5_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_6 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_6_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [25]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_6_D_SB_LUT4_O ( + .I0(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [0]), + .I1(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [1]), + .I2(\core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_6_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_7 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_7_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [24]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_7_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_7_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_8 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_8_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [23]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0 [0]), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0 [1]), + .I2(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [0]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.alu.sub_SB_LUT4_I2_O [0]), + .I1(\core.alu.sum [23]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]), + .I3(\core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hbbb0) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3]), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00f3) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0fcc) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I2(\core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h330f) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]), + .I2(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I2(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [1]), + .I3(\core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9731) + ) \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.alu.op_a [23]), + .I1(\core.alu.op_b_inv [23]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [3]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .O(\core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1091.1-1107.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_result_SB_DFFER_Q_9 ( + .C(clk), + .D(\core.xm_result_SB_DFFER_Q_9_D ), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_result [22]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_9_D_SB_LUT4_O ( + .I0(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [0]), + .I1(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [1]), + .I2(\core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_9_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f77) + ) \core.xm_result_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [0]), + .I1(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]), + .O(\core.xm_result_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rs2_SB_DFFER_Q ( + .C(clk), + .D(\core.d_rs2 [4]), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rs2 [4]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rs2_SB_DFFER_Q_1 ( + .C(clk), + .D(\core.d_rs2 [3]), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rs2 [3]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rs2_SB_DFFER_Q_2 ( + .C(clk), + .D(\core.d_rs2 [2]), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rs2 [2]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rs2_SB_DFFER_Q_3 ( + .C(clk), + .D(\core.d_rs2 [1]), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rs2 [1]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_rs2_SB_DFFER_Q_4 ( + .C(clk), + .D(\core.d_rs2 [0]), + .E(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .Q(\core.xm_rs2 [0]), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hb00b) + ) \core.xm_rs2_SB_LUT4_I0 ( + .I0(\core.xm_rs2 [4]), + .I1(\core.mw_rd [4]), + .I2(\core.mw_rd [3]), + .I3(\core.xm_rs2 [3]), + .O(\core.xm_rs2_SB_LUT4_I0_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9009) + ) \core.xm_rs2_SB_LUT4_I1 ( + .I0(\core.mw_rd [0]), + .I1(\core.xm_rs2 [0]), + .I2(\core.mw_rd [1]), + .I3(\core.xm_rs2 [1]), + .O(\core.xm_rs2_SB_LUT4_I0_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h9000) + ) \core.xm_rs2_SB_LUT4_I1_1 ( + .I0(\core.mw_rd [2]), + .I1(\core.xm_rs2 [2]), + .I2(\core.xm_rs2_SB_LUT4_I0_O [2]), + .I3(\core.xm_rs2_SB_LUT4_I0_O [3]), + .O(\core.xm_rs2_SB_LUT4_I1_1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.xm_rs2_SB_LUT4_I1_1_O_SB_LUT4_O ( + .I0(\core.mw_rd [0]), + .I1(\core.mw_rd [1]), + .I2(\core.mw_rd [2]), + .I3(\core.mw_rd [3]), + .O(\core.xm_rs2_SB_LUT4_I1_1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf100) + ) \core.xm_rs2_SB_LUT4_I1_2 ( + .I0(\core.xm_rs2_SB_LUT4_I1_1_O [0]), + .I1(\core.xm_rs2 [4]), + .I2(\core.mw_rd [4]), + .I3(\core.xm_rs2_SB_LUT4_I1_1_O [3]), + .O(\core.xm_rs2_SB_LUT4_I1_2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_rs2_SB_LUT4_I1_2_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.xm_result [20]), + .I2(\core.mw_result [20]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_27_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) \core.xm_rs2_SB_LUT4_I1_2_O_SB_LUT4_I3_1 ( + .I0(1'h0), + .I1(\core.xm_result [4]), + .I2(\core.mw_result [4]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_27_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_core.v:1025.1-1075.4|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER \core.xm_sleep_wfi_SB_DFFER_Q ( + .C(clk), + .D(\core.xm_sleep_wfi_SB_DFFER_Q_D ), + .E(d_hresp_SB_LUT4_I1_O), + .Q(\core.xm_sleep_wfi ), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O ( + .I0(\core.df_cir_use_SB_LUT4_I2_O [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3 [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3 [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [3]), + .I3(\core.frontend.cir [14]), + .O(\core.alu.op_a_SB_LUT4_O_3_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h03ff) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [12]), + .I2(\core.frontend.cir [13]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fc) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [1]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [0]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h01ff) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_1 ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [0]), + .I1(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [1]), + .I2(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .I2(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [1]), + .I3(\core.frontend.cir [6]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [7]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [8]), + .I1(\core.frontend.cir [9]), + .I2(\core.frontend.cir [10]), + .I3(\core.frontend.cir [11]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h003f) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 [2]), + .I2(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [1]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 [2]), + .I3(\core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.xm_result [3]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.regs.rdata1 [3]), + .I2(\core.mw_result [3]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_7_O [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_O ( + .I0(\core.frontend.cir [12]), + .I1(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .I3(\core.frontend.cir [31]), + .O(\core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcfff) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [6]), + .I2(\core.frontend.cir [4]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.frontend.cir [2]), + .I1(\core.frontend.cir [3]), + .I2(\core.frontend.cir [0]), + .I3(\core.frontend.cir [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1 ( + .I0(\core.frontend.cir [13]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [1]), + .I2(\core.frontend.cir [12]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [4]), + .I2(\core.frontend.cir [5]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [14]), + .I3(\core.frontend.cir [13]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [12]), + .I2(\core.frontend.cir [6]), + .I3(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2 ( + .I0(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0]), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [1]), + .I3(\core.frontend.cir [12]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0700) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1 ( + .I0(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_4_I0 [0]), + .I2(\core.d_rs2_SB_LUT4_O_4_I0 [1]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 [2]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h07ff) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [1]), + .I3(\core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]), + .I3(\core.frontend.cir [6]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h1000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(\core.frontend.cir [5]), + .I1(\core.frontend.cir [6]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]), + .I3(\core.frontend.cir [4]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0a0c) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.xm_result [31]), + .I1(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [1]), + .I2(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [2]), + .I3(\core.d_rs1_predecoded_SB_LUT4_I1_4_O [3]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.frontend.cir [3]), + .I1(\core.frontend.cir [2]), + .I2(\core.frontend.cir [0]), + .I3(\core.frontend.cir [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [4]), + .I3(\core.frontend.cir [5]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [4]), + .I2(\core.frontend.cir [5]), + .I3(\core.frontend.cir [6]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h8000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 [1]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .I3(\core.frontend.cir [28]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3 [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 [1]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [0]), + .O(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 [0]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [2]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.frontend.cir [20]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [2]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h4000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(\core.frontend.cir [21]), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2]), + .I2(\core.frontend.cir [20]), + .I3(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]), + .I3(\core.frontend.cir [20]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [23]), + .I2(\core.frontend.cir [21]), + .I3(\core.frontend.cir [22]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.cir [28]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3 ( + .I0(1'h0), + .I1(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1]), + .I2(\core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [1]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [2]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(\core.frontend.cir [16]), + .I1(\core.frontend.cir [17]), + .I2(\core.frontend.cir [18]), + .I3(\core.frontend.cir [19]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0001) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_O_1 ( + .I0(\core.frontend.cir [27]), + .I1(\core.frontend.cir [25]), + .I2(\core.frontend.cir [24]), + .I3(\core.frontend.cir [26]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0003) + ) \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.cir [30]), + .I2(\core.frontend.cir [29]), + .I3(\core.frontend.cir [31]), + .O(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf300) + ) \core.xm_sleep_wfi_SB_LUT4_I1 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi ), + .I2(\core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [1]), + .I3(\core.power_ctrl.state [1]), + .O(pwrup_ack_SB_LUT4_I1_I3[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.x_addr_sum [31]), + .I2(dbg_sbus_addr[31]), + .I3(bus_gnt_s), + .O(d_haddr[31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.x_addr_sum [30]), + .I2(dbg_sbus_addr[30]), + .I3(bus_gnt_s), + .O(d_haddr[30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.x_addr_sum [21]), + .I2(dbg_sbus_addr[21]), + .I3(bus_gnt_s), + .O(d_haddr[21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.x_addr_sum [20]), + .I2(dbg_sbus_addr[20]), + .I3(bus_gnt_s), + .O(d_haddr[20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.x_addr_sum [19]), + .I2(dbg_sbus_addr[19]), + .I3(bus_gnt_s), + .O(d_haddr[19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.x_addr_sum [18]), + .I2(dbg_sbus_addr[18]), + .I3(bus_gnt_s), + .O(d_haddr[18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.x_addr_sum [17]), + .I2(dbg_sbus_addr[17]), + .I3(bus_gnt_s), + .O(d_haddr[17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.x_addr_sum [16]), + .I2(dbg_sbus_addr[16]), + .I3(bus_gnt_s), + .O(d_haddr[16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.x_addr_sum [15]), + .I2(dbg_sbus_addr[15]), + .I3(bus_gnt_s), + .O(d_haddr[15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.x_addr_sum [14]), + .I2(dbg_sbus_addr[14]), + .I3(bus_gnt_s), + .O(d_haddr[14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.x_addr_sum [13]), + .I2(dbg_sbus_addr[13]), + .I3(bus_gnt_s), + .O(d_haddr[13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.x_addr_sum [12]), + .I2(dbg_sbus_addr[12]), + .I3(bus_gnt_s), + .O(d_haddr[12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.x_addr_sum [29]), + .I2(dbg_sbus_addr[29]), + .I3(bus_gnt_s), + .O(d_haddr[29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.x_addr_sum [11]), + .I2(dbg_sbus_addr[11]), + .I3(bus_gnt_s), + .O(d_haddr[11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.x_addr_sum [10]), + .I2(dbg_sbus_addr[10]), + .I3(bus_gnt_s), + .O(d_haddr[10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.x_addr_sum [9]), + .I2(dbg_sbus_addr[9]), + .I3(bus_gnt_s), + .O(d_haddr[9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.x_addr_sum [8]), + .I2(dbg_sbus_addr[8]), + .I3(bus_gnt_s), + .O(d_haddr[8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.x_addr_sum [7]), + .I2(dbg_sbus_addr[7]), + .I3(bus_gnt_s), + .O(d_haddr[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.x_addr_sum [6]), + .I2(dbg_sbus_addr[6]), + .I3(bus_gnt_s), + .O(d_haddr[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.x_addr_sum [5]), + .I2(dbg_sbus_addr[5]), + .I3(bus_gnt_s), + .O(d_haddr[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.x_addr_sum [4]), + .I2(dbg_sbus_addr[4]), + .I3(bus_gnt_s), + .O(d_haddr[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.x_addr_sum [3]), + .I2(dbg_sbus_addr[3]), + .I3(bus_gnt_s), + .O(d_haddr[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.x_addr_sum [2]), + .I2(dbg_sbus_addr[2]), + .I3(bus_gnt_s), + .O(d_haddr[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.x_addr_sum [28]), + .I2(dbg_sbus_addr[28]), + .I3(bus_gnt_s), + .O(d_haddr[28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(\core.x_jump_misaligned ), + .I2(dbg_sbus_addr[1]), + .I3(bus_gnt_s), + .O(d_haddr[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(\core.bus_haddr_d [0]), + .I2(dbg_sbus_addr[0]), + .I3(bus_gnt_s), + .O(d_haddr[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.x_addr_sum [27]), + .I2(dbg_sbus_addr[27]), + .I3(bus_gnt_s), + .O(d_haddr[27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.x_addr_sum [26]), + .I2(dbg_sbus_addr[26]), + .I3(bus_gnt_s), + .O(d_haddr[26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.x_addr_sum [25]), + .I2(dbg_sbus_addr[25]), + .I3(bus_gnt_s), + .O(d_haddr[25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.x_addr_sum [24]), + .I2(dbg_sbus_addr[24]), + .I3(bus_gnt_s), + .O(d_haddr[24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.x_addr_sum [23]), + .I2(dbg_sbus_addr[23]), + .I3(bus_gnt_s), + .O(d_haddr[23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_haddr_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.x_addr_sum [22]), + .I2(dbg_sbus_addr[22]), + .I3(bus_gnt_s), + .O(d_haddr[22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffc0) + ) d_hresp_SB_LUT4_I1 ( + .I0(1'h0), + .I1(d_hresp), + .I2(bus_active_dph_d), + .I3(\core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(d_hresp_SB_LUT4_I1_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hsize_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hsize_SB_LUT4_O_I1[0]), + .I2(dbg_sbus_size[1]), + .I3(bus_gnt_s), + .O(d_hsize[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hsize_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(d_hsize_SB_LUT4_O_1_I1[0]), + .I2(dbg_sbus_size[0]), + .I3(bus_gnt_s), + .O(d_hsize[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00fc) + ) d_hsize_SB_LUT4_O_1_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[0]), + .I2(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[1]), + .I3(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[2]), + .O(d_hsize_SB_LUT4_O_1_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf800) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_I2 ( + .I0(d_hsize_SB_LUT4_O_1_I1[0]), + .I1(\core.bus_haddr_d [0]), + .I2(d_hsize_SB_LUT4_O_I1[0]), + .I3(d_hsize_SB_LUT4_O_1_I1[3]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfac0) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O ( + .I0(\core.frontend.cir_bus_err [1]), + .I1(\core.frontend.cir_vld [0]), + .I2(\core.frontend.cir_bus_err [0]), + .I3(\core.frontend.cir_vld [1]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [0]), + .I3(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [1]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0071) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[1]), + .I1(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[0]), + .I2(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[2]), + .I3(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I3[3]), + .O(d_hsize_SB_LUT4_O_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3f00) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O [1]), + .I3(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [2]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hc300) + ) d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [0]), + .I2(\core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1]), + .I3(\core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [1]), + .O(d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I3[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0300) + ) d_htrans_SB_LUT4_I3 ( + .I0(1'h0), + .I1(d_hready), + .I2(d_hresp), + .I3(d_htrans[1]), + .O(bus_hold_aph_SB_DFFR_Q_D) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hfff0) + ) d_htrans_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(bus_gnt_d), + .I3(bus_gnt_s), + .O(d_htrans[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O ( + .I0(d_hwdata_SB_LUT4_O_I0[0]), + .I1(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[31]), + .I3(bus_active_dph_s), + .O(d_hwdata[31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_1 ( + .I0(d_hwdata_SB_LUT4_O_1_I0[0]), + .I1(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[30]), + .I3(bus_active_dph_s), + .O(d_hwdata[30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[21]), + .I2(d_hwdata_SB_LUT4_O_10_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_10_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_10_I2_SB_LUT4_O_I1[0]), + .I2(d_hwdata_SB_LUT4_O_26_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_10_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_10_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [21]), + .I2(\core.mw_result [21]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_10_I2_SB_LUT4_O_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[20]), + .I2(d_hwdata_SB_LUT4_O_11_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_11_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_27_I2[0]), + .I2(d_hwdata_SB_LUT4_O_27_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_11_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[19]), + .I2(d_hwdata_SB_LUT4_O_12_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_12_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_12_I2_SB_LUT4_O_I1[0]), + .I2(d_hwdata_SB_LUT4_O_28_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_12_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_12_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [19]), + .I2(\core.mw_result [19]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_12_I2_SB_LUT4_O_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[18]), + .I2(d_hwdata_SB_LUT4_O_13_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_13_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_13_I2_SB_LUT4_O_I1[0]), + .I2(d_hwdata_SB_LUT4_O_29_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_13_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_13_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [18]), + .I2(\core.mw_result [18]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_13_I2_SB_LUT4_O_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[17]), + .I2(d_hwdata_SB_LUT4_O_14_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_14_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_30_I2[0]), + .I2(d_hwdata_SB_LUT4_O_30_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_14_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[16]), + .I2(d_hwdata_SB_LUT4_O_15_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_15_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_31_I2[0]), + .I2(d_hwdata_SB_LUT4_O_31_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_15_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_16 ( + .I0(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[0]), + .I1(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[15]), + .I3(bus_active_dph_s), + .O(d_hwdata[15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_17 ( + .I0(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[0]), + .I1(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[14]), + .I3(bus_active_dph_s), + .O(d_hwdata[14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_18 ( + .I0(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[0]), + .I1(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[13]), + .I3(bus_active_dph_s), + .O(d_hwdata[13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_19 ( + .I0(d_hwdata_SB_LUT4_O_19_I0[0]), + .I1(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[12]), + .I3(bus_active_dph_s), + .O(d_hwdata[12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_19_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0 ( + .I0(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2[0]), + .I1(d_hwdata_SB_LUT4_O_27_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_result [28]), + .I1(\core.mw_result [28]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [12]), + .I2(\core.mw_result [12]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_1_I0_SB_LUT4_O ( + .I0(\core.xm_result [30]), + .I1(\core.mw_result [30]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_1_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_2 ( + .I0(d_hwdata_SB_LUT4_O_2_I0[0]), + .I1(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[29]), + .I3(bus_active_dph_s), + .O(d_hwdata[29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_20 ( + .I0(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[0]), + .I1(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[11]), + .I3(bus_active_dph_s), + .O(d_hwdata[11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_21 ( + .I0(d_hwdata_SB_LUT4_O_21_I0[0]), + .I1(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[10]), + .I3(bus_active_dph_s), + .O(d_hwdata[10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_21_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0 ( + .I0(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2[0]), + .I1(d_hwdata_SB_LUT4_O_29_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_result [26]), + .I1(\core.mw_result [26]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [10]), + .I2(\core.mw_result [10]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_22 ( + .I0(d_hwdata_SB_LUT4_O_22_I0[0]), + .I1(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[9]), + .I3(bus_active_dph_s), + .O(d_hwdata[9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_22_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0 ( + .I0(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2[0]), + .I1(d_hwdata_SB_LUT4_O_30_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_result [25]), + .I1(\core.mw_result [25]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [9]), + .I2(\core.mw_result [9]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_23 ( + .I0(d_hwdata_SB_LUT4_O_23_I0[0]), + .I1(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[8]), + .I3(bus_active_dph_s), + .O(d_hwdata[8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_23_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0 ( + .I0(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2[0]), + .I1(d_hwdata_SB_LUT4_O_31_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O ( + .I0(\core.xm_result [24]), + .I1(\core.mw_result [24]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [8]), + .I2(\core.mw_result [8]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[7]), + .I2(d_hwdata_SB_LUT4_O_24_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1 ( + .I0(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0[0]), + .I1(d_hwdata_SB_LUT4_O_24_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [15]), + .I2(\core.mw_result [15]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [7]), + .I2(\core.mw_result [7]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_24_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[6]), + .I2(d_hwdata_SB_LUT4_O_25_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1 ( + .I0(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0[0]), + .I1(d_hwdata_SB_LUT4_O_25_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [14]), + .I2(\core.mw_result [14]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [6]), + .I2(\core.mw_result [6]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_25_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[5]), + .I2(d_hwdata_SB_LUT4_O_26_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1 ( + .I0(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0[0]), + .I1(d_hwdata_SB_LUT4_O_26_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [13]), + .I2(\core.mw_result [13]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [5]), + .I2(\core.mw_result [5]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_26_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[4]), + .I2(d_hwdata_SB_LUT4_O_27_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[3]), + .I2(d_hwdata_SB_LUT4_O_28_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcaff) + ) d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1 ( + .I0(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0[0]), + .I1(d_hwdata_SB_LUT4_O_28_I2[1]), + .I2(\core.xm_memop [0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [11]), + .I2(\core.mw_result [11]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h000f) + ) d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0[0]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [3]), + .I2(\core.mw_result [3]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_28_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[2]), + .I2(d_hwdata_SB_LUT4_O_29_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_29_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [2]), + .I2(\core.mw_result [2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_29_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_2_I0_SB_LUT4_O ( + .I0(\core.xm_result [29]), + .I1(\core.mw_result [29]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_2_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_3 ( + .I0(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]), + .I1(d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[28]), + .I3(bus_active_dph_s), + .O(d_hwdata[28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[1]), + .I2(d_hwdata_SB_LUT4_O_30_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_30_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [17]), + .I2(\core.mw_result [17]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_30_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_30_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result [1]), + .I2(\core.mw_result [1]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_30_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[0]), + .I2(d_hwdata_SB_LUT4_O_31_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_31_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [16]), + .I2(\core.mw_result [16]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_31_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_31_I2_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.xm_result [0]), + .I2(\core.mw_result [0]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_31_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_4 ( + .I0(d_hwdata_SB_LUT4_O_4_I0[0]), + .I1(d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[1]), + .I2(dbg_sbus_wdata[27]), + .I3(bus_active_dph_s), + .O(d_hwdata[27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_4_I0_SB_LUT4_O ( + .I0(\core.xm_result [27]), + .I1(\core.mw_result [27]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_4_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_5 ( + .I0(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]), + .I1(d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[26]), + .I3(bus_active_dph_s), + .O(d_hwdata[26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_6 ( + .I0(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]), + .I1(d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[25]), + .I3(bus_active_dph_s), + .O(d_hwdata[25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0bb) + ) d_hwdata_SB_LUT4_O_7 ( + .I0(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[0]), + .I1(d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1]), + .I2(dbg_sbus_wdata[24]), + .I3(bus_active_dph_s), + .O(d_hwdata[24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[23]), + .I2(d_hwdata_SB_LUT4_O_8_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_8_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_8_I2_SB_LUT4_O_I1[0]), + .I2(d_hwdata_SB_LUT4_O_24_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_8_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_8_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [23]), + .I2(\core.mw_result [23]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_8_I2_SB_LUT4_O_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hcc0f) + ) d_hwdata_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(dbg_sbus_wdata[22]), + .I2(d_hwdata_SB_LUT4_O_9_I2[1]), + .I3(bus_active_dph_s), + .O(d_hwdata[22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwdata_SB_LUT4_O_9_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hwdata_SB_LUT4_O_9_I2_SB_LUT4_O_I1[0]), + .I2(d_hwdata_SB_LUT4_O_25_I2[1]), + .I3(d_hwdata_SB_LUT4_O_27_I2[2]), + .O(d_hwdata_SB_LUT4_O_9_I2[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f33) + ) d_hwdata_SB_LUT4_O_9_I2_SB_LUT4_O_I1_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.xm_result [22]), + .I2(\core.mw_result [22]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_9_I2_SB_LUT4_O_I1[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0c0a) + ) d_hwdata_SB_LUT4_O_I0_SB_LUT4_O ( + .I0(\core.xm_result [31]), + .I1(\core.mw_result [31]), + .I2(d_hwdata_SB_LUT4_O_27_I2[2]), + .I3(\core.xm_rs2_SB_LUT4_I1_2_O [2]), + .O(d_hwdata_SB_LUT4_O_I0[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) d_hwrite_SB_LUT4_O ( + .I0(1'h0), + .I1(d_hsize_SB_LUT4_O_I1_SB_LUT4_I2_O[0]), + .I2(dbg_sbus_write), + .I3(bus_gnt_s), + .O(d_hwrite) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [1]), + .O(dbg_data0_wdata[31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_19_I2 [1]), + .O(dbg_data0_wdata[30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_7_I2 [1]), + .O(dbg_data0_wdata[21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_13_I2 [0]), + .O(dbg_data0_wdata[20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_12_I2 [1]), + .O(dbg_data0_wdata[19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_2_I2 [1]), + .O(dbg_data0_wdata[18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_20_I2 [1]), + .O(dbg_data0_wdata[17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_11_I2 [1]), + .O(dbg_data0_wdata[16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_15_I2 [1]), + .O(dbg_data0_wdata[15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_10_I2 [1]), + .O(dbg_data0_wdata[14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_21_I2 [1]), + .O(dbg_data0_wdata[13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_28_I2 [1]), + .O(dbg_data0_wdata[12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_9_I2 [0]), + .O(dbg_data0_wdata[29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_24_I2 [1]), + .O(dbg_data0_wdata[11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_26_I2 [1]), + .O(dbg_data0_wdata[10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_14_I2 [1]), + .O(dbg_data0_wdata[9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_31_I2 [1]), + .O(dbg_data0_wdata[8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_27_I2 [1]), + .O(dbg_data0_wdata[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_5_I2 [1]), + .O(dbg_data0_wdata[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_25_I2 [1]), + .O(dbg_data0_wdata[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) dbg_data0_wdata_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_4_I2 [1]), + .I2(\core.regs.raddr1_SB_LUT4_O_I1 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .O(dbg_data0_wdata[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) dbg_data0_wdata_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_17_I2 [1]), + .I2(dbg_data0_wdata_SB_LUT4_O_28_I2[0]), + .I3(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .O(dbg_data0_wdata[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) dbg_data0_wdata_SB_LUT4_O_28_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [17]), + .O(dbg_data0_wdata_SB_LUT4_O_28_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) dbg_data0_wdata_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [0]), + .I2(dbg_data0_wdata_SB_LUT4_O_29_I2[0]), + .I3(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .O(dbg_data0_wdata[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) dbg_data0_wdata_SB_LUT4_O_29_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [18]), + .O(dbg_data0_wdata_SB_LUT4_O_29_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_22_I2 [0]), + .O(dbg_data0_wdata[28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) dbg_data0_wdata_SB_LUT4_O_30 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_I2 [1]), + .I2(\core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [0]), + .I3(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .O(dbg_data0_wdata[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) dbg_data0_wdata_SB_LUT4_O_31 ( + .I0(1'h0), + .I1(\core.alu.op_a_SB_LUT4_O_18_I3 [1]), + .I2(dbg_data0_wdata_SB_LUT4_O_31_I2[0]), + .I3(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .O(dbg_data0_wdata[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'h3000) + ) dbg_data0_wdata_SB_LUT4_O_31_I2_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [0]), + .I2(\core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]), + .I3(\core.frontend.cir [15]), + .O(dbg_data0_wdata_SB_LUT4_O_31_I2[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_23_I2 [0]), + .O(dbg_data0_wdata[27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_6_I2 [1]), + .O(dbg_data0_wdata[26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_8_I2 [0]), + .O(dbg_data0_wdata[25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_16_I2 [1]), + .O(dbg_data0_wdata[24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_3_I2 [1]), + .O(dbg_data0_wdata[23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_data0_wdata_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.alu.op_a_SB_LUT4_O_3_I2 [0]), + .I3(\core.alu.op_a_SB_LUT4_O_29_I2 [0]), + .O(dbg_data0_wdata[22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) dbg_sbus_err_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hresp), + .I3(bus_active_dph_s), + .O(dbg_sbus_err) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) dbg_sbus_rdy_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(d_hready), + .I3(bus_active_dph_s), + .O(dbg_sbus_rdy) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dbg_sbus_vld_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(bus_active_dph_s), + .I3(dbg_sbus_vld), + .O(bus_gnt_s_SB_LUT4_O_I1[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:193.1-197.37|/usr/local/bin/../share/yosys/ice40/ff_map.v:14.63-14.116" *) + SB_DFFER dphase_active_i_SB_DFFER_Q ( + .C(clk), + .D(\core.frontend.mem_addr_vld ), + .E(i_hready), + .Q(dphase_active_i), + .R(rst_n_SB_LUT4_I3_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) dphase_active_i_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(i_hready), + .I3(dphase_active_i), + .O(dphase_active_i_SB_LUT4_I3_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'h0f00) + ) dphase_active_i_SB_LUT4_I3_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.frontend.mem_addr_hold ), + .I3(\core.frontend.mem_addr_vld ), + .O(dphase_active_i_SB_LUT4_I3_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [31]), + .I2(\core.decode_u.f_jump_target [31]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[31]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [30]), + .I2(\core.decode_u.f_jump_target [30]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[30]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [21]), + .I2(\core.decode_u.f_jump_target [21]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [20]), + .I2(\core.decode_u.f_jump_target [20]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [19]), + .I2(\core.decode_u.f_jump_target [19]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [18]), + .I2(\core.decode_u.f_jump_target [18]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [17]), + .I2(\core.decode_u.f_jump_target [17]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [16]), + .I2(\core.decode_u.f_jump_target [16]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [15]), + .I2(\core.decode_u.f_jump_target [15]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [14]), + .I2(\core.decode_u.f_jump_target [14]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [13]), + .I2(\core.decode_u.f_jump_target [13]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [12]), + .I2(\core.decode_u.f_jump_target [12]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [29]), + .I2(\core.decode_u.f_jump_target [29]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [11]), + .I2(\core.decode_u.f_jump_target [11]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [10]), + .I2(\core.decode_u.f_jump_target [10]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [9]), + .I2(\core.decode_u.f_jump_target [9]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [8]), + .I2(\core.decode_u.f_jump_target [8]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [7]), + .I2(\core.decode_u.f_jump_target [7]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [6]), + .I2(\core.decode_u.f_jump_target [6]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [5]), + .I2(\core.decode_u.f_jump_target [5]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [4]), + .I2(\core.decode_u.f_jump_target [4]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [3]), + .I2(\core.decode_u.f_jump_target [3]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_29 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [2]), + .I2(\core.decode_u.f_jump_target [2]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [28]), + .I2(\core.decode_u.f_jump_target [28]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [27]), + .I2(\core.decode_u.f_jump_target [27]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [26]), + .I2(\core.decode_u.f_jump_target [26]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [25]), + .I2(\core.decode_u.f_jump_target [25]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [24]), + .I2(\core.decode_u.f_jump_target [24]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [23]), + .I2(\core.decode_u.f_jump_target [23]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf0cc) + ) i_haddr_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(\core.frontend.fetch_addr [22]), + .I2(\core.decode_u.f_jump_target [22]), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_haddr[22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hffc0) + ) i_hready_SB_LUT4_I2 ( + .I0(1'h0), + .I1(\core.frontend.mem_addr_vld ), + .I2(i_hready), + .I3(\core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]), + .O(i_hready_SB_LUT4_I2_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) i_hready_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(dphase_active_i_SB_LUT4_I3_O[0]), + .I3(i_hready), + .O(i_hready_SB_LUT4_I3_O) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0 ( + .CI(1'h0), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[1]), + .I0(i_hready_SB_LUT4_I3_O), + .I1(\core.decode_u.f_jump_target [2]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[9]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[10]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [11]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_1 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[8]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[9]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [10]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_10 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[26]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[27]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [28]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_11 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[25]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[26]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [27]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_12 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[24]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[25]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [26]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_13 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[23]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[24]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [25]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_14 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[22]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[23]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [24]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_15 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[21]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[22]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [23]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_16 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[20]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[21]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [22]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_17 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[1]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[2]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [3]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_18 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[19]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[20]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [21]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_19 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[18]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[19]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [20]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_2 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[7]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[8]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [9]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_20 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[17]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[18]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [19]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_21 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[16]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[17]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [18]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_22 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[15]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[16]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [17]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_23 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[14]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[15]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [16]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_24 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[13]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[14]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [15]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_25 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[12]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[13]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [14]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_26 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[11]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[12]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [13]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_27 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[10]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[11]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [12]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_3 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[6]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[7]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [8]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_4 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[5]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[6]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [7]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_5 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[4]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[5]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [6]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_6 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[3]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[4]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [5]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_7 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[2]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[3]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [4]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_8 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[28]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[29]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [30]) + ); + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4" *) + SB_CARRY i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO_SB_CARRY_CO_9 ( + .CI(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[27]), + .CO(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[28]), + .I0(1'h0), + .I1(\core.decode_u.f_jump_target [29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1 ( + .I0(1'h0), + .I1(i_hready_SB_LUT4_I3_O), + .I2(\core.decode_u.f_jump_target [2]), + .I3(1'h0), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [11]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[9]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_1 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [10]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[8]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_10 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [29]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[27]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[27]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_11 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [28]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[26]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[26]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_12 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [27]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[25]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[25]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_13 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [26]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[24]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[24]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_14 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [25]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[23]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[23]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_15 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [24]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[22]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[22]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_16 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [23]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[21]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[21]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_17 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [22]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[20]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[20]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_18 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [3]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[1]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_19 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [21]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[19]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[19]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_2 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [9]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[7]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_20 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [20]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[18]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[18]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_21 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [19]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[17]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[17]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_22 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [18]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[16]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[16]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_23 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [17]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[15]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[15]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_24 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [16]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[14]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[14]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_25 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [15]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[13]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[13]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_26 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [14]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[12]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[12]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_27 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [13]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[11]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[11]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_28 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [12]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[10]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[10]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_3 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [8]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[6]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_4 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [7]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[5]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_5 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [6]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[4]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_6 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [5]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[3]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_7 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [4]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[2]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_8 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [31]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[29]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[29]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/luke/proj/hazard3/hdl/hazard3_cpu_2port.v:125.3-180.2|/home/luke/proj/hazard3/hdl/hazard3_frontend.v:266.19-266.77|/home/luke/proj/hazard3/hdl/hazard3_core.v:131.3-175.2|/usr/local/bin/../share/yosys/ice40/arith_map.v:62.5-70.4|/usr/local/bin/../share/yosys/ice40/cells_map.v:26.33-27.52" *) + SB_LUT4 #( + .LUT_INIT(16'h6996) + ) i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O_SB_LUT4_O_9 ( + .I0(1'h0), + .I1(1'h0), + .I2(\core.decode_u.f_jump_target [30]), + .I3(i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[28]), + .O(i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[28]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:22.34-23.52" *) + SB_LUT4 #( + .LUT_INIT(16'hff30) + ) pwrup_ack_SB_LUT4_I1 ( + .I0(1'h0), + .I1(pwrup_ack), + .I2(\core.power_ctrl.state [2]), + .I3(pwrup_ack_SB_LUT4_I1_I3[2]), + .O(pwrup_ack_SB_LUT4_I1_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:17.34-18.52" *) + SB_LUT4 #( + .LUT_INIT(16'hf000) + ) pwrup_ack_SB_LUT4_I2 ( + .I0(1'h0), + .I1(1'h0), + .I2(pwrup_ack), + .I3(\core.power_ctrl.state [2]), + .O(pwrup_ack_SB_LUT4_I2_O) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/ice40/cells_map.v:12.34-13.52" *) + SB_LUT4 #( + .LUT_INIT(16'h00ff) + ) rst_n_SB_LUT4_I3 ( + .I0(1'h0), + .I1(1'h0), + .I2(1'h0), + .I3(rst_n), + .O(rst_n_SB_LUT4_I3_O) + ); + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3] }; + assign \core.d_rs1_predecoded_SB_LUT4_I1_4_O [0] = \core.xm_result [31]; + assign { \core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1_I1 [3:2], \core.alu.op_b_inv_SB_LUT4_O_5_I1_SB_LUT4_O_1_I1 [0] } = { \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1], \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [26] }; + assign \core.d_rs1_predecoded_SB_LUT4_I1_7_O [1:0] = { \core.mw_result [31], \core.regs.rdata1 [31] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.d_rs1_predecoded_SB_LUT4_I1_6_O [1:0] = { \core.d_rs1_predecoded [3], \core.mw_rd [3] }; + assign \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] = \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]; + assign { \core.m_result_SB_LUT4_O_3_I2 [2], \core.m_result_SB_LUT4_O_3_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [29] }; + assign \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [0] }; + assign \core.d_addr_offs_SB_LUT4_O_13_I1 [1] = \core.frontend.cir [20]; + assign \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1:0] = { \core.alu.sub_SB_LUT4_I2_O [0], \core.alu.sum [2] }; + assign \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0], \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0] }; + assign \core.xm_result_SB_DFFER_Q_29_D_SB_LUT4_O_I1 [2:1] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_O [0] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign \core.d_rs1_predecoded_SB_LUT4_I1_O [1:0] = \core.d_rs1_predecoded [1:0]; + assign \core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [1] = \core.df_cir_use [1]; + assign { \core.alu.op_a_SB_LUT4_O_6_I2 [2], \core.alu.op_a_SB_LUT4_O_6_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [26] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_22_I0 [3:1] = { dbg_data0_wdata[9], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.d_rs1_predecoded_SB_LUT4_I1_3_O [1:0] = { \core.d_rs1_predecoded [3], \core.xm_rd [3] }; + assign { \core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_6_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [26] }; + assign \core.alu.op_a_SB_LUT4_O_31_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign { \core.m_result_SB_LUT4_O_8_I2 [2], \core.m_result_SB_LUT4_O_8_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [24] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [8] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_11_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_11_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [21] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [8] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_I3 [2:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [23] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0 [3:1] = { dbg_data0_wdata[8], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_8_I2 [3:1] = { \core.alu.op_a [23], \core.alu.op_a [18], \core.alu.op_b_inv_SB_LUT4_O_13_I2 [0] }; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 [2:1] = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O [0], \core.csr_u.wdata_update [8] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0]; + assign { \core.alu.op_a_SB_LUT4_O_2_I2 [2], \core.alu.op_a_SB_LUT4_O_2_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [18] }; + assign { bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[2], bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1], \core.decode_u.cir_lock_prev }; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 [2:1] = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O [0], \core.csr_u.wdata_update [6] }; + assign { \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 [3], \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_O_I1 [0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1] }; + assign \core.csr_u.irq_timer_r_SB_LUT4_I3_O [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [7] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_24_I0_SB_LUT4_O_I2 [1:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3], \core.csr_u.meicontext_irq [3] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_24_I0 [3:1] = { dbg_data0_wdata[7], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 [2:1] = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O [0], \core.csr_u.wdata_update [7] }; + assign { \core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_2_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [18] }; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign \core.alu.op_a_SB_LUT4_O_25_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2 [0], \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0] }; + assign { \core.m_result_SB_LUT4_O_5_I2 [2], \core.m_result_SB_LUT4_O_5_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [27] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0 [3:1] = { dbg_data0_wdata[5], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 [1:0] = { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [11] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2] = \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0]; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_20_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_20_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [12] }; + assign \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [3:1] = { \core.xm_rd [0], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1], \core.frontend.cir [15] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0], \core.csr_u.mcause_code [2] }; + assign \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_I3 [0] = \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0]; + assign { \core.d_rs1_predecoded_SB_LUT4_I1_7_O_SB_LUT4_I3_O [3:2], \core.d_rs1_predecoded_SB_LUT4_I1_7_O_SB_LUT4_I3_O [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [23] }; + assign \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I2 [1:0] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O [2] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [0] } = { \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [1], \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0] }; + assign \core.csr_u.mstatus_mprv_SB_LUT4_I3_O [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [17] }; + assign { \core.m_result_SB_LUT4_O_2_I2 [2], \core.m_result_SB_LUT4_O_2_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [30] }; + assign \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O [2] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I1_O [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I1_O [0] } = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2:1]; + assign \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0], \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [0] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 [2]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign { \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [23] }; + assign \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1], d_hrdata[26] }; + assign { \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1] }; + assign \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O_SB_LUT4_O_I2 [1] = \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [1:0] = { \core.csr_u.wdata_update [16], \core.csr_u.meifa [0] }; + assign \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1 [1] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [2]; + assign \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [0] = \core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]; + assign \core.m_result_SB_LUT4_O_29_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1], d_hrdata[2] }; + assign { \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [3:2], \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [0] } = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2:1], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2] }; + assign \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0], \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign \core.d_rs2_SB_LUT4_O_2_I3 [2:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0], \core.d_rs2_SB_LUT4_O_4_I0 [1:0] }; + assign \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [3:2] = { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1], \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 [1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_13_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [18] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0], \core.csr_u.mscratch [2] }; + assign \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.meifa [4] }; + assign \core.d_rs2_SB_LUT4_O_3_I3 [2:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0], \core.d_rs2_SB_LUT4_O_4_I0 [1:0] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2_SB_LUT4_I2_I3 [2:0] = { \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [2], \core.frontend.mem_addr_hold_SB_LUT4_I2_O [0], \core.csr_u.mie [3] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_28_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [19], \core.csr_u.meifa [3] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign { \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [3], \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 [3:2], \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2 [0] } = { dbg_data0_wdata[0], \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0], \core.csr_u.irq_r [23] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_29_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [18], \core.csr_u.meifa [2] }; + assign \core.d_rs2_SB_LUT4_O_I1_SB_LUT4_O_I2 [1] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [1]; + assign { \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [2], \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0] } = { \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [2], \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [0] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_24_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [23], \core.csr_u.meifa [7] }; + assign \core.xm_memop_SB_DFFER_Q_D_SB_LUT4_O_I3 [3:2] = { \core.xm_rd [4], \core.d_rs2 [4] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] = \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [0]; + assign \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [0] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [0]; + assign \core.csr_u.mie_SB_DFFER_Q_E [1] = \core.frontend.mem_addr_hold_SB_LUT4_I2_O [0]; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O [0] = \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]; + assign \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_I2_I0 [3:2] = { \core.alu.op_a [21], \core.alu.op_b_inv_SB_LUT4_O_10_I2 [0] }; + assign { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [3], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3 [0] = \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [1]; + assign \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0], \core.csr_u.mscratch [21] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [22], \core.csr_u.meifa [6] }; + assign \core.alu.op_a_SB_LUT4_O_13_I2 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2], \core.decode_u.pc [20] }; + assign { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1] }; + assign { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 [3], \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0 [1] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0], \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [0] = \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]; + assign \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_I0 [2] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]; + assign \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign { \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [2], \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2] }; + assign \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.alu.sum [29], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign \core.d_rs2_SB_LUT4_O_4_I3 [2:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0], \core.d_rs2_SB_LUT4_O_4_I0 [1:0] }; + assign \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_O [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign { \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_10_I2_SB_LUT4_O_I0_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [21] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [2] }; + assign \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [3:2] = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O [3] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_1_I2[1] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]; + assign \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] = \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [0]; + assign \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I2_O [2]; + assign \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1 [2:1] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_30_I0 [0] }; + assign { \core.alu.op_a_SB_LUT4_O_7_I2 [2], \core.alu.op_a_SB_LUT4_O_7_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [21] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.m_reg_wen_SB_LUT4_O_I2 [2] = \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3 [3]; + assign { \core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_26_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [21], \core.csr_u.meifa [5] }; + assign { \core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_7_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [21] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [3], \core.csr_u.wdata_update_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [30], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [1:0] = \core.xm_rd [1:0]; + assign \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign { \core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_21_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [26], \core.csr_u.meifa [10] }; + assign \core.d_addr_offs_SB_LUT4_O_8_I3_SB_LUT4_O_I3 [2:0] = { \core.frontend.cir [6], \core.d_addr_offs_SB_LUT4_O_9_I3 [2], \core.frontend.cir [7] }; + assign \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.frontend.next_instr_SB_LUT4_O_11_I3 [1:0] = { \core.frontend.fifo_mem[0] [20], \core.frontend.buf_level_SB_LUT4_I3_I2 [1] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [24], \core.csr_u.meifa [8] }; + assign \core.d_rs2_SB_LUT4_O_4_I0 [2] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0]; + assign { \core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_22_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [25], \core.csr_u.meifa [9] }; + assign \core.csr_u.mstatus_mprv_SB_DFFER_Q_E [1] = \core.frontend.mem_addr_hold_SB_LUT4_I2_O [1]; + assign \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O [2] = \core.df_cir_use_SB_LUT4_I2_O [2]; + assign { \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [30], \core.csr_u.meifa [14] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [3:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [0] }; + assign \core.alu.op_a_SB_LUT4_O_24_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign { \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [28], \core.csr_u.meifa [12] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1_I1 [3:2], \core.alu.op_b_inv_SB_LUT4_O_11_I0_SB_LUT4_O_1_I1 [0] } = { \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1], \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [20] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_1_I1 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0] }; + assign \core.d_addr_offs_SB_LUT4_O_8_I3 [1:0] = { \core.frontend.cir [20], \core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [2] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_20_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [27], \core.csr_u.meifa [11] }; + assign { \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [18], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [0] } = { \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] }; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0], \core.csr_u.mscratch [18] }; + assign \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1], d_hrdata[24] }; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] = \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]; + assign d_hwdata_SB_LUT4_O_12_I2_SB_LUT4_O_I1[2:1] = { d_hwdata_SB_LUT4_O_27_I2[2], d_hwdata_SB_LUT4_O_28_I2[1] }; + assign { \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2], \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [0] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [0]; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2], \core.csr_u.meiea [8], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0]; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1:0] = { \core.alu.sub_SB_LUT4_I2_O [0], \core.alu.sum [4] }; + assign { \core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_13_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [20] }; + assign \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I3 [0] = \core.frontend.cir [31]; + assign \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [1:0] = { \core.csr_u.wdata_update [16], \core.csr_u.meifa [16] }; + assign { d_hwdata_SB_LUT4_O_12_I2[2], d_hwdata_SB_LUT4_O_12_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[19] }; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1 [2:1] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_27_I0 [0] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [2], d_hrdata[14] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I3 [1:0] = { \core.frontend.cir [12], \core.frontend.cir [31] }; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_I3 [2:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.csr_u.irq_r [2], \core.csr_u.meifa [2] }; + assign \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_I1_I2 [1:0] = { \core.alu.op_b_inv_SB_LUT4_O_19_I2 [0], \core.alu.op_a [12] }; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.csr_u.meifa_SB_DFFR_Q_16_D_SB_LUT4_O_I2 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.meifa [15] }; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [1] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]; + assign { \core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_18_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_I2_O [3], \core.csr_u.wdata_update [29], \core.csr_u.meifa [13] }; + assign \core.m_result_SB_LUT4_O_25_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1], d_hrdata[6] }; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [0] = d_hrdata[8]; + assign d_hwdata_SB_LUT4_O_13_I2_SB_LUT4_O_I1[2:1] = { d_hwdata_SB_LUT4_O_27_I2[2], d_hwdata_SB_LUT4_O_29_I2[1] }; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [0] = \core.xm_result [8]; + assign \core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [1] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [2:0] = { \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2], \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [0] }; + assign { d_hwdata_SB_LUT4_O_13_I2[2], d_hwdata_SB_LUT4_O_13_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[18] }; + assign \core.csr_u.meifa_SB_DFFR_Q_8_D_SB_LUT4_O_I3 [1:0] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [0] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_26_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.xm_rs2_SB_LUT4_I1_2_O [1:0] = { \core.mw_result [21], \core.xm_result [21] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign { \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [2]; + assign \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3 [0] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [0]; + assign \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [1] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign { \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_12_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [19] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2[3:1] = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_27_I2[1] }; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O [3:2] = \core.frontend.cir [21:20]; + assign \core.alu.op_a_SB_LUT4_O_23_I2 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2], \core.decode_u.pc [27] }; + assign \core.csr_u.meifa_SB_DFFR_Q_4_D_SB_LUT4_O_I3 [1:0] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [2]; + assign { \core.alu.op_a_SB_LUT4_O_12_I2 [2], \core.alu.op_a_SB_LUT4_O_12_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [19] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_O_I2 [1] = \core.frontend.cir [14]; + assign { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [3], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_I3 [0] } = { \core.frontend.cir [20], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1] }; + assign { \core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_12_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [19] }; + assign \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1], d_hrdata[28] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_5_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_5_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [27] }; + assign \core.csr_u.meifa_SB_DFFR_Q_6_D_SB_LUT4_O_I3 [1:0] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I0 [0] = \core.frontend.cir [13]; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_21_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_21_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [11] }; + assign { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [3], \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_25_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign { d_hwdata_SB_LUT4_O_11_I2[2], d_hwdata_SB_LUT4_O_11_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[20] }; + assign \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_I3 [1:0] = { \core.frontend.cir [4], \core.frontend.cir [5] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_2_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_2_I1 [0] } = { \core.alu.op_a [29], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] = \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2]; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [2:0] = { dbg_data0_wdata[0], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [19] }; + assign \core.m_result_SB_LUT4_O_27_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1], d_hrdata[4] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] = \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2]; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [1:0] = { \core.alu.sub_SB_LUT4_I2_O [0], \core.alu.sum [6] }; + assign \core.alu.op_a_SB_LUT4_O_22_I2 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2], \core.decode_u.pc [28] }; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O [2] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3 [1:0] = \core.frontend.cir [26:25]; + assign \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1], d_hrdata[0] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = \core.frontend.cir [28:27]; + assign \core.csr_u.meifa_SB_DFFR_Q_D_SB_LUT4_O_I3 [1:0] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [0] }; + assign d_hwdata_SB_LUT4_O_30_I2[2] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 [0] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3], \core.csr_u.wdata_update [30], \core.csr_u.meifa [30] }; + assign { \core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_9_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [29] }; + assign { d_hwdata_SB_LUT4_O_14_I2[2], d_hwdata_SB_LUT4_O_14_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[17] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_4_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_4_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [28] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [2:0] = { dbg_data0_wdata[0], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [3] }; + assign \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0]; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [3], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [2] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3], \core.csr_u.wdata_update [28], \core.csr_u.meifa [28] }; + assign { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_I1 [3:2], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_I1 [0] } = { \core.frontend.cir [26], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [2], \core.frontend.cir [24] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_2_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3], \core.csr_u.wdata_update [29], \core.csr_u.meifa [29] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O [1:0] = { \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2], \core.frontend.cir [12] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [1] = \core.frontend.cir [6]; + assign { \core.m_result_SB_LUT4_O_27_I2 [2], \core.m_result_SB_LUT4_O_27_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [4] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_2_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [29] }; + assign d_hwdata_SB_LUT4_O_31_I2[2] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [24] }; + assign d_hwdata_SB_LUT4_O_8_I2_SB_LUT4_O_I1[2:1] = { d_hwdata_SB_LUT4_O_27_I2[2], d_hwdata_SB_LUT4_O_24_I2[1] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [0] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [1]; + assign { \core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O_I1 [3:2], \core.csr_u.mcause_code_SB_DFFER_Q_2_D_SB_LUT4_O_I1 [0] } = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2], \core.csr_u.wdata_update [1], \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0] }; + assign { d_hwdata_SB_LUT4_O_15_I2[2], d_hwdata_SB_LUT4_O_15_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[16] }; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [3], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2 [1:0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [1], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0 [1:0] }; + assign { d_hwdata_SB_LUT4_O_8_I2[2], d_hwdata_SB_LUT4_O_8_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[23] }; + assign \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I3 [2:0] = { \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1], \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_6_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_6_I1 [0] } = { \core.alu.op_a [25], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign { \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I1 [3:2], \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I1 [0] } = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2], \core.csr_u.wdata_update [0], \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [0] }; + assign { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [3], \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2], \core.csr_u.meiea [9], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2 [1] = \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]; + assign \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I3 [2:0] = { \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1], \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [0] }; + assign \core.alu.op_a_SB_LUT4_O_9_I2 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2], \core.decode_u.pc [29] }; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 [3:2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 [0] } = { \core.frontend.cir [28], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 [1], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [2] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_O_I2 [1] = \core.frontend.cir [20]; + assign { \core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_8_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [25] }; + assign \core.csr_u.mcause_code_SB_DFFER_Q_1_D_SB_LUT4_O_I3 [1:0] = { \core.csr_u.wdata_update [2], \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2] }; + assign d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0[1] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [19] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_3_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_3_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [29] }; + assign \core.csr_u.mcause_code_SB_DFFER_Q_D_SB_LUT4_O_I0 [3:1] = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O_SB_LUT4_I3_O [2], \core.csr_u.wdata_update [3], \core.csr_u.meicontext_mreteirq_SB_LUT4_I1_O [3] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_21_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I3 [1:0] = \core.frontend.cir [5:4]; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0 [3:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [3] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_6_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [25] }; + assign d_hwdata_SB_LUT4_O_21_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[10], d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1] }; + assign { d_hwdata_SB_LUT4_O_24_I2[3:2], d_hwdata_SB_LUT4_O_24_I2[0] } = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_I0[0] }; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [3:2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [0], \core.frontend.cir [12], \core.frontend.cir [13] }; + assign \core.alu.op_b_inv_SB_LUT4_O_24_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign { \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I1 [0] } = { \core.alu.sum [27], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.m_result_SB_LUT4_O_13_I2 [2], \core.m_result_SB_LUT4_O_13_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [19] }; + assign d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[15] }; + assign { \core.m_result_SB_LUT4_O_10_I2 [2], \core.m_result_SB_LUT4_O_10_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [22] }; + assign \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [2] = \core.csr_u.mstatus_mie_SB_LUT4_I3_O [1]; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [7], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign { \core.m_result_SB_LUT4_O_7_I2 [2], \core.m_result_SB_LUT4_O_7_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [25] }; + assign \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_24_I0 [0] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.alu.op_b_inv_SB_LUT4_O_20_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign { \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [3], \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I0 [0] } = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1:0]; + assign { \core.m_result_SB_LUT4_O_4_I2 [2], \core.m_result_SB_LUT4_O_4_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [28] }; + assign \core.alu.op_b_inv_SB_LUT4_O_19_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2_SB_LUT4_O_I3 [2:0] = { \core.xm_addr_align [0], d_hrdata[23], d_hrdata[7] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [0] = \core.frontend.cir [7]; + assign d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0[1] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign { \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign { \core.m_result_SB_LUT4_O_31_I2 [2], \core.m_result_SB_LUT4_O_31_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_23_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.alu.op_a_SB_LUT4_O_29_I2 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2], \core.decode_u.pc [22] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_I0_SB_LUT4_O_2_I2 [2] = \core.frontend.cir [6]; + assign \core.csr_u.irq_software_r_SB_LUT4_I3_O [3:2] = { \core.csr_u.mstatus_mie , \core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [1] }; + assign { \core.alu.op_a_SB_LUT4_O_11_I2 [2], \core.alu.op_a_SB_LUT4_O_11_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [16] }; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_I2 [1] = \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1]; + assign { \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [8], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign { \core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_11_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [16] }; + assign \core.xm_result_SB_DFFER_Q_23_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_23_I0 [0] }; + assign { d_hwdata_SB_LUT4_O_25_I2[3:2], d_hwdata_SB_LUT4_O_25_I2[0] } = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_I0[0] }; + assign \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1:0] = { \core.frontend.cir [15], \core.frontend.cir [12] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_10_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_10_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [22] }; + assign \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I2_O [2]; + assign d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[14] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign \core.alu.op_a_SB_LUT4_O_14_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign \core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [3:2] = { \core.csr_u.mie_SB_DFFER_Q_E [0], \core.csr_u.wdata_update [3] }; + assign { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [2], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [1], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [1] }; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [24], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [1:0] = { \core.csr_u.wdata_update [17], \core.csr_u.meiea [1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_15_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [16] }; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0 [1:0] = \core.frontend.cir [31:30]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [3] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I0 [3:1] = { \core.frontend.reset_holdoff , \core.frontend.mem_addr_vld_SB_LUT4_O_I2 [0], \core.frontend.mem_addr_hold }; + assign d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0[1] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign { \core.alu.op_b_inv_SB_LUT4_O_17_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_17_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I2_O [1] = \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I3_O [0]; + assign \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [3:2] = { \core.csr_u.mie [11], \core.csr_u.meicontext_preempt [4] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_16_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_16_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0], \core.csr_u.mscratch [25] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 [0] = \core.frontend.cir [28]; + assign { \core.alu.op_b_inv_SB_LUT4_O_15_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_15_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign { d_hwdata_SB_LUT4_O_26_I2[3:2], d_hwdata_SB_LUT4_O_26_I2[0] } = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_I0[0] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 [1] }; + assign d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[13] }; + assign { \core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_10_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [14] }; + assign \core.alu.op_b_inv_SB_LUT4_O_22_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_I0_I1 [1] = \core.csr_u.meiea [31]; + assign \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1], d_hrdata[29] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 [1] }; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1:0] = \core.frontend.cir [21:20]; + assign { \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [9], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign dphase_active_i_SB_LUT4_I3_O[2] = \core.frontend.pending_fetches [0]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign { \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_17_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [14] }; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign \core.m_result_SB_LUT4_O_26_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1], d_hrdata[5] }; + assign { \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_15_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_15_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [17] }; + assign { \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [3], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [0] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_22_I0 [0] }; + assign { d_hwdata_SB_LUT4_O_29_I2[3:2], d_hwdata_SB_LUT4_O_29_I2[0] } = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2[0] }; + assign d_hwdata_SB_LUT4_O_10_I2_SB_LUT4_O_I1[2:1] = { d_hwdata_SB_LUT4_O_27_I2[2], d_hwdata_SB_LUT4_O_26_I2[1] }; + assign \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [2] = \core.csr_u.meifa_SB_DFFR_Q_5_D_SB_LUT4_O_I0 [1]; + assign \core.alu.op_a_SB_LUT4_O_26_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign { \core.alu.op_b_inv_SB_LUT4_O_14_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_14_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [3] = dbg_data0_wdata[23]; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [24], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_13_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [1:0] = { \core.csr_u.wdata_update [23], \core.csr_u.meiea [23] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_12_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_12_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_18_I0_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [13] }; + assign { \core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_31_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [8] }; + assign \core.alu.op_a_SB_LUT4_O_21_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_18_I0 [3:1] = { dbg_data0_wdata[13], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_O [1] }; + assign \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [2] = \core.csr_u.meifa_SB_DFFR_Q_9_D_SB_LUT4_O_I0 [1]; + assign { \core.alu.op_b_inv_SB_LUT4_O_11_I0 [3], \core.alu.op_b_inv_SB_LUT4_O_11_I0 [1] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3], \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [25], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_23_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [8] }; + assign \core.csr_u.meicontext_noirq_SB_LUT4_I1_I3 [1:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3], \core.csr_u.meicontext_noirq }; + assign { \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [23], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I3 [1:0] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [0], \core.csr_u.meifa_SB_DFFR_Q_12_D_SB_LUT4_O_I1 [1] }; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [0] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I1 [1] }; + assign \core.frontend.next_instr_SB_LUT4_O_15_I3 [1:0] = { \core.frontend.cir [16], \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_13_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3], \core.csr_u.wdata_update [18], \core.csr_u.meifa [18] }; + assign { \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O_I2 [3], \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_O_I2 [1:0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [1], d_hrdata[15] }; + assign \core.alu.op_b_inv_SB_LUT4_O_10_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [1] = \core.frontend.next_instr [16]; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1 [1] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]; + assign { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [1:0] } = { \core.frontend.cir [12], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [1] }; + assign \core.m_result_SB_LUT4_O_17_I1 [2:0] = { d_hrdata[31], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3], \core.xm_memop [1] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [3], \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [30], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign \core.m_result_SB_LUT4_O_17_I1_SB_LUT4_I3_O [0] = d_hrdata[31]; + assign { \core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_14_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3], \core.csr_u.wdata_update [17], \core.csr_u.meifa [17] }; + assign { \core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [11] }; + assign { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2 [3], \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_I3_SB_LUT4_I3_O [3], \core.csr_u.wdata_update [20], \core.csr_u.meifa [20] }; + assign \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_I2 [1:0] = { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1 [0], \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0] }; + assign \core.frontend.next_instr_SB_LUT4_O_8_I3 [1:0] = { \core.frontend.cir [23], \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1] }; + assign \core.decode_u.cir_lock_prev_SB_LUT4_I2_O [1:0] = { \core.decode_u.f_jump_target [13], \core.decode_u.pc_seq_next [13] }; + assign { \core.m_result_SB_LUT4_O_1_I2 [2], \core.m_result_SB_LUT4_O_1_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [31] }; + assign \core.d_rs2_SB_LUT4_O_I1 [2:1] = { \core.frontend.cir [23], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_22_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_22_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [10] }; + assign { \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [20], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I1 [3:2], \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I1 [0] } = { \core.alu.sum [25], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [5] }; + assign { \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2], \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0] }; + assign { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [16], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [1:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3], \core.csr_u.meicontext_irq [7] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_17_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_17_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [15] }; + assign \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign { \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2 [3], \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2 [1:0] } = { \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1], \core.frontend.cir [25], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [3] }; + assign \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0[1] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0_SB_LUT4_O_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [11] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_26_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [5] }; + assign \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [2:1] = { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [1], \core.csr_u.meicontext_preempt [4] }; + assign { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I1 [0] } = { \core.alu.sum [19], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_20_I0 [3:1] = { dbg_data0_wdata[11], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0 [3:1] = { dbg_data0_wdata[29], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_9_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_9_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [23] }; + assign \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0], \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [2:1] = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] }; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [16] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_21_I0 [3:1] = { dbg_data0_wdata[10], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_20_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [11] }; + assign { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_13_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_13_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [19] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I1_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0 [3:2] = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [1] }; + assign \core.frontend.next_instr_SB_LUT4_O_10_I3 [1:0] = { \core.frontend.fifo_mem[0] [21], \core.frontend.buf_level_SB_LUT4_I3_I2 [1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_3_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_3_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_23_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_23_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [9] }; + assign { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2], \core.csr_u.meiea [0], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign \core.d_addr_offs_SB_LUT4_O_13_I1_SB_LUT4_I3_O [1:0] = { \core.frontend.cir [15], \core.frontend.cir [31] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [1] = \core.csr_u.meiea [15]; + assign \core.frontend.next_instr_SB_LUT4_O_9_I3 [1:0] = { \core.frontend.fifo_mem[0] [22], \core.frontend.buf_level_SB_LUT4_I3_I2 [1] }; + assign { \core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_26_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [10] }; + assign \core.m_result_SB_LUT4_O_19_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1], d_hrdata[13] }; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign \core.alu.sub_SB_LUT4_I2_O [1] = \core.alu.sum [0]; + assign { \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [18], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign \core.csr_u.meicontext_noirq_SB_LUT4_I1_O [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0], \core.csr_u.mscratch [15] }; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign { \core.m_result_SB_LUT4_O_19_I2 [2], \core.m_result_SB_LUT4_O_19_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [13] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0] }; + assign \core.alu.op_a_SB_LUT4_O_15_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [1] = \core.csr_u.meiea [10]; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I0_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_16_I0 [3:1] = { dbg_data0_wdata[15], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_21_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [10] }; + assign \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_1_I3 [1] = \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_I1 [1]; + assign { \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_I1_I2 [1:0] = { \core.alu.op_b_inv_SB_LUT4_O_24_I2 [0], \core.alu.op_a [7] }; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [3], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [0] } = { \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0], \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0] }; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign \core.m_result_SB_LUT4_O_21_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1], d_hrdata[11] }; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [0] = \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]; + assign { d_hwdata_SB_LUT4_O_28_I2[3:2], d_hwdata_SB_LUT4_O_28_I2[0] } = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_I0[0] }; + assign \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O [2:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2], \core.csr_u.meifa [1], \core.csr_u.wdata_update [17] }; + assign { \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_I1 [3:2], \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O_SB_LUT4_O_I1 [0] } = { \core.alu.sum [17], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_24_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [7] }; + assign \core.csr_u.mstatus_mprv_SB_LUT4_I3_O_SB_LUT4_I2_O_SB_LUT4_I0_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I2_O [1] = \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [3]; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [1] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [1:0] = { \core.alu.op_a [31], \core.alu.op_a [0] }; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign { \core.m_result_SB_LUT4_O_21_I2 [2], \core.m_result_SB_LUT4_O_21_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [11] }; + assign { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O_SB_LUT4_O_I1 [0] } = { \core.alu.sum [16], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_I2 [3], \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [4] }; + assign \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [0], \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2] }; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I2 [2], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1 [1] }; + assign { \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] }; + assign { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [3], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3] }; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign { \core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_27_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [7] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_I2 [1] = \core.csr_u.meiea [7]; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1 [0] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O [2:1] = { \core.alu.op_a [0], \core.alu.op_b_inv [0] }; + assign \core.csr_u.mcause_code_SB_DFFER_Q_3_D_SB_LUT4_O_I0 [1] = \core.csr_u.irq_vector_enable ; + assign { \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [3], \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2 [0] } = { \core.alu.op_a [12], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2_SB_LUT4_O_I0 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2]; + assign \core.xm_rs2_SB_LUT4_I0_O [1:0] = { \core.xm_rs2 [2], \core.mw_rd [2] }; + assign { \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_31_D_SB_LUT4_O_I2 [0] } = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_31_I0 [0] }; + assign \core.csr_u.irq_vector_enable_SB_LUT4_I3_O [2:1] = { \core.csr_u.mepc [2], \core.csr_u.mtvec_reg [2] }; + assign { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [0] } = { \core.alu.sum [15], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O_SB_LUT4_O_I3 [2:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.csr_u.irq_r [14], \core.csr_u.meifa [14] }; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [1:0] = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2] }; + assign { \core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_28_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [12] }; + assign \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_16_I0 [0] }; + assign \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [0] = \core.x_addr_sum [2]; + assign \core.alu.op_a_SB_LUT4_O_27_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign \core.m_result_SB_LUT4_O_22_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1], d_hrdata[10] }; + assign { \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2_I2 [3], \core.csr_u.meicontext_preempt_SB_LUT4_I1_O_SB_LUT4_O_2_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [20], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [1] }; + assign d_hwdata_SB_LUT4_O_23_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[8], d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_19_I2_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [12] }; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [1:0] = { i_hready_SB_LUT4_I3_O_SB_LUT4_I1_O[0], \core.frontend.fetch_addr [2] }; + assign { \core.m_result_SB_LUT4_O_22_I2 [2], \core.m_result_SB_LUT4_O_22_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [10] }; + assign d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[11] }; + assign \core.alu.op_b_inv_SB_LUT4_O_9_I1 [3:2] = { \core.alu.op_a [22], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3], \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [29], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I1 [0] } = { \core.alu.sum [14], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_9_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [22] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] } = { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_6_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_6_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [26] }; + assign { \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.alu.sum [13], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign \core.m_result_SB_LUT4_O_17_I0 [3:1] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [15], \core.m_result_SB_LUT4_O_17_I1 [3] }; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [1:0] = { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3 [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2] }; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_17_I0 [0] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign { \core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_29_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [22] }; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign d_hwdata_SB_LUT4_O_22_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[9], d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1] }; + assign \core.m_result_SB_LUT4_O_20_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1], d_hrdata[12] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_2_I0 [0] }; + assign { \core.m_result_SB_LUT4_O_20_I2 [2], \core.m_result_SB_LUT4_O_20_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [12] }; + assign d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2[1] = d_hwdata_SB_LUT4_O_27_I2[2]; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_1_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_1_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [31] }; + assign \core.alu.op_b_inv_SB_LUT4_O_1_I2 [3:1] = { \core.alu.op_a [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0], \core.alu.op_a [30] }; + assign \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [0] = \core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [0]; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_8_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_8_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [24] }; + assign { \core.alu.op_a_SB_LUT4_O_19_I2 [2], \core.alu.op_a_SB_LUT4_O_19_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [30] }; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I2 [1] = \core.frontend.mem_addr_hold ; + assign { \core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_19_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [30] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [1] = \core.csr_u.meiea [13]; + assign { \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0] }; + assign \core.m_result_SB_LUT4_O_18_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1], d_hrdata[14] }; + assign \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0]; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1 [1] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]; + assign \core.xm_result_SB_DFFER_Q_18_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_18_I0 [0] }; + assign { \core.m_result_SB_LUT4_O_18_I2 [2], \core.m_result_SB_LUT4_O_18_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [14] }; + assign \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [3] = dbg_data0_wdata[0]; + assign \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_I2 [2], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [30] }; + assign \core.csr_u.mcause_irq_SB_LUT4_I1_O [0] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]; + assign \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [1], d_hrdata[1] }; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2 [2], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1] }; + assign \core.alu.op_a_SB_LUT4_O_18_I3 [0] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2]; + assign \core.m_result_SB_LUT4_O_30_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1], d_hrdata[25] }; + assign { \core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_18_I3_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [0] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3_SB_LUT4_O_I3 [2:0] = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [12], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O [1:0] = { \core.csr_u.meicontext_preempt_SB_LUT4_I1_1_I0 [0], \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0] }; + assign \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [0] = \core.frontend.fifo_almost_full ; + assign \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [2:1] = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_8_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] }; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [3], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_2_O [1] } = { d_hrdata[9], d_hrdata[17] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_1_I3 [1:0] = { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [0] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_24_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_24_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [8] }; + assign \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2]; + assign { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [0] }; + assign { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2 [3], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_1_I2 [1:0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [3], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign { \core.m_result_SB_LUT4_O_12_I2 [2], \core.m_result_SB_LUT4_O_12_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [20] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_7_I2 [3:2], \core.alu.op_b_inv_SB_LUT4_O_7_I2 [0] } = { \core.alu.op_a [2], \core.alu.op_a [24], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2] }; + assign \core.csr_u.irq_timer_r_SB_LUT4_I3_1_O [2] = \core.csr_u.mstatus_mie ; + assign { \core.alu.op_a_SB_LUT4_O_16_I2 [2], \core.alu.op_a_SB_LUT4_O_16_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [24] }; + assign { \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0_SB_LUT4_O_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [10], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [2], \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [1] }; + assign { \core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_16_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [24] }; + assign d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2[3:1] = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_31_I2[1] }; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_O [2] = \core.csr_u.irq_vector_enable ; + assign d_hwdata_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[24] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.decode_u.f_jump_target_SB_LUT4_O_28_I2_SB_LUT4_O_I0 [3:1] = { \core.csr_u.irq_vector_enable_SB_LUT4_I3_O [3], \core.csr_u.mepc [4], \core.csr_u.mtvec_reg [4] }; + assign { \core.alu.op_a_SB_LUT4_O_17_I2 [2], \core.alu.op_a_SB_LUT4_O_17_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [2] }; + assign { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [3:2], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2 [1], \core.frontend.cir [15], \core.frontend.cir [13] }; + assign { \core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_17_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [2] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_28_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_28_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [4] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_18_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_18_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [14] }; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I1_O [2:1] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [1], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3] }; + assign \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0 [2:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0], \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign { \core.m_result_SB_LUT4_O_16_I2 [2], \core.m_result_SB_LUT4_O_16_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [16] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_7_I2_SB_LUT4_O_I0_SB_LUT4_O_1_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [24] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3 [2:0] = { \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2], \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0 [1:0] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_19_I0 [0] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] } = { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_I0_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2] }; + assign { \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2 [3], \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I2 [1:0] } = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O [3], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign d_hwdata_SB_LUT4_O_21_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[26] }; + assign \core.d_addr_offs_SB_LUT4_O_9_I3 [1:0] = { \core.frontend.cir [10], \core.frontend.cir [23] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] = \core.x_jump_misaligned ; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [1] = \core.decode_u.pc [3]; + assign { \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.csr_u.meicontext_irq_SB_DFFER_Q_4_D_SB_LUT4_O_I1_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_12_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_12_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [20] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [2] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [1] }; + assign \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [27] }; + assign { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [3:2], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O [0] } = { \core.xm_addr_align [0], \core.xm_addr_align [1], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [5] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_29_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_29_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [3] }; + assign { \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [3], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O [1] }; + assign { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [2], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3 [0] } = \core.xm_memop [1:0]; + assign { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [13] }; + assign { \core.m_result_SB_LUT4_O_9_I2 [2], \core.m_result_SB_LUT4_O_9_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [23] }; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign { d_hwdata_SB_LUT4_O_10_I2[2], d_hwdata_SB_LUT4_O_10_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[21] }; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_2_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [22] }; + assign \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I0 [3:1] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_O [1], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2] }; + assign d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2[3:1] = { d_hwdata_SB_LUT4_O_27_I2[2], \core.xm_memop [0], d_hwdata_SB_LUT4_O_30_I2[1] }; + assign d_hwdata_SB_LUT4_O_9_I2_SB_LUT4_O_I1[2:1] = { d_hwdata_SB_LUT4_O_27_I2[2], d_hwdata_SB_LUT4_O_25_I2[1] }; + assign { d_hwdata_SB_LUT4_O_9_I2[2], d_hwdata_SB_LUT4_O_9_I2[0] } = { bus_active_dph_s, dbg_sbus_wdata[22] }; + assign \core.xm_result_SB_DFFER_Q_21_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_21_I0 [0] }; + assign d_hwdata_SB_LUT4_O_1_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[30], d_hwdata_SB_LUT4_O_25_I2_SB_LUT4_I1_O[1] }; + assign \core.frontend.buf_level_SB_LUT4_I3_O [2] = \core.decode_u.cir_lock_prev_SB_LUT4_I2_I3 [0]; + assign dbg_data0_wdata_SB_LUT4_O_31_I2[2:1] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2], \core.frontend.next_instr [15] }; + assign { \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1 [3:2], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1 [0] } = { \core.alu.sum [22], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O_I1 [3:2], \core.csr_u.mie_SB_DFFER_Q_1_D_SB_LUT4_O_I1 [0] } = { \core.csr_u.mie_SB_DFFER_Q_E [0], \core.csr_u.mie_SB_DFFER_Q_2_D_SB_LUT4_O_I0 [1], \core.csr_u.wdata_update [3] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.alu.sum [5], \core.alu.sub_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I3_1_O [2] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_26_I0 [0] }; + assign d_hwdata_SB_LUT4_O_22_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[25] }; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_I0 [2] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2]; + assign \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I3 [2:0] = { \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0 [1] }; + assign { \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I1 [3:2], \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O_SB_LUT4_O_1_I1 [0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [1], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_O [3], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_21_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [13] }; + assign \core.csr_u.mcause_irq_SB_LUT4_I1_O_SB_LUT4_I1_O_SB_LUT4_I3_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign { \core.m_result_SB_LUT4_O_14_I2 [2], \core.m_result_SB_LUT4_O_14_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [18] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_25_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_25_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [7] }; + assign { \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1 [3:2], \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_I1 [0] } = { \core.xm_memop_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_I3_O [1], \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [3], \core.alu.sub_SB_LUT4_I2_O [2] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_I3 [2:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [30] }; + assign { \core.alu.op_a_SB_LUT4_O_20_I2 [2], \core.alu.op_a_SB_LUT4_O_20_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [17] }; + assign d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[3:2] = { bus_active_dph_s, dbg_sbus_wdata[28] }; + assign \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [0] = d_hrdata[7]; + assign { \core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_20_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [17] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_1_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [26], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign { \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [3:2], \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.alu.sum [11], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0], \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2 [1] }; + assign \core.xm_result_SB_DFFER_Q_20_D_SB_LUT4_O_I0 [3:2] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_20_I0 [0] }; + assign \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I3 [2:0] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2], \core.frontend.fifo_valid_hw[1]_SB_LUT4_I0_I1 [1], \core.frontend.fifo_valid_hw[1] [1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.m_result_SB_LUT4_O_I2 [2], \core.m_result_SB_LUT4_O_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [7] }; + assign \core.xm_result_SB_DFFER_Q_24_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O [0]; + assign { \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_14_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [17] }; + assign { \core.frontend.buf_level_SB_LUT4_I3_I2 [2], \core.frontend.buf_level_SB_LUT4_I3_I2 [0] } = { \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [2], \core.frontend.fifo_full }; + assign \core.frontend.ctr_flush_pending_SB_DFFER_Q_D_SB_LUT4_O_I0 [3:1] = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2], \core.frontend.ctr_flush_pending [0], \core.frontend.ctr_flush_pending [1] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1 [3] = \core.alu.op_a [3]; + assign { \core.m_result_SB_LUT4_O_6_I2 [2], \core.m_result_SB_LUT4_O_6_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [26] }; + assign \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I0_O [2:0] = { \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1_SB_LUT4_I3_O [1], \core.csr_u.meifa_SB_DFFR_Q_7_D_SB_LUT4_O_I1 [0], \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [2] }; + assign \core.frontend.fifo_valid_hw[0]_SB_DFFER_Q_E [1:0] = { \core.frontend.fifo_full , \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_I2_O [2] }; + assign { \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_27_D_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I2_SB_LUT4_O_1_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.meiea [27], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_2_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_2_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [30] }; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1 [3:2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I1 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0], \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2] }; + assign bus_hold_aph_SB_LUT4_I2_O[2] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [1]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_1_I3 [1:0] = { \core.csr_u.mepc [26], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2] }; + assign { \core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_15_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [15] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_26_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_26_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [6] }; + assign { \core.m_result_SB_LUT4_O_15_I2 [2], \core.m_result_SB_LUT4_O_15_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [17] }; + assign { \core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [2], \core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [0] } = { \core.power_ctrl.state [1], \core.xm_sleep_wfi }; + assign \core.m_result_SB_LUT4_O_23_I2_SB_LUT4_O_I3 [1:0] = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O [1], d_hrdata[9] }; + assign { \core.m_result_SB_LUT4_O_11_I2 [2], \core.m_result_SB_LUT4_O_11_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [21] }; + assign { \core.m_result_SB_LUT4_O_26_I2 [2], \core.m_result_SB_LUT4_O_26_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [5] }; + assign \core.alu.op_a_SB_LUT4_O_8_I2 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O [2], \core.decode_u.pc [25] }; + assign \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [0] = d_hrdata[27]; + assign { \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.m_result_SB_LUT4_O_25_I2 [2], \core.m_result_SB_LUT4_O_25_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [6] }; + assign pwrup_ack_SB_LUT4_I1_I3[1:0] = { \core.power_ctrl.state [2], pwrup_ack }; + assign { \core.m_result_SB_LUT4_O_29_I2 [2], \core.m_result_SB_LUT4_O_29_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [2] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_16_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [15] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O_I1 [3:2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_LUT4_I2_O_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [3] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_7_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_7_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [25] }; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2_I2 [3], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_2_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I2_O [2], \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [26] }; + assign \core.m_result_SB_LUT4_O_31_I2_SB_LUT4_O_I2 [0] = d_hrdata[3]; + assign { bus_gnt_d_SB_LUT4_O_I2[2], bus_gnt_d_SB_LUT4_O_I2[0] } = { bus_hold_aph, bus_gnt_ds_prev[1] }; + assign { \core.m_result_SB_LUT4_O_28_I2 [2], \core.m_result_SB_LUT4_O_28_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [3] }; + assign bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_1_I3[2:0] = { bus_active_dph_d_SB_LUT4_I1_I3[2], \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O [1:0] }; + assign \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1 [2:1] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_O [2]; + assign { \core.m_result_SB_LUT4_O_30_I2 [2], \core.m_result_SB_LUT4_O_30_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [1] }; + assign d_hwdata_SB_LUT4_O_2_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[29], d_hwdata_SB_LUT4_O_26_I2_SB_LUT4_I1_O[1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [28] }; + assign d_hwdata_SB_LUT4_O_4_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[27], d_hwdata_SB_LUT4_O_28_I2_SB_LUT4_I1_O[1] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [3], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I2 [1:0] } = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2], \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0 [0] }; + assign { bus_gnt_s_SB_LUT4_O_I1[3:2], bus_gnt_s_SB_LUT4_O_I1[0] } = { bus_hold_aph, bus_gnt_ds_prev[2], bus_gnt_d_SB_LUT4_O_I2[1] }; + assign \core.frontend.next_instr_SB_LUT4_O_13_I3 [1:0] = { \core.frontend.cir [18], \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1_I2 [3], \core.csr_u.wdata_update_SB_LUT4_O_10_I0_SB_LUT4_O_1_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [21], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_10_I0 [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign dbg_data0_wdata_SB_LUT4_O_29_I2[2:1] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2], \core.frontend.next_instr [18] }; + assign \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2 [2:0] = { \core.power_ctrl.stall_release_SB_LUT4_I2_O [1], \core.csr_u.mstatus_mie_SB_LUT4_I3_O [1], \core.frontend.mem_addr_hold }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.frontend.next_instr_SB_LUT4_O_14_I3 [1:0] = { \core.frontend.fifo_mem[0] [17], \core.frontend.buf_level_SB_LUT4_I3_I2 [1] }; + assign { \core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [28] }; + assign dbg_data0_wdata_SB_LUT4_O_28_I2[2:1] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2], \core.frontend.next_instr [17] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1 [0] } = { \core.alu.op_a [1], \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_I1_I3 [1:0] = { \core.alu.op_a [9], \core.alu.op_b_inv_SB_LUT4_O_22_I2 [0] }; + assign bus_active_dph_d_SB_LUT4_I1_I3[1:0] = { d_hready, bus_active_dph_d }; + assign { \core.alu.op_a_SB_LUT4_O_I2 [2], \core.alu.op_a_SB_LUT4_O_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_19_I0_SB_LUT4_O_I2 [0] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [2]; + assign { \core.m_result_SB_LUT4_O_23_I2 [2], \core.m_result_SB_LUT4_O_23_I2 [0] } = { \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_I3_1_O_SB_LUT4_I2_O [2], \core.xm_result [9] }; + assign { \core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_14_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [9] }; + assign { \core.df_cir_use_SB_LUT4_I2_O [3], \core.df_cir_use_SB_LUT4_I2_O [1] } = { \core.frontend.cir [9], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_17_I0_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [14] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_16_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_16_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [16] }; + assign \core.alu.op_a_SB_LUT4_O_10_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign { \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_17_I0 [3:1] = { dbg_data0_wdata[14], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [1] = \core.df_cir_use_SB_LUT4_I2_O [0]; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 [0] = \core.csr_u.meifa_SB_DFFR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [2]; + assign \core.frontend.next_instr_SB_LUT4_O_12_I3 [1:0] = { \core.frontend.cir [19], \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_22_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [9] }; + assign \core.regs.raddr1_SB_LUT4_O_I1 [2:1] = { \core.prev_instr_was_32_bit_SB_DFFER_Q_E_SB_LUT4_I1_O [2], \core.frontend.next_instr [19] }; + assign \core.alu.op_a_SB_LUT4_O_28_I2 [0] = \core.alu.op_a_SB_LUT4_O_3_I2 [0]; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_I1 [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_19_I0 [3:1] = { dbg_data0_wdata[12], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.xm_memop_SB_DFFER_Q_1_D_SB_LUT4_O_I3 [1:0] = { \core.df_cir_use_SB_LUT4_I2_O [0], \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [0] }; + assign bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I3[2:0] = { \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_I2_O [2], bus_hold_aph_SB_LUT4_I2_O_SB_LUT4_O_I1[1], \core.power_ctrl.stall_release_SB_LUT4_I2_O [1] }; + assign \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1 [2:1] = { \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2], \core.df_cir_use_SB_LUT4_I2_O [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_4_I1 [3], \core.alu.op_b_inv_SB_LUT4_O_4_I1 [0] } = { \core.alu.op_a [27], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_I1_O_SB_LUT4_I2_O [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_8_I2_SB_LUT4_I0_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [1] }; + assign \core.frontend.next_instr_SB_LUT4_O_16_I3 [1:0] = { \core.frontend.cir [15], \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1] }; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [3], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [1] } = { \core.csr_u.mie [3], \core.csr_u.mscratch [3] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_19_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_19_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [13] }; + assign \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [3:2] = { \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2], \core.df_cir_use_SB_LUT4_I2_O [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [0] }; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [3], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [1] } = { \core.csr_u.mepc [3], \core.csr_u.mtvec_reg [3] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_4_I1_SB_LUT4_O_1_I2_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [27] }; + assign \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I3 [2:0] = { \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [2], \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1 [4], \core.m_result_SB_LUT4_O_17_I0_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O [3] }; + assign \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [3], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [1] } = { \core.csr_u.mstatus_mie , \core.csr_u.mcause_code [3] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [0] = \core.csr_u.irq_software_r ; + assign { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I2 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0], \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_O_I1 [1] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [2] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1]; + assign { \core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_23_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [27] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_O [1] = \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_I3_O [2]; + assign \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [2] = \core.df_cir_use_SB_LUT4_I2_O [0]; + assign \core.csr_u.meifa_SB_DFFR_Q_27_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [2:0] = { \core.csr_u.meifa_SB_DFFR_Q_19_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O [1], \core.csr_u.meifa_SB_DFFR_Q_11_D_SB_LUT4_O_I2_SB_LUT4_O_I3 [1], \core.csr_u.meifa_SB_DFFR_Q_10_D_SB_LUT4_O_I1 [0] }; + assign d_hwdata_SB_LUT4_O_19_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[12], d_hwdata_SB_LUT4_O_19_I0_SB_LUT4_O_I2_SB_LUT4_I0_O[1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_26_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [5] }; + assign \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign \core.csr_u.wdata_update_SB_LUT4_O_30_I0_SB_LUT4_O_I2 [1:0] = { \core.frontend.mem_addr_hold_SB_LUT4_I2_O [0], \core.csr_u.mie [7] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3 [2:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_I3_O [1], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I1_O [1], \core.df_cir_use_SB_LUT4_I2_O [0] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_28_I0_SB_LUT4_O_I3 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I3_O [0], \core.csr_u.mscratch [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I3 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I2 [1], \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_30_I0 [3:1] = { dbg_data0_wdata[3], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_I2 [1] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [1]; + assign \core.frontend.next_instr_SB_LUT4_O_7_I3 [1:0] = { \core.frontend.cir [24], \core.frontend.ctr_flush_pending_SB_LUT4_I1_O [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O_SB_LUT4_O_I2_SB_LUT4_I1_O [0], \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_I1 [0] }; + assign { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0 [3:2], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0 [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O [3] }; + assign \core.xm_except_SB_DFFES_Q_1_D_SB_LUT4_O_I2 [0] = \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1 [0]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I3 [1:0] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I1 [2] }; + assign \core.csr_u.meicontext_mreteirq_SB_LUT4_I3_I0 [3:1] = { \core.csr_u.meicontext_mreteirq , \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O [3], \core.csr_u.mscratch [0] }; + assign { \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.alu.op_b_inv_SB_LUT4_O_25_I2_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [6] }; + assign \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_I1_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.csr_u.meicontext_mreteirq_SB_LUT4_I3_O [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.irq_vector_enable }; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0 [3:1] = { dbg_data0_wdata[4], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_1_I0 [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_31_I0_SB_LUT4_O_I3 [2:0] = { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O [2], \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_I2_SB_LUT4_I2_O [0], \core.csr_u.mcause_code [0] }; + assign { \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [2], \core.xm_except_SB_DFFES_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [0] } = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_except_SB_DFFES_Q_3_D_SB_LUT4_O_I1 [0] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_I3 [1:0] = { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [28] }; + assign { \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [2], \core.decode_u.cir_lock_prev_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_I3_O [0] } = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_2_O [1] }; + assign { \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 [3:2], \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 [0] } = { \core.alu.sum [28], \core.alu.sub_SB_LUT4_I2_O [0], \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2] }; + assign { \core.power_ctrl.stall_release_SB_LUT4_I2_O [3:2], \core.power_ctrl.stall_release_SB_LUT4_I2_O [0] } = { \core.power_ctrl.state [3], \core.power_ctrl.state [0], \core.power_ctrl.state_SB_DFFR_Q_D_SB_LUT4_O_I1 [1] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3_SB_LUT4_O_I3 [1:0] = { \core.xm_result_SB_DFFER_Q_28_D_SB_LUT4_O_I1_SB_LUT4_O_I2 [1], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I2_O [0] }; + assign { \core.alu.op_a_SB_LUT4_O_5_I2 [2], \core.alu.op_a_SB_LUT4_O_5_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [6] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_28_I0 [3:1] = { dbg_data0_wdata[1], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.m_reg_wen_if_nonzero_SB_LUT4_O_I2_SB_LUT4_I3_O [1:0] = { bus_active_dph_d, d_hresp }; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_I3 [1:0] = { \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [1], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O [0] }; + assign \core.xm_result_SB_DFFER_Q_19_D_SB_LUT4_O_I0_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_1_I1 [2] = \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I1_O [2]; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0 [2] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign { \core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_5_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [6] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_2_I0_SB_LUT4_O_I1_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [29] }; + assign \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [1] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2] = \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I1_O [0]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_1_I3 [1:0] = { \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2 [0], \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I2_O [2] }; + assign \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [0] = \core.csr_u.mie_SB_DFFER_Q_E_SB_LUT4_O_I2 [0]; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_I3 [1:0] = { \core.csr_u.mstatus_mie_SB_LUT4_I3_1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_I3_O [1], \core.csr_u.meiea [12] }; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1 [1] = \core.alu.op_b_inv_SB_LUT4_O_I2_SB_LUT4_O_I1 [1]; + assign d_hsize_SB_LUT4_O_1_I1[2:1] = { d_hsize_SB_LUT4_O_I1[0], \core.bus_haddr_d [0] }; + assign \core.d_rs2_predecoded_SB_LUT4_I1_2_O [0] = \core.xm_result [31]; + assign \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [3] = \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2]; + assign { \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_26_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I1_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_I2 [0] } = { \core.d_rs2_predecoded_SB_LUT4_I1_2_O [2], \core.xm_result [4] }; + assign \core.d_rs2_predecoded_SB_LUT4_I1_5_O [1:0] = { \core.mw_result [31], \core.regs.rdata2 [31] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2_SB_LUT4_O_1_I0 [3:2] = { \core.csr_u.wdata_update_SB_LUT4_O_23_I0_SB_LUT4_O_I2_SB_LUT4_O_1_I3_SB_LUT4_I2_1_O [2], dbg_data0_wdata[0] }; + assign d_hsize_SB_LUT4_O_I1[2:1] = { bus_gnt_s, dbg_sbus_size[1] }; + assign \core.d_rs2_predecoded_SB_LUT4_I1_4_O [1:0] = { \core.d_rs2_predecoded [2], \core.mw_rd [2] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3_SB_LUT4_O_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [0], \core.csr_u.mtvec_reg [4] }; + assign d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I3[2:0] = { d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[2], d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[0], d_hsize_SB_LUT4_O_I1_SB_LUT4_O_I0[1] }; + assign \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O [2] = \core.csr_u.meifa_SB_DFFR_Q_25_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]; + assign \core.decode_u.f_jump_target_SB_LUT4_O_27_I0 [3:2] = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [5] }; + assign \core.csr_u.meifa_SB_DFFR_Q_23_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I3_O [0] = \core.csr_u.meifa_SB_DFFR_Q_17_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I3_O [0]; + assign \core.d_rs2_predecoded_SB_LUT4_I1_O [1:0] = { \core.d_rs2_predecoded [2], \core.xm_rd [2] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_3_I0_SB_LUT4_O_1_I2 [1:0] = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1_SB_LUT4_I3_O [2], \core.csr_u.mepc [28] }; + assign { \core.alu.op_a_SB_LUT4_O_4_I2 [2], \core.alu.op_a_SB_LUT4_O_4_I2 [0] } = { \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.decode_u.pc [4] }; + assign \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I3 [1:0] = { \core.csr_u.wdata_update_SB_LUT4_O_27_I0_SB_LUT4_O_I2 [0], \core.csr_u.irq_software_r_SB_LUT4_I0_O_SB_LUT4_I1_O [0] }; + assign { \core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O_I1 [3:2], \core.alu.op_a_SB_LUT4_O_4_I2_SB_LUT4_O_I1 [0] } = { \core.d_rs1_predecoded_SB_LUT4_I1_4_O [3:2], \core.xm_result [4] }; + assign \core.xm_rs2_SB_LUT4_I1_1_O [2:1] = { \core.mw_rd [4], \core.xm_rs2 [4] }; + assign \core.alu.op_b_inv_SB_LUT4_O_3_I1_SB_LUT4_O_I2 [1] = \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I1_O [2]; + assign { \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [3], \core.xm_result_SB_DFFER_Q_17_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_1_I2 [1:0] } = { \core.xm_result_SB_DFFER_Q_16_D_SB_LUT4_O_I0_SB_LUT4_O_I3_SB_LUT4_O_1_I1_SB_LUT4_I3_O [2], \core.alu.sum [1], \core.alu.sub_SB_LUT4_I2_O [0] }; + assign \core.csr_u.meifa_SB_DFFR_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I2 [1] = \core.csr_u.meicontext_preempt_SB_LUT4_I2_I0_SB_LUT4_O_I0 [1]; + assign \core.alu.sub_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_I2_SB_LUT4_I2_O [3] = \core.frontend.cir [12]; + assign \core.d_rs2_predecoded_SB_LUT4_I0_O [0] = \core.d_rs2_predecoded [3]; + assign { \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I2 [0] } = { \core.xm_result_SB_DFFER_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_1_I0_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_I2_I1_SB_LUT4_I2_O_SB_LUT4_I2_O [2], \core.xm_result_SB_DFFER_Q_22_D_SB_LUT4_O_I0_SB_LUT4_O_1_I1_SB_LUT4_O_I2_SB_LUT4_O_I1 [0] }; + assign d_hwdata_SB_LUT4_O_I0[3:1] = { bus_active_dph_s, dbg_sbus_wdata[31], d_hwdata_SB_LUT4_O_24_I2_SB_LUT4_I1_O[1] }; + assign \core.alu.op_b_inv_SB_LUT4_O_5_I1 [2] = \core.alu.op_a [26]; + assign { \core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O_I2 [2], \core.xm_result_SB_DFFER_Q_30_D_SB_LUT4_O_I2 [0] } = { \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I1_O [2], \core.csr_u.wdata_update_SB_LUT4_O_28_I0 [0] }; + assign { \core.decode_u.f_jump_target_SB_LUT4_O_14_I2 [2], \core.decode_u.f_jump_target_SB_LUT4_O_14_I2 [0] } = { \core.xm_delay_irq_entry_on_ls_dphase_SB_LUT4_I3_O_SB_LUT4_I1_O [2], \core.x_addr_sum [18] }; + assign \core.xm_sleep_wfi_SB_DFFER_Q_D_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_I2_O [0] = \core.decode_u.pc [31]; + assign \core.csr_u.wdata_update_SB_LUT4_O_31_I0 [3:1] = { dbg_data0_wdata[0], \core.frontend.mem_addr_vld_SB_LUT4_O_I2_SB_LUT4_O_I2_SB_LUT4_I1_O_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_I2_O [2:1] }; + assign \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [2] = 1'h1; + assign \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI [2:0] = { \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI [3], \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [0], 1'h1 }; + assign \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3 [2:0] = { \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI [3], \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_CI [3], \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [0] }; + assign \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI [4:1] = { \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [3], 1'h1, \core.m_reg_wen_SB_LUT4_O_I2_SB_LUT4_I1_I3_SB_CARRY_CO_I1 [1:0] }; + assign { \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [3], \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [1:0] } = { \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [4], \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI [0], 1'h1 }; + assign \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1 [3:0] = { \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [4], \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [4], \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI [2], \core.xm_except_SB_DFFES_Q_2_D_SB_LUT4_O_I1_SB_CARRY_CO_CI_SB_CARRY_CO_1_CI [0] }; + assign \core.d_addr_offs_SB_CARRY_I1_CO [0] = 1'h0; + assign \core.prev_instr_was_32_bit_SB_LUT4_I3_O [30:2] = 29'h1fffffff; + assign \core.prev_instr_was_32_bit_SB_LUT4_I3_O_SB_CARRY_I1_CO [0] = 1'h1; + assign \core.alu.sub_SB_CARRY_CI_CO [0] = \core.alu.sub ; + assign \core.decode_u.pc_seq_next_SB_LUT4_O_I3 [1:0] = { \core.decode_u.pc [2], 1'h0 }; + assign i_hready_SB_LUT4_I3_O_SB_CARRY_I0_CO[0] = 1'h0; + assign \core.frontend.fetch_addr_SB_DFFER_Q_D_SB_LUT4_O_I3 [1:0] = { \core.frontend.fetch_addr [2], 1'h0 }; + assign bus_gnt_ds_prev[0] = 1'hx; + assign clk_en = 1'h1; + assign \core.alu.aluop [5:4] = 2'h0; + assign \core.alu.clmul_mul.i = 32'd32; + assign \core.alu.cpop_count.i = 32'd32; + assign \core.alu.ctz_priority_encode.encode_u.encode.i = 6'h20; + assign \core.alu.ctz_priority_encode.priority_u.select.i = 32'd32; + assign \core.alu.do_zip_unzip.i = 32'd32; + assign \core.alu.funct3_32b = \core.frontend.cir [14:12]; + assign \core.alu.funct7_32b = \core.frontend.cir [31:25]; + assign \core.alu.op_a_rev = { \core.alu.op_a [0], \core.alu.op_a [1], \core.alu.op_a [2], \core.alu.op_a [3], \core.alu.op_a [4], \core.alu.op_a [5], \core.alu.op_a [6], \core.alu.op_a [7], \core.alu.op_a [8], \core.alu.op_a [9], \core.alu.op_a [10], \core.alu.op_a [11], \core.alu.op_a [12], \core.alu.op_a [13], \core.alu.op_a [14], \core.alu.op_a [15], \core.alu.op_a [16], \core.alu.op_a [17], \core.alu.op_a [18], \core.alu.op_a [19], \core.alu.op_a [20], \core.alu.op_a [21], \core.alu.op_a [22], \core.alu.op_a [23], \core.alu.op_a [24], \core.alu.op_a [25], \core.alu.op_a [26], \core.alu.op_a [27], \core.alu.op_a [28], \core.alu.op_a [29], \core.alu.op_a [30], \core.alu.op_a [31] }; + assign \core.alu.op_a_shifted = \core.alu.op_a ; + assign \core.alu.rev_op_a.i = 32'd32; + assign \core.alu.shift_rotate = 1'h0; + assign \core.alu.shifter.din = \core.alu.op_a ; + assign \core.alu.shifter.rotate = 1'h0; + assign \core.alu.shifter.shift.i = 32'd32; + assign \core.alu.unzip = { \core.alu.op_a [31], \core.alu.op_a [29], \core.alu.op_a [27], \core.alu.op_a [25], \core.alu.op_a [23], \core.alu.op_a [21], \core.alu.op_a [19], \core.alu.op_a [17], \core.alu.op_a [15], \core.alu.op_a [13], \core.alu.op_a [11], \core.alu.op_a [9], \core.alu.op_a [7], \core.alu.op_a [5], \core.alu.op_a [3], \core.alu.op_a [1], \core.alu.op_a [30], \core.alu.op_a [28], \core.alu.op_a [26], \core.alu.op_a [24], \core.alu.op_a [22], \core.alu.op_a [20], \core.alu.op_a [18], \core.alu.op_a [16], \core.alu.op_a [14], \core.alu.op_a [12], \core.alu.op_a [10], \core.alu.op_a [8], \core.alu.op_a [6], \core.alu.op_a [4], \core.alu.op_a [2], \core.alu.op_a [0] }; + assign \core.alu.zip = { \core.alu.op_a [31], \core.alu.op_a [15], \core.alu.op_a [30], \core.alu.op_a [14], \core.alu.op_a [29], \core.alu.op_a [13], \core.alu.op_a [28], \core.alu.op_a [12], \core.alu.op_a [27], \core.alu.op_a [11], \core.alu.op_a [26], \core.alu.op_a [10], \core.alu.op_a [25], \core.alu.op_a [9], \core.alu.op_a [24], \core.alu.op_a [8], \core.alu.op_a [23], \core.alu.op_a [7], \core.alu.op_a [22], \core.alu.op_a [6], \core.alu.op_a [21], \core.alu.op_a [5], \core.alu.op_a [20], \core.alu.op_a [4], \core.alu.op_a [19], \core.alu.op_a [3], \core.alu.op_a [18], \core.alu.op_a [2], \core.alu.op_a [17], \core.alu.op_a [1], \core.alu.op_a [16], \core.alu.op_a [0] }; + assign \core.bus_aph_excl_d = 1'h0; + assign \core.bus_aph_panic_i = 1'h0; + assign \core.bus_aph_req_i = \core.frontend.mem_addr_vld ; + assign \core.bus_dph_err_i = \core.frontend.mem_data_err ; + assign \core.bus_haddr_d [31:1] = { \core.x_addr_sum [31:2], \core.x_jump_misaligned }; + assign \core.bus_haddr_i = { i_haddr[31:2], 2'h0 }; + assign \core.bus_hsize_d [2] = 1'h0; + assign \core.bus_hsize_i = 3'h2; + assign \core.bus_priv_d = 1'h1; + assign \core.bus_priv_i = 1'h1; + assign \core.bus_rdata_d = d_hrdata; + assign \core.bus_rdata_i = i_hrdata; + assign \core.clk = clk; + assign \core.clk_always_on = clk_always_on; + assign \core.clk_en = 1'h1; + assign \core.csr_u.addr = \core.frontend.cir [31:20]; + assign \core.csr_u.clk = clk; + assign \core.csr_u.clk_always_on = clk_always_on; + assign \core.csr_u.dbg_data0_rdata = dbg_data0_rdata; + assign \core.csr_u.dbg_data0_wdata = dbg_data0_wdata; + assign \core.csr_u.dbg_data0_wen = 1'h0; + assign \core.csr_u.dbg_instr_caught_ebreak = 1'h0; + assign \core.csr_u.dbg_instr_caught_exception = 1'h0; + assign \core.csr_u.dbg_req_halt = dbg_req_halt; + assign \core.csr_u.dbg_req_halt_on_reset = dbg_req_halt_on_reset; + assign \core.csr_u.dbg_req_halt_prev = 1'h0; + assign \core.csr_u.dbg_req_resume = dbg_req_resume; + assign \core.csr_u.dbg_req_resume_prev = 1'h0; + assign \core.csr_u.dcsr_ebreakm = 1'h0; + assign \core.csr_u.dcsr_ebreaku = 1'h0; + assign \core.csr_u.dcsr_step = 1'h0; + assign \core.csr_u.debug_mode = 1'h0; + assign \core.csr_u.debug_suppresses_trap_update = 1'h0; + assign \core.csr_u.dpc = 32'd0; + assign \core.csr_u.eirq_compare.i = 32'd32; + assign \core.csr_u.eirq_encode_u.encode.i = 10'h020; + assign \core.csr_u.eirq_encode_u.gnt [8:5] = 4'h0; + assign \core.csr_u.eirq_highest_priority = 4'h0; + assign \core.csr_u.eirq_priority_u.active_layer_sel [15:1] = 15'h0000; + assign \core.csr_u.eirq_priority_u.level_has_req = { 15'h0000, \core.csr_u.eirq_priority_u.active_layer_sel [0] }; + assign \core.csr_u.eirq_priority_u.mux_reqs_by_layer.i = 32'd16; + assign \core.csr_u.eirq_priority_u.pri = 128'h00000000000000000000000000000000; + assign \core.csr_u.eirq_priority_u.prisel_layer.gnt = { 15'h0000, \core.csr_u.eirq_priority_u.active_layer_sel [0] }; + assign \core.csr_u.eirq_priority_u.prisel_layer.req = { 15'h0000, \core.csr_u.eirq_priority_u.active_layer_sel [0] }; + assign \core.csr_u.eirq_priority_u.prisel_layer.select.i = 32'd16; + assign \core.csr_u.eirq_priority_u.prisel_tiebreak.select.i = 32'd32; + assign \core.csr_u.eirq_priority_u.req_stratified[10] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[11] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[12] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[13] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[14] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[15] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[1] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[2] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[3] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[4] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[5] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[6] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[7] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[8] = 32'd0; + assign \core.csr_u.eirq_priority_u.req_stratified[9] = 32'd0; + assign \core.csr_u.eirq_priority_u.stratify.i = 32'd16; + assign \core.csr_u.eirq_priority_u.stratify.j = 32'd32; + assign \core.csr_u.enter_debug_mode = 1'h0; + assign \core.csr_u.except = \core.xm_except ; + assign \core.csr_u.get_highest_eirq_priority.i = 32'd32; + assign \core.csr_u.have_just_reset = 1'h0; + assign \core.csr_u.irq = irq; + assign \core.csr_u.irq_software = soft_irq; + assign \core.csr_u.irq_timer = timer_irq; + assign \core.csr_u.m_mode = 1'h1; + assign \core.csr_u.m_mode_execution = 1'h1; + assign \core.csr_u.m_mode_loadstore = 1'h1; + assign \core.csr_u.m_mode_trap_entry = 1'h1; + assign \core.csr_u.match_mrw = 1'h1; + assign \core.csr_u.match_urw = 1'h0; + assign \core.csr_u.mcause_irq_num [0] = \core.csr_u.mcause_irq_num [1]; + assign \core.csr_u.meicontext_pppreempt = 4'h0; + assign \core.csr_u.meicontext_ppreempt = 4'h0; + assign \core.csr_u.meicontext_preempt [3:0] = 4'h0; + assign \core.csr_u.meiea [511:32] = 480'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + assign \core.csr_u.meifa [511:32] = 480'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + assign \core.csr_u.meinext_irq [8:5] = 4'h0; + assign \core.csr_u.meinext_irq_unmasked = { 4'h0, \core.csr_u.eirq_encode_u.gnt [4:0] }; + assign \core.csr_u.meipa [511:32] = 480'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + assign \core.csr_u.meipra = 2048'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + assign \core.csr_u.mepc [1:0] = 2'h0; + assign \core.csr_u.mepc_in [0] = 1'h0; + assign { \core.csr_u.mie [31:12], \core.csr_u.mie [10:8], \core.csr_u.mie [6:4], \core.csr_u.mie [2:0] } = 29'h00000000; + assign { \core.csr_u.mip [31:12], \core.csr_u.mip [10:0] } = { 23'h000000, \core.csr_u.irq_timer_r , 3'h0, \core.csr_u.irq_software_r , 3'h0 }; + assign \core.csr_u.msleep_deepsleep = 1'h0; + assign \core.csr_u.msleep_powerdown = 1'h0; + assign \core.csr_u.msleep_sleeponblock = 1'h0; + assign \core.csr_u.mstatus_mpp = 1'h1; + assign \core.csr_u.mstatus_tw = 1'h0; + assign \core.csr_u.mtvec = { \core.csr_u.mtvec_reg [31:2], 2'h0 }; + assign \core.csr_u.mtvec_reg [1:0] = { 1'hx, \core.csr_u.irq_vector_enable }; + assign \core.csr_u.pending_dbg_resume = 1'h0; + assign \core.csr_u.pending_dbg_resume_prev = 1'h0; + assign \core.csr_u.pmp_cfg_addr = \core.frontend.cir [31:20]; + assign \core.csr_u.pmp_cfg_rdata = 32'd0; + assign \core.csr_u.pmp_cfg_wdata = \core.csr_u.wdata_update ; + assign \core.csr_u.pmp_cfg_wen = 1'h0; + assign \core.csr_u.preempt_level_next = 5'h10; + assign \core.csr_u.pwr_allow_power_down = 1'h0; + assign \core.csr_u.pwr_allow_sleep = 1'h0; + assign \core.csr_u.pwr_allow_sleep_on_block = 1'h0; + assign \core.csr_u.rst_n = rst_n; + assign \core.csr_u.standard_irq_num [0] = \core.csr_u.standard_irq_num [1]; + assign \core.csr_u.step_halt_req = 1'h0; + assign \core.csr_u.trap_addr [1:0] = 2'h0; + assign \core.csr_u.trap_is_debug_entry = 1'h0; + assign \core.csr_u.trap_wfi = 1'h0; + assign \core.csr_u.trig_cfg_addr = \core.frontend.cir [31:20]; + assign \core.csr_u.trig_cfg_rdata = 32'd0; + assign \core.csr_u.trig_cfg_wdata = \core.csr_u.wdata_update ; + assign \core.csr_u.trig_cfg_wen = 1'h0; + assign \core.csr_u.vector_sel [0] = \core.csr_u.vector_sel [1]; + assign \core.csr_u.want_halt_except = 1'h0; + assign \core.csr_u.want_halt_irq = 1'h0; + assign \core.csr_u.want_halt_irq_if_no_exception = 1'h0; + assign \core.csr_u.wdata = dbg_data0_wdata; + assign { \core.d_addr_offs [31:20], \core.d_addr_offs [10:5] } = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31:25] }; + assign \core.d_aluop = { 2'h0, \core.alu.aluop [3:0] }; + assign \core.d_btb_target_addr = 32'd0; + assign \core.d_fence_i = 1'h0; + assign \core.d_funct3_32b = \core.frontend.cir [14:12]; + assign \core.d_funct7_32b = \core.frontend.cir [31:25]; + assign \core.d_memop [3] = 1'h0; + assign \core.d_memop_is_amo = 1'h0; + assign \core.d_mulop = 3'h0; + assign \core.d_pc = { \core.decode_u.pc [31:1], 1'h0 }; + assign \core.d_sleep_block = 1'h0; + assign \core.d_sleep_unblock = 1'h0; + assign \core.dbg_data0_rdata = dbg_data0_rdata; + assign \core.dbg_data0_wdata = dbg_data0_wdata; + assign \core.dbg_data0_wen = 1'h0; + assign \core.dbg_halted = 1'h0; + assign \core.dbg_instr_caught_ebreak = 1'h0; + assign \core.dbg_instr_caught_exception = 1'h0; + assign \core.dbg_instr_data = dbg_instr_data; + assign \core.dbg_instr_data_rdy = 1'h0; + assign \core.dbg_instr_data_vld = dbg_instr_data_vld; + assign \core.dbg_req_halt = dbg_req_halt; + assign \core.dbg_req_halt_on_reset = dbg_req_halt_on_reset; + assign \core.dbg_req_resume = dbg_req_resume; + assign \core.dbg_running = 1'h0; + assign \core.debug_mode = 1'h0; + assign \core.decode_u.branch_offs = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [7], \core.frontend.cir [30:25], \core.frontend.cir [11:8], 1'h0 }; + assign \core.decode_u.clk = clk; + assign \core.decode_u.d_addr_offs = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.d_addr_offs [19:11], \core.frontend.cir [30:25], \core.d_addr_offs [4:0] }; + assign \core.decode_u.d_aluop = { 2'h0, \core.alu.aluop [3:0] }; + assign \core.decode_u.d_btb_target_addr = 32'd0; + assign \core.decode_u.d_fence_i = 1'h0; + assign \core.decode_u.d_funct3_32b = \core.frontend.cir [14:12]; + assign \core.decode_u.d_funct7_32b = \core.frontend.cir [31:25]; + assign \core.decode_u.d_imm_b = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [7], \core.frontend.cir [30:25], \core.frontend.cir [11:8], 1'h0 }; + assign \core.decode_u.d_imm_i = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31:20] }; + assign \core.decode_u.d_imm_j = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [19:12], \core.frontend.cir [20], \core.frontend.cir [30:21], 1'h0 }; + assign \core.decode_u.d_imm_s = { \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31], \core.frontend.cir [31:25], \core.frontend.cir [11:7] }; + assign \core.decode_u.d_imm_u = { \core.frontend.cir [31:12], 12'h000 }; + assign \core.decode_u.d_instr = \core.frontend.cir ; + assign \core.decode_u.d_instr_is_32bit = 1'h1; + assign \core.decode_u.d_invalid_16bit = 1'h0; + assign \core.decode_u.d_memop = { \core.d_memop [4], 1'h0, \core.d_memop [2:0] }; + assign \core.decode_u.d_mulop = 3'h0; + assign \core.decode_u.d_pc = { \core.decode_u.pc [31:1], 1'h0 }; + assign \core.decode_u.d_rs2 = \core.d_rs2 ; + assign \core.decode_u.d_sleep_block = 1'h0; + assign \core.decode_u.d_sleep_unblock = 1'h0; + assign \core.decode_u.debug_mode = 1'h0; + assign \core.decode_u.decomp.imm_cb = { \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [6:5], \core.frontend.cir [2], 13'h0000, \core.frontend.cir [11:10], \core.frontend.cir [4:3], \core.frontend.cir [12], 7'h00 }; + assign \core.decode_u.decomp.imm_ci = { \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [6:2], 20'h00000 }; + assign \core.decode_u.decomp.imm_cj = { \core.frontend.cir [12], \core.frontend.cir [8], \core.frontend.cir [10:9], \core.frontend.cir [6], \core.frontend.cir [7], \core.frontend.cir [2], \core.frontend.cir [11], \core.frontend.cir [5:3], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], \core.frontend.cir [12], 12'h000 }; + assign \core.decode_u.decomp.instr_in = \core.frontend.cir ; + assign \core.decode_u.decomp.instr_is_32bit = 1'h1; + assign \core.decode_u.decomp.instr_out = \core.frontend.cir ; + assign \core.decode_u.decomp.invalid = 1'h0; + assign \core.decode_u.decomp.rd_l = \core.frontend.cir [11:7]; + assign \core.decode_u.decomp.rd_s = { 2'h1, \core.frontend.cir [4:2] }; + assign \core.decode_u.decomp.rs1_l = \core.frontend.cir [11:7]; + assign \core.decode_u.decomp.rs1_s = { 2'h1, \core.frontend.cir [9:7] }; + assign \core.decode_u.decomp.rs2_l = \core.frontend.cir [6:2]; + assign \core.decode_u.decomp.rs2_s = { 2'h1, \core.frontend.cir [4:2] }; + assign \core.decode_u.df_cir_use = { \core.df_cir_use [1], 1'h0 }; + assign \core.decode_u.f_jump_target [0] = 1'h0; + assign \core.decode_u.fd_cir = \core.frontend.cir ; + assign \core.decode_u.fd_cir_err = \core.frontend.cir_bus_err [1:0]; + assign \core.decode_u.fd_cir_vld = \core.frontend.cir_vld ; + assign \core.decode_u.m_mode = 1'h1; + assign \core.decode_u.partial_predicted_branch = 1'h0; + assign \core.decode_u.pc [0] = 1'h0; + assign \core.decode_u.pc_seq_next [1:0] = { \core.decode_u.pc [1], 1'h0 }; + assign \core.decode_u.predicted_branch = 1'h0; + assign \core.decode_u.rst_n = rst_n; + assign \core.decode_u.trap_wfi = 1'h0; + assign \core.df_cir_use [0] = 1'h0; + assign \core.f_jump_priv = 1'h1; + assign \core.f_jump_target = { \core.decode_u.f_jump_target [31:1], 1'h0 }; + assign \core.f_mem_size = 1'h1; + assign \core.f_rs1_coarse = \core.frontend.next_instr [19:15]; + assign \core.f_rs1_fine = \core.frontend.next_instr [19:15]; + assign \core.f_rs2_coarse = \core.frontend.next_instr [24:20]; + assign \core.f_rs2_fine = \core.frontend.next_instr [24:20]; + assign \core.fd_cir = \core.frontend.cir ; + assign \core.fd_cir_err = \core.frontend.cir_bus_err [1:0]; + assign \core.fd_cir_vld = \core.frontend.cir_vld ; + assign \core.frontend.boundary_conditions.i = 32'd2; + assign \core.frontend.btb_match_current_addr = 1'h0; + assign \core.frontend.btb_match_next_addr = 1'h0; + assign \core.frontend.btb_match_word = 1'h0; + assign \core.frontend.btb_set = 1'h0; + assign \core.frontend.btb_set_src_addr = { \core.decode_u.pc [31:1], 1'h0 }; + assign \core.frontend.btb_set_target_addr = { \core.x_addr_sum [31:2], \core.x_jump_misaligned , 1'h0 }; + assign \core.frontend.btb_src_addr = 32'd0; + assign \core.frontend.btb_src_overhanging = 1'h0; + assign \core.frontend.btb_target_addr = 32'd0; + assign \core.frontend.btb_target_addr_out = 32'd0; + assign \core.frontend.btb_valid = 1'h0; + assign \core.frontend.buf_level [1] = \core.frontend.cir_vld [1]; + assign \core.frontend.cir_bus_err [2] = 1'h0; + assign \core.frontend.cir_bus_err_plus_fetch [2] = 1'h0; + assign \core.frontend.cir_bus_err_shifted [2:1] = 2'h0; + assign \core.frontend.cir_err = \core.frontend.cir_bus_err [1:0]; + assign \core.frontend.cir_use = { \core.df_cir_use [1], 1'h0 }; + assign \core.frontend.clk = clk; + assign \core.frontend.dbg_instr_data = dbg_instr_data; + assign \core.frontend.dbg_instr_data_rdy = 1'h0; + assign \core.frontend.dbg_instr_data_vld = dbg_instr_data_vld; + assign \core.frontend.debug_mode = 1'h0; + assign \core.frontend.fetch_addr [1:0] = 2'h0; + assign \core.frontend.fetch_data_hwvld [0] = 1'h1; + assign \core.frontend.fetch_priv = 1'h1; + assign \core.frontend.fifo_dbg_inject = 1'h0; + assign \core.frontend.fifo_err[2] = 1'h0; + assign \core.frontend.fifo_mem[2] = i_hrdata; + assign \core.frontend.fifo_predbranch[2] = 2'h0; + assign \core.frontend.fifo_rdata = \core.frontend.fifo_mem[0] ; + assign \core.frontend.fifo_valid[0] = \core.frontend.fifo_almost_full ; + assign \core.frontend.fifo_valid[1] = \core.frontend.fifo_full ; + assign \core.frontend.fifo_valid[2] = 1'h0; + assign \core.frontend.fifo_valid_hw[0] [0] = \core.frontend.fifo_almost_full ; + assign \core.frontend.fifo_valid_hw[1] [0] = \core.frontend.fifo_full ; + assign \core.frontend.fifo_valid_hw[2] = 2'h0; + assign \core.frontend.hwbuf = 16'h0000; + assign \core.frontend.instr_data_plus_fetch = { 16'h0000, \core.frontend.next_instr }; + assign { \core.frontend.instr_data_shifted [47:16], \core.frontend.instr_data_shifted [14:0] } = { 23'h000000, \core.frontend.cir [24:16], 15'h0000 }; + assign \core.frontend.jump_priv = 1'h1; + assign \core.frontend.jump_target = { \core.decode_u.f_jump_target [31:1], 1'h0 }; + assign \core.frontend.level_next_no_fetch [0] = \core.frontend.buf_level [0]; + assign \core.frontend.mem_addr = { i_haddr[31:2], 2'h0 }; + assign \core.frontend.mem_addr_r = { i_haddr[31:2], 2'h0 }; + assign \core.frontend.mem_data = i_hrdata; + assign \core.frontend.mem_data_hwvld = 2'h3; + assign \core.frontend.mem_priv = 1'h1; + assign \core.frontend.mem_priv_r = 1'h1; + assign \core.frontend.mem_size = 1'h1; + assign \core.frontend.next_instr_is_32bit = 1'h1; + assign \core.frontend.predecode_rs1_coarse = \core.frontend.next_instr [19:15]; + assign \core.frontend.predecode_rs1_fine = \core.frontend.next_instr [19:15]; + assign \core.frontend.predecode_rs2_coarse = \core.frontend.next_instr [24:20]; + assign \core.frontend.predecode_rs2_fine = \core.frontend.next_instr [24:20]; + assign \core.frontend.rst_n = rst_n; + assign \core.irq = irq; + assign \core.m_exception_return_addr = { \core.csr_u.mepc_in [31:1], 1'h0 }; + assign \core.m_fast_mul_result = 32'd0; + assign \core.m_fast_mul_result_vld = 1'h0; + assign \core.m_mmode_trap_entry = 1'h1; + assign \core.m_pwr_allow_power_down = 1'h0; + assign \core.m_pwr_allow_sleep = 1'h0; + assign \core.m_pwr_allow_sleep_on_block = 1'h0; + assign \core.m_sleep_stall_release = \core.power_ctrl.stall_release ; + assign \core.m_trap_addr = { \core.csr_u.trap_addr [31:2], 2'h0 }; + assign \core.m_trap_is_debug_entry = 1'h0; + assign \core.power_ctrl.allow_power_down = 1'h0; + assign \core.power_ctrl.allow_sleep = 1'h0; + assign \core.power_ctrl.allow_sleep_on_block = 1'h0; + assign \core.power_ctrl.block_wakeup_req_pulse = unblock_in; + assign \core.power_ctrl.clk_always_on = clk_always_on; + assign \core.power_ctrl.clk_en = 1'h1; + assign \core.power_ctrl.pwrup_ack = pwrup_ack; + assign \core.power_ctrl.pwrup_req = 1'h1; + assign \core.power_ctrl.rst_n = rst_n; + assign \core.power_ctrl.sleeping_on_block = 1'h0; + assign \core.power_ctrl.sleeping_on_wfi = \core.xm_sleep_wfi ; + assign \core.pwrup_ack = pwrup_ack; + assign \core.pwrup_req = 1'h1; + assign \core.regs.clk = clk; + assign \core.regs.rst_n = rst_n; + assign \core.regs.waddr = \core.xm_rd ; + assign \core.regs.wdata = \core.m_result ; + assign \core.regs.wen = \core.m_reg_wen ; + assign \core.rst_n = rst_n; + assign \core.soft_irq = soft_irq; + assign \core.timer_irq = timer_irq; + assign \core.unblock_in = unblock_in; + assign \core.unblock_out = 1'h0; + assign \core.x_addr_sum [1:0] = { \core.x_jump_misaligned , \core.bus_haddr_d [0] }; + assign \core.x_branch_was_predicted = 1'h0; + assign \core.x_btb_set = 1'h0; + assign \core.x_btb_set_src_addr = { \core.decode_u.pc [31:1], 1'h0 }; + assign \core.x_btb_set_target_addr = { \core.x_addr_sum [31:2], \core.x_jump_misaligned , 1'h0 }; + assign \core.x_csr_wdata = dbg_data0_wdata; + assign \core.x_exec_pmp_fail = 1'h0; + assign \core.x_jump_target = { \core.x_addr_sum [31:2], \core.x_jump_misaligned , 1'h0 }; + assign \core.x_loadstore_pmp_fail = 1'h0; + assign \core.x_mmode_execution = 1'h1; + assign \core.x_mmode_loadstore = 1'h1; + assign \core.x_muldiv_result = 32'd0; + assign \core.x_op_a = \core.alu.op_a ; + assign \core.x_pmp_cfg_addr = \core.frontend.cir [31:20]; + assign \core.x_pmp_cfg_rdata = 32'd0; + assign \core.x_pmp_cfg_wdata = \core.csr_u.wdata_update ; + assign \core.x_pmp_cfg_wen = 1'h0; + assign \core.x_rdata1 = \core.regs.rdata1 ; + assign \core.x_rdata2 = \core.regs.rdata2 ; + assign \core.x_stall_muldiv = 1'h0; + assign \core.x_stall_on_amo = 1'h0; + assign \core.x_stall_on_exclusive_overlap = 1'h0; + assign \core.x_trap_wfi = 1'h0; + assign \core.x_trig_break = 1'h0; + assign \core.x_trig_break_d_mode = 1'h0; + assign \core.x_trig_cfg_addr = \core.frontend.cir [31:20]; + assign \core.x_trig_cfg_rdata = 32'd0; + assign \core.x_trig_cfg_wdata = \core.csr_u.wdata_update ; + assign \core.x_trig_cfg_wen = 1'h0; + assign \core.x_use_fast_mul = 1'h0; + assign \core.xm_memop [3] = 1'h0; + assign \core.xm_sleep_block = 1'h0; + assign core_aph_excl_d = 1'h0; + assign core_aph_req_i = \core.frontend.mem_addr_vld ; + assign core_dph_err_i = \core.frontend.mem_data_err ; + assign core_haddr_d = { \core.x_addr_sum [31:2], \core.x_jump_misaligned , \core.bus_haddr_d [0] }; + assign core_haddr_i = { i_haddr[31:2], 2'h0 }; + assign core_hsize_d = { 1'h0, \core.bus_hsize_d [1:0] }; + assign core_hsize_i = 3'h2; + assign core_priv_d = 1'h1; + assign core_priv_i = 1'h1; + assign core_rdata_d = d_hrdata; + assign core_rdata_i = i_hrdata; + assign d_hburst = 3'h0; + assign d_hexcl = 1'h0; + assign d_hmaster = { 7'h00, bus_gnt_s }; + assign d_hmastlock = 1'h0; + assign d_hprot = 4'h3; + assign d_hsize[2] = 1'h0; + assign d_htrans[0] = 1'h0; + assign dbg_data0_wen = 1'h0; + assign dbg_halted = 1'h0; + assign dbg_instr_caught_ebreak = 1'h0; + assign dbg_instr_caught_exception = 1'h0; + assign dbg_instr_data_rdy = 1'h0; + assign dbg_running = 1'h0; + assign dbg_sbus_rdata = d_hrdata; + assign i_haddr[1:0] = 2'h0; + assign i_hburst = 3'h0; + assign i_hmaster = 8'h00; + assign i_hmastlock = 1'h0; + assign i_hprot = 4'h2; + assign i_hsize = 3'h2; + assign i_htrans = { \core.frontend.mem_addr_vld , 1'h0 }; + assign i_hwdata = 32'd0; + assign i_hwrite = 1'h0; + assign pwrup_req = 1'h1; + assign unblock_out = 1'h0; +endmodule