Do not rely on environment variables for any intra-project paths

It's no longer necessary to source `sourceme` before running any
of the project Makefiles.
This commit is contained in:
Luke Wren 2024-05-27 16:52:54 +01:00
parent 8b9503c804
commit d239de803c
16 changed files with 61 additions and 28 deletions
Readme.md
example_soc
project_env.shproject_paths.mkscriptssourceme
test
formal
bus_compliance_1port
bus_compliance_2port
frontend_fetch_match
instruction_fetch_match
project_paths.mk
project_paths.mk
sim

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@ -99,9 +99,6 @@ Make sure you have done a _recursive_ clone of the Hazard3 repository. Build the
```bash
cd hazard3
# Set up some paths, add RISC-V toolchain to PATH
. sourceme
cd test/sim/tb_cxxrtl
make
```
@ -270,7 +267,6 @@ Note there is no software tree for this SoC. For now you'll have to read the sou
```bash
cd hazard3
. sourceme
cd example_soc/synth
make -f Icebreaker.mk prog
# Should be able to attach to the processor
@ -281,7 +277,6 @@ riscv-openocd -f ../icebreaker-openocd.cfg
```bash
cd hazard3
. sourceme
cd example_soc/synth
make -f ULX3S.mk flash
# Should be able to attach to the processor

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@ -0,0 +1,2 @@
# Link up to project root
include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../project_paths.mk

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@ -1,8 +1,9 @@
include ../project_paths.mk
CHIPNAME=fpga_icebreaker
DOTF=../fpga/fpga_icebreaker.f
SYNTH_OPT=-dsp
PNR_OPT=--timing-allow-fail
PNR_OPT=--timing-allow-fail --detailed-timing-report
DEVICE=up5k
PACKAGE=sg48

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@ -1,3 +1,5 @@
include ../project_paths.mk
CHIPNAME=fpga_ulx3s
TOP=fpga_ulx3s
DOTF=../fpga/fpga_ulx3s.f

10
project_env.sh Normal file
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@ -0,0 +1,10 @@
# Source this file to add paths and tools to your shell environment. The stock
# Makefiles should work fine with just project_dir_paths.mk but it can be
# convenient to have everything available in your shell.
export PROJ_ROOT = $(git rev-parse --show-toplevel)
export HDL = ${PROJ_ROOT}/hdl
export SCRIPTS = ${PROJ_ROOT}/scripts
export PATH = "${PATH}:${PROJ_ROOT}/scripts"
export PATH = "${PATH}:/opt/riscv/bin"

7
project_paths.mk Normal file
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@ -0,0 +1,7 @@
# Set up root paths used by Makefiles (there is a lot of cross-referencing,
# e.g. tests referencing the HDL directory). This .mk file is
# (eventually) included by every Makefile in the project.
PROJ_ROOT := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
HDL := $(PROJ_ROOT)/hdl
SCRIPTS := $(PROJ_ROOT)/scripts

@ -1 +1 @@
Subproject commit 77fecbee4a0b9194d6a99ee6c49243b0d2b90d8d
Subproject commit 841ed3ec1717ce490587b1ad7456bc77faf9a2f3

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@ -1,6 +0,0 @@
export PROJ_ROOT=$PWD
export HDL=$PROJ_ROOT/hdl
export SCRIPTS=$PROJ_ROOT/scripts
export PATH="$PATH:$PWD/scripts"
export PATH="$PATH:/opt/riscv/bin"

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@ -1,3 +1,5 @@
include ../project_paths.mk
DOTF=tb.f
TOP=tb
YOSYS_SMT_SOLVER=z3

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@ -1,3 +1,5 @@
include ../project_paths.mk
DOTF=tb.f
TOP=tb
YOSYS_SMT_SOLVER=z3

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@ -1,3 +1,5 @@
include ../project_paths.mk
DOTF=tb.f
TOP=tb
YOSYS_SMT_SOLVER=z3

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@ -1,3 +1,5 @@
include ../project_paths.mk
DOTF=tb.f
TOP=tb
YOSYS_SMT_SOLVER=z3

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@ -0,0 +1,2 @@
# Link up to project root
include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../project_paths.mk

2
test/project_paths.mk Normal file
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@ -0,0 +1,2 @@
# Link up to project root
include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../project_paths.mk

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@ -0,0 +1,2 @@
# Link up to project root
include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../project_paths.mk

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@ -1,29 +1,37 @@
# To build single-core dual-port tb: make
# To build dual-core single-port tb: make DOTF=tb_multicore.f
TOP := tb
DOTF := tb.f
CONFIG := default
TBEXEC := $(patsubst %.f,%,$(DOTF))
include ../project_paths.mk
TOP := tb
DOTF := tb.f
CONFIG := default
TBEXEC := $(patsubst %.f,%,$(DOTF))
FILE_LIST := $(shell HDL=$(HDL) $(SCRIPTS)/listfiles $(DOTF))
BUILD_DIR := build-$(patsubst %.f,%,$(DOTF))
# Note: clang++-18 has a >20x compile time regression, even at low
# optimisation levels. I have tried clang++-16 and clang++-17, both fine.
CLANGXX := clang++-16
CLANGXX := clang++-16
.PHONY: clean all
.PHONY: clean all lint
all: $(TBEXEC)
SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(shell listfiles $(DOTF));
SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh" $(FILE_LIST);
SYNTH_CMD += hierarchy -top $(TOP);
SYNTH_CMD += write_cxxrtl build-$(DOTF)/dut.cpp
SYNTH_CMD += write_cxxrtl $(BUILD_DIR)/dut.cpp
build-$(DOTF)/dut.cpp: $(shell listfiles $(DOTF)) $(wildcard *.vh)
mkdir -p build-$(DOTF)
yosys -p '$(SYNTH_CMD)' 2>&1 > build-$(DOTF)/cxxrtl.log
$(BUILD_DIR)/dut.cpp: $(FILE_LIST) $(wildcard *.vh)
mkdir -p $(BUILD_DIR)
yosys -p '$(SYNTH_CMD)' 2>&1 > $(BUILD_DIR)/cxxrtl.log
clean::
rm -rf build-$(DOTF) $(TBEXEC)
rm -rf $(BUILD_DIR) $(TBEXEC)
$(TBEXEC): build-$(DOTF)/dut.cpp tb.cpp
$(CLANGXX) -O3 -std=c++14 $(addprefix -D,$(CDEFINES) $(CDEFINES_$(DOTF))) -I $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime -I build-$(DOTF) tb.cpp -o $(TBEXEC)
$(TBEXEC): $(BUILD_DIR)/dut.cpp tb.cpp
$(CLANGXX) -O3 -std=c++14 $(addprefix -D,$(CDEFINES) $(CDEFINES_$(DOTF))) -I $(shell yosys-config --datdir)/include/backends/cxxrtl/runtime -I $(BUILD_DIR) tb.cpp -o $(TBEXEC)
lint:
verilator --lint-only --top-module $(TOP) -I$(HDL) $(FILE_LIST)