More width tweaks
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@ -440,12 +440,12 @@ always @ (*) begin
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// feed back through the ALU.
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if (|EXTENSION_A && x_amo_phase == 3'h2)
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x_op_a = mw_result;
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else if (|d_alusrc_a)
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else if (d_alusrc_a)
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x_op_a = d_pc;
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else
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x_op_a = x_rs1_bypass;
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if (|d_alusrc_b)
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if (d_alusrc_b)
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x_op_b = d_imm;
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else
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x_op_b = x_rs2_bypass;
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@ -933,7 +933,7 @@ hazard3_csr #(
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// Other CSR-specific signalling
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.permit_wfi (x_permit_wfi),
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.instr_ret (|x_instr_ret)
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.instr_ret (x_instr_ret)
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);
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// Pipe register
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@ -287,6 +287,8 @@ always @ (*) begin
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RV_SEXT_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_SEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_XNOR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_XNOR; end else begin d_invalid_32bit = 1'b1; end
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// Note: ZEXT_H is a subset of PACK from Zbkb. This is fine as long as
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// this case appears first, since Zbkb implies Zbb on Hazard3.
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RV_ZEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ZEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
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RV_CLMUL: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end
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@ -86,7 +86,7 @@ end else begin: instr_decompress
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RV_C_ADDI4SPN: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_s) | rfmt_rs1(5'h2)
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| {2'h0, instr_in[10:7], instr_in[12:11], instr_in[5], instr_in[6], 2'b00, 20'h00000};
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RV_C_LW: instr_out = RV_NOZ_LW | rfmt_rd(rd_s) | rfmt_rs1(rs1_s)
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| {6'h00, instr_in[5], instr_in[12:10], instr_in[6], 2'b00, 20'h00000};
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| {5'h00, instr_in[5], instr_in[12:10], instr_in[6], 2'b00, 20'h00000};
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RV_C_SW: instr_out = RV_NOZ_SW | rfmt_rs2(rs2_s) | rfmt_rs1(rs1_s)
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| {5'h00, instr_in[5], instr_in[12], 13'h000, instr_in[11:10], instr_in[6], 2'b00, 7'h00};
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RV_C_ADDI: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | imm_ci;
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