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More width tweaks

This commit is contained in:
Luke Wren 2022-08-20 16:11:58 +01:00
parent bc274867c0
commit d299a3ca4e
3 changed files with 6 additions and 4 deletions
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6
hdl/hazard3_core.v
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@ -440,12 +440,12 @@ always @ (*) begin
// feed back through the ALU. // feed back through the ALU.
if (|EXTENSION_A && x_amo_phase == 3'h2) if (|EXTENSION_A && x_amo_phase == 3'h2)
x_op_a = mw_result; x_op_a = mw_result;
else if (|d_alusrc_a) else if (d_alusrc_a)
x_op_a = d_pc; x_op_a = d_pc;
else else
x_op_a = x_rs1_bypass; x_op_a = x_rs1_bypass;
if (|d_alusrc_b) if (d_alusrc_b)
x_op_b = d_imm; x_op_b = d_imm;
else else
x_op_b = x_rs2_bypass; x_op_b = x_rs2_bypass;
@ -933,7 +933,7 @@ hazard3_csr #(
// Other CSR-specific signalling // Other CSR-specific signalling
.permit_wfi (x_permit_wfi), .permit_wfi (x_permit_wfi),
.instr_ret (|x_instr_ret) .instr_ret (x_instr_ret)
); );
// Pipe register // Pipe register

2
hdl/hazard3_decode.v
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@ -287,6 +287,8 @@ always @ (*) begin
RV_SEXT_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end RV_SEXT_B: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_B; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
RV_SEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end RV_SEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_SEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
RV_XNOR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_XNOR; end else begin d_invalid_32bit = 1'b1; end RV_XNOR: if (EXTENSION_ZBB) begin d_aluop = ALUOP_XNOR; end else begin d_invalid_32bit = 1'b1; end
// Note: ZEXT_H is a subset of PACK from Zbkb. This is fine as long as
// this case appears first, since Zbkb implies Zbb on Hazard3.
RV_ZEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ZEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end RV_ZEXT_H: if (EXTENSION_ZBB) begin d_aluop = ALUOP_ZEXT_H; d_rs2 = X0; end else begin d_invalid_32bit = 1'b1; end
RV_CLMUL: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end RV_CLMUL: if (EXTENSION_ZBC) begin d_aluop = ALUOP_CLMUL; end else begin d_invalid_32bit = 1'b1; end

2
hdl/hazard3_instr_decompress.v
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@ -86,7 +86,7 @@ end else begin: instr_decompress
RV_C_ADDI4SPN: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_s) | rfmt_rs1(5'h2) RV_C_ADDI4SPN: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_s) | rfmt_rs1(5'h2)
| {2'h0, instr_in[10:7], instr_in[12:11], instr_in[5], instr_in[6], 2'b00, 20'h00000}; | {2'h0, instr_in[10:7], instr_in[12:11], instr_in[5], instr_in[6], 2'b00, 20'h00000};
RV_C_LW: instr_out = RV_NOZ_LW | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) RV_C_LW: instr_out = RV_NOZ_LW | rfmt_rd(rd_s) | rfmt_rs1(rs1_s)
| {6'h00, instr_in[5], instr_in[12:10], instr_in[6], 2'b00, 20'h00000}; | {5'h00, instr_in[5], instr_in[12:10], instr_in[6], 2'b00, 20'h00000};
RV_C_SW: instr_out = RV_NOZ_SW | rfmt_rs2(rs2_s) | rfmt_rs1(rs1_s) RV_C_SW: instr_out = RV_NOZ_SW | rfmt_rs2(rs2_s) | rfmt_rs1(rs1_s)
| {5'h00, instr_in[5], instr_in[12], 13'h000, instr_in[11:10], instr_in[6], 2'b00, 7'h00}; | {5'h00, instr_in[5], instr_in[12], 13'h000, instr_in[11:10], instr_in[6], 2'b00, 7'h00};
RV_C_ADDI: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | imm_ci; RV_C_ADDI: instr_out = RV_NOZ_ADDI | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | imm_ci;