From d3667769d247231a4caf1895711a57bbaefc6035 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Sat, 8 Oct 2022 16:50:58 +0100
Subject: [PATCH] Arrange for address buses to be 0 when processor is held in
reset
---
hdl/hazard3_decode.v | 25 ++++++++++++++-----------
hdl/hazard3_frontend.v | 14 +++++++-------
2 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/hdl/hazard3_decode.v b/hdl/hazard3_decode.v
index 0eae47f..5b4cec5 100644
--- a/hdl/hazard3_decode.v
+++ b/hdl/hazard3_decode.v
@@ -348,17 +348,20 @@ always @ (*) begin
endcase
if (d_invalid || d_starved || d_except_instr_bus_fault || partial_predicted_branch) begin
- d_rs1 = {W_REGADDR{1'b0}};
- d_rs2 = {W_REGADDR{1'b0}};
- d_rd = {W_REGADDR{1'b0}};
- d_memop = MEMOP_NONE;
- d_branchcond = BCOND_NEVER;
- d_csr_ren = 1'b0;
- d_csr_wen = 1'b0;
- d_except = EXCEPT_NONE;
- d_sleep_wfi = 1'b0;
- d_sleep_block = 1'b0;
- d_sleep_unblock = 1'b0;
+ d_rs1 = {W_REGADDR{1'b0}};
+ d_rs2 = {W_REGADDR{1'b0}};
+ d_rd = {W_REGADDR{1'b0}};
+ d_memop = MEMOP_NONE;
+ d_branchcond = BCOND_NEVER;
+ d_csr_ren = 1'b0;
+ d_csr_wen = 1'b0;
+ d_except = EXCEPT_NONE;
+ d_sleep_wfi = 1'b0;
+ d_sleep_block = 1'b0;
+ d_sleep_unblock = 1'b0;
+ // Ensure address bus is 0 in reset if register file is resettable:
+ d_addr_is_regoffs = 1'b1;
+
if (EXTENSION_M)
d_aluop = ALUOP_ADD;
diff --git a/hdl/hazard3_frontend.v b/hdl/hazard3_frontend.v
index ba6ce35..5372830 100644
--- a/hdl/hazard3_frontend.v
+++ b/hdl/hazard3_frontend.v
@@ -311,14 +311,14 @@ always @ (*) begin
mem_priv_r = fetch_priv;
mem_addr_vld_r = 1'b1;
case (1'b1)
- mem_addr_hold : begin mem_addr_r = fetch_addr; end
- jump_target_vld : begin
- mem_addr_r = {jump_target[W_ADDR-1:2], 2'b00};
- mem_priv_r = jump_priv || !U_MODE;
+ mem_addr_hold : begin mem_addr_r = fetch_addr; end
+ jump_target_vld || reset_holdoff : begin
+ mem_addr_r = {jump_target[W_ADDR-1:2], 2'b00};
+ mem_priv_r = jump_priv || !U_MODE;
end
- DEBUG_SUPPORT && debug_mode : begin mem_addr_vld_r = 1'b0; end
- !fetch_stall : begin mem_addr_r = fetch_addr; end
- default : begin mem_addr_vld_r = 1'b0; end
+ DEBUG_SUPPORT && debug_mode : begin mem_addr_vld_r = 1'b0; end
+ !fetch_stall : begin mem_addr_r = fetch_addr; end
+ default : begin mem_addr_vld_r = 1'b0; end
endcase
end