Work on docs. Document config options, expand the intro, move instruction timings and pseudocode to appendices.
This commit is contained in:
Luke Wren
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a79c857d82
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Readme.md
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Readme.md
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@ -3,8 +3,8 @@
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Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` instruction set and the following optional extensions:
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* `M`: integer multiply/divide/modulo
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* `C`: compressed instructions
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* `A` : atomic memory operations, with AHB5 global exclusives
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* `C`: compressed instructions
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* `Zicsr`: CSR access
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* `Zba`: address generation
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* `Zbb`: basic bit manipulation
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@ -35,10 +35,10 @@ These are links to the ratified versions of the extensions.
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| `C` v2.0 | [Unprivileged ISA 20191213](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf) |
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| `Zicsr` v2.0 | [Unprivileged ISA 20191213](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf) |
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| `Zifencei` v2.0 | [Unprivileged ISA 20191213](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf) |
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| `Zba` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf)
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| `Zbb` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf)
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| `Zbc` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf)
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| `Zbs` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf)
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| `Zba` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf) |
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| `Zbb` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf) |
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| `Zbc` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf) |
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| `Zbs` v1.0.0 | [Bit Manipulation ISA extensions 20210628](https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf) |
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| `Zbkb` v1.0.1 | [Scalar Cryptography ISA extensions 20220218](https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf) |
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| Machine ISA v1.12 | [Privileged Architecture 20211203](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf) |
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| Debug v0.13.2 | [RISC-V External Debug Support 20190322](https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf) |
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@ -10,11 +10,15 @@ include::rev.adoc[]
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include::sections/introduction.adoc[]
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include::sections/instruction_timings.adoc[]
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include::sections/instruction_pseudocode.adoc[]
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include::sections/configuration_and_integration.adoc[]
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include::sections/csr.adoc[]
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[[debug-chapter]]
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include::sections/debug.adoc[]
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[appendix]
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include::sections/instruction_timings.adoc[]
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[appendix]
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include::sections/instruction_pseudocode.adoc[]
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88638
doc/hazard3.pdf
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doc/hazard3.pdf
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Load Diff
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@ -0,0 +1,385 @@
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== Configuration and Integration
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=== Hazard3 Source Files
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Hazard3's source is written in Verilog 2005, and is self-contained. It can be found here: https://github.com/Wren6991/Hazard3/tree/master/hdl[github.com/Wren6991/Hazard3/blob/master/hdl].
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The file https://github.com/Wren6991/Hazard3/blob/master/hdl/hazard3.f[hdl/hazard3.f] is a list of all the source files required to instantiate Hazard3. This is supposed to be read by a tool called https://github.com/Wren6991/fpgascripts/blob/master/listfiles[listfiles], to generate other file list formats, but it should be simple enough to copy and hand-edit.
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Files ending with `.vh` are preprocessor include files used by the Hazard3 source. The most important are:
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* https://github.com/Wren6991/Hazard3/blob/master/hdl/hazard3_config.vh[hazard3_config.vh]: the main Hazard3 configuration header. Lists and describes Hazard3's global configuration parameters, such as ISA extension support
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* https://github.com/Wren6991/Hazard3/blob/master/hdl/hazard3_config_inst.vh[hazard3_config.vh]: a file which propagates configuration parameters through module instantiations, all the way down from Hazard3's top-level modules through the internals
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Therefore there are two ways to configure Hazard3:
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* Directly edit the parameter defaults in `hazard3_config.vh` in your local Hazard3 checkout (and then let the top-level parameters default when instantiating Hazard3)
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* Set all configuration parameters in your Hazard3 instantiation, and let the parameters propagate down through the hierarchy
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=== Top-level Modules
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Hazard3 has two top-level modules:
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* https://github.com/Wren6991/Hazard3/blob/master/hdl/hazard3_cpu_1port.v[hazard3_cpu_1port]
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* https://github.com/Wren6991/Hazard3/blob/master/hdl/hazard3_cpu_2port.v[hazard3_cpu_2port]
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These are both thin wrappers around the https://github.com/Wren6991/Hazard3/blob/master/hdl/hazard3_core.v[hazard3_core] module. `hazard3_cpu_1port` has a single AHB5 bus port which is shared for instruction fetch, loads, stores and AMOs. `hazard3_cpu_2port` has two AHB5 bus ports, one for instruction fetch, and the other for loads, stores and AMOs. The 2-port wrapper has higher potential for performance, but the 1-port wrapper may be simpler to integrate, since there is no need to arbitrate multiple bus masters externally.
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The core module `hazard3_core` can also be instantiated directly, which may be more efficient if support for some other bus standard is desired. However, the interface of `hazard3_core` will not be documented and is not guaranteed to be stable.
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=== Configuration Parameters
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==== Reset state configuration
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===== RESET_VECTOR
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Address of the first instruction executed after Hazard3 comes out of reset.
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Default value: all-zeroes.
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===== MTVEC_INIT
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Initial value of the machine trap vector base CSR (<<reg-mtvec>>).
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Bits clear in <<param-MTVEC_WMASK>> will never change from this initial value.
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Bits set in <<param-MTVEC_WMASK>> can be written/set/cleared as normal.
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Default value: all-zeroes.
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==== RISC-V ISA support
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[[param-EXTENSION_A]]
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===== EXTENSION_A
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Support for the A extension: atomic read/modify/write. 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_C]]
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===== EXTENSION_C
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Support for the C extension: compressed (variable-width). 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_M]]
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===== EXTENSION_M
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Support for the M extension: hardware multiply/divide/modulo. 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_ZBA]]
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===== EXTENSION_ZBA
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Support for Zba address generation instructions. 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_ZBB]]
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===== EXTENSION_ZBB
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Support for Zbb basic bit manipulation instructions. 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_ZBC]]
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===== EXTENSION_ZBC
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Support for Zbc carry-less multiplication instructions. 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_ZBS]]
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===== EXTENSION_ZBS
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Support for Zbs single-bit manipulation instructions. 0 for disable, 1 for enable.
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Default value: 1
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[[param-EXTENSION_ZBKB]]
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===== EXTENSION_ZBKB
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Support for Zbkb basic bit manipulation for cryptography.
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Requires: <<param-EXTENSION_ZBB>>. (Since Zbb and Zbkb have a large overlap, this flag enables only those instructions which are in Zbkb but aren't in Zbb. Therefore both flags must be set for full Zbkb support.)
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Default value: 1
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[[param-EXTENSION_XH3B]]
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===== EXTENSION_XH3B
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Custom bit manipulation instructions for Hazard3: `h3.bextm` and `h3.bextmi`.
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Default value: 1
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[[param-EXTENSION_ZIFENCEI]]
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===== EXTENSION_ZIFENCEI
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Support for the fence.i instruction. When the branch predictor is not present,
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this instruction is optional, since a plain branch/jump is sufficient to
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flush the instruction prefetch queue. When the branch predictor is enabled
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(<<param-BRANCH_PREDICTOR>> is 1), this instruction must be implemented.
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Default value: 1
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==== CSR support
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NOTE: the Zicsr extension is implied by any of <<param-CSR_M_MANDATORY>>, <<param-CSR_M_TRAP>>,
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<<param-CSR_COUNTER>>.
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[[param-CSR_M_MANDATORY]]
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===== CSR_M_MANDATORY
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Bare minimum CSR support e.g. <<reg-misa>>. This flag is an absolute
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requirement for compliance with the RISC-V privileged specification. However,
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the privileged specification itself is an optional extension. Hazard3 allows
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the mandatory CSRs to be disabled to save a small amount of area in
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deeply-embedded implementations.
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[[param-CSR_M_TRAP]]
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===== CSR_M_TRAP
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Include M-mode trap-handling CSRs, and enable trap support.
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[[param-CSR_COUNTER]]
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===== CSR_COUNTER
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Include the basic performance counters (`cycle`/`instret`) and relevant CSRs. Note that these performance counters are now in their own separate extension (Zicntr) and are no longer mandatory.
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[[param-U_MODE]]
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===== U_MODE
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Support the U (user) privilege level. In U-mode, the core performs unprivileged
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bus accesses, and software's access to CSRs is restricted. Additionally, if
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the PMP is included, the core may restrict U-mode software's access to
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memory.
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Requires: <<param-CSR_M_TRAP>>.
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[[param-PMP_REGIONS]]
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===== PMP_REGIONS
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Number of physical memory protection regions, or 0 for no PMP. PMP is more
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useful if U mode is supported, but this is not a requirement.
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Hazard3's PMP supports only the NAPOT and(if <<param-PMP_GRAIN>> is 0) NA4
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region types.
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Requires: <<param-CSR_M_TRAP>>.
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[[param-PMP_GRAIN]]
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===== PMP_GRAIN
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This is the _G_ parameter in the privileged spec, which defines the
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granularity of PMP regions. Minimum PMP region size is 1 <<(_G_ + 2) bytes.
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If _G_ > 0, `pmcfg.a` can not be set to NA4 (attempting to do so will set the
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region to OFF instead).
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If _G_ > 1, the _G_ - 1 LSBs of pmpaddr are read-only-0 when `pmpcfg.a` is
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OFF, and read-only-1 when `pmpcfg.a` is NAPOT.
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Default value: 0
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[[param-PMP_HARDWIRED]]
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===== PMP_HARDWIRED
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PMPADDR_HARDWIRED: If a bit is 1, the corresponding region's pmpaddr and
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pmpcfg registers are read-only, with their values fixed when the processor is
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instantiated. PMP_GRAIN is ignored on hardwired regions.
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Hardwired regions are far cheaper, both in area and comparison delay, than
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dynamically configurable regions.
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Hardwired PMP regions are a good option for setting default U-mode permissions
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on regions which have access controls outside of the processor, such as
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peripheral regions. For this case it's recommended to make hardwired regions
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the highest-numbered, so they can be overridden by lower-numbered dynamic
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regions.
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Default value: all-zeroes.
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[[param-PMP_HARDWIRED_ADDR]]
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===== PMP_HARDWIRED_ADDR
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Values of pmpaddr registers whose PMP_HARDWIRED bits are set to 1. Has no effect on PMP regions which are not hardwired.
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Default value: all-zeroes.
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[[param-PMP_HARDWIRED_CFG]]
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===== PMP_HARDWIRED_CFG
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Values of pmpcfg registers whose PMP_HARDWIRED bits are set to 1. Has no effect on PMP regions which are not hardwired.
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Default value: all-zeroes.
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[[param-DEBUG_SUPPORT]]
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===== DEBUG_SUPPORT
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Support for run/halt and instruction injection from an external Debug Module,
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support for Debug Mode, and Debug Mode CSRs.
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Requires: <<param-CSR_M_MANDATORY>>, <<param-CSR_M_TRAP>>.
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Default value: 0
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[[param-BREAKPOINT_TRIGGERS]]
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===== BREAKPOINT_TRIGGERS
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Number of hardware breakpoints. A breakpoint is implemented as a trigger that
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supports only exact execution address matches, ignoring instruction size.
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That is, a trigger which supports type=2 execute=1 (but not store/load=1,
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i.e. not a watchpoint).
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Requires: <<param-DEBUG_SUPPORT>>
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Default value: 0
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==== External interrupt support
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[[param-NUM_IRQS]]
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===== NUM_IRQS
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Number of external IRQs implemented in meiea, meipa, meifa and meipra, if
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<<param-CSR_M_TRAP>> is enabled. Minimum 1, maximum 512.
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Default value: 32
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[[param-IRQ_PRIORITY_BITS]]
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===== IRQ_PRIORITY_BITS
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Number of priority bits implemented for each interrupt in meipra. The
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number of distinct levels is (1 << IRQ_PRIORITY_BITS). Minimum 0, max 4.
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Note that having more than 1 priority level with a large number of IRQs
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will have a severe effect on timing.
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Default value: 0
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==== Identification Registers
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[[param-MVENDORID_VAL]]
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===== MVENDORID_VAL
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Value of the <<reg-mvendorid>> CSR. JEDEC JEP106-compliant vendor ID, or
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all-zeroes. 31:7 is continuation code count, 6:0 is ID. Parity bit is not
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stored.
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Default value: all-zeroes.
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[[param-MIMPID_VAL]]
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===== MIMPID_VAL
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Value of the <<reg-mimpid>> CSR. Implementation ID for this specific version of Hazard3. Should be a git hash, or all-zeroes.
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Default value: all-zeroes.
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[[param-MHARTID_VAL]]
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===== MHARTID_VAL
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Value of the <<reg-mhartid>> CSR. Each Hazard3 core has a single hardware thread. Multiple cores should have unique IDs.
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Default value: all-zeroes.
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[[param-MCONFIGPTR_VAL]]
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===== MCONFIGPTR_VAL
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Value of the <<reg-mconfigptr>> CSR. Pointer to configuration structure blob,
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or all-zeroes. Must be at least 4-byte-aligned.
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Default value: all-zeroes.
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==== Performance/size options
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[[param-REDUCED_BYPASS]]
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===== REDUCED_BYPASS
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Remove all forwarding paths except X->X (so back-to-back ALU ops can still run
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at 1 CPI), to save area. This has a significant impact on per-clock
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performance, so should only be considered for extremely low-area
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implementations.
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Default value: 0
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[[param-MULDIV_UNROLL]]
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===== MULDIV_UNROLL
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Bits per clock for multiply/divide circuit, if present. Must be a power of 2.
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Default value: 1
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[[param-MUL_FAST]]
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===== MUL_FAST
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Use single-cycle multiply circuit for MUL instructions, retiring to stage 3.
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The sequential multiply/divide circuit is still used for MULH*
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Default value: 0
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[[param-MUL_FASTER]]
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===== MUL_FASTER
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Retire fast multiply results to stage 2 instead of stage 3.
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Throughput is the same, but latency is reduced from 2 cycles to 1 cycle.
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Requires: <<param-MUL_FAST>>.
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Default value: 0
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[[param-MULH_FAST]]
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===== MULH_FAST
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Extend the fast multiply circuit to also cover MULH*, and remove
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the multiply functionality from the sequential multiply/divide circuit.
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Requires: <<param-MUL_FAST>>
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Default value: 0
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[[param-FAST_BRANCHCMP]]
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===== FAST_BRANCHCMP
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Instantiate a separate comparator (eq/lt/ltu) for branch comparisons, rather
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than using the ALU. Improves fetch address delay, especially if `Zba`
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extension is enabled. Disabling may save area.
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Default value: 1
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[[param-RESET_REGFILE]]
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===== RESET_REGFILE
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Whether to support reset of the general purpose registers. There are around 1k
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bits in the register file, so the reset can be disabled e.g. to permit
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block-RAM inference on FPGA.
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Default value: 1
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[[param-BRANCH_PREDICTOR]]
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===== BRANCH_PREDICTOR
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Enable branch prediction. The branch predictor consists of a single BTB entry
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which is allocated on a taken backward branch, and cleared on a mispredicted
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nontaken branch, a fence.i or a trap. Successful prediction eliminates the
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1-cyle fetch bubble on a taken branch, usually making tight loops faster.
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Requires: <<param-EXTENSION_ZIFENCEI>>
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Default value: 1
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[[param-MTVEC_WMASK]]
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===== MTVEC_WMASK
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||||
|
||||
MTVEC_WMASK: Mask of which bits in mtvec are writable. Full writability (except for bit 1) is
|
||||
recommended, because a common idiom in setup code is to set mtvec just
|
||||
past code that may trap, as a hardware `try {...} catch` block.
|
||||
|
||||
|
||||
* The vectoring mode can be made fixed by clearing the LSB of MTVEC_WMASK
|
||||
* In vectored mode, the vector table must be aligned to its size, rounded
|
||||
up to a power of two.
|
||||
|
||||
Default: All writable except for bit 1.
|
||||
|
||||
=== Interfaces (Top-level Ports)
|
||||
|
||||
TODO lol
|
||||
|
|
@ -9,6 +9,7 @@ IMPORTANT: The https://github.com/riscv/riscv-isa-manual/releases/download/Priv-
|
|||
|
||||
=== Standard M-mode Identification CSRs
|
||||
|
||||
[[reg-mvendorid]]
|
||||
==== mvendorid
|
||||
|
||||
Address: `0xf11`
|
||||
|
|
@ -35,7 +36,7 @@ Architecture identifier for Hazard3. Read-only, constant.
|
|||
| 30:0 | - | 0x1b (decimal 27): the https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[registered] architecture ID for Hazard3
|
||||
|===
|
||||
|
||||
|
||||
[[reg-mimpid]]
|
||||
==== mimpid
|
||||
|
||||
Address: `0xf13`
|
||||
|
|
@ -48,6 +49,7 @@ Implementation identifier. Read-only, configurable constant.
|
|||
| 31:0 | - | Should contain the git hash of the Hazard3 revision from which the processor was synthesised, or all-zeroes.
|
||||
|===
|
||||
|
||||
[[reg-mhartid]]
|
||||
==== mhartid
|
||||
|
||||
Address: `0xf14`
|
||||
|
|
@ -60,6 +62,7 @@ Hart identification register. Read-only, configurable constant.
|
|||
| 31:0 | - | Hazard3 cores possess only one hardware thread, so this is a unique per-core identifier, assigned consecutively from 0.
|
||||
|===
|
||||
|
||||
[[reg-mconfigptr]]
|
||||
==== mconfigptr
|
||||
|
||||
Address: `0xf15`
|
||||
|
|
@ -72,6 +75,7 @@ Pointer to configuration data structure. Read-only, configurable constant.
|
|||
| 31:0 | - | Either pointer to configuration data structure, containing information about the harts and system, or all-zeroes. At least 4-byte-aligned.
|
||||
|===
|
||||
|
||||
[[reg-misa]]
|
||||
==== misa
|
||||
|
||||
Address: `0x301`
|
||||
|
|
@ -162,6 +166,7 @@ The table below lists the fields which are _not_ hardwired to 0:
|
|||
| 3 | `msip` | Software interrupt pending. In spite of the name, this is not triggered by an instruction on this core, rather it is wired to an external memory-mapped register to provide a cross-hart level-sensitive doorbell interrupt.
|
||||
|===
|
||||
|
||||
[[reg-mtvec]]
|
||||
==== mtvec
|
||||
|
||||
Address: `0x305`
|
||||
|
|
@ -216,6 +221,7 @@ The following exception causes may be set by Hazard3 hardware:
|
|||
[cols="10h,~", options="header"]
|
||||
|===
|
||||
| Cause | Description
|
||||
| 0 | Instruction address misaligned
|
||||
| 1 | Instruction access fault
|
||||
| 2 | Illegal instruction
|
||||
| 3 | Breakpoint
|
||||
|
|
|
|||
|
|
@ -6,7 +6,8 @@ Hazard3, along with its external debug components, implements version 0.13.2 of
|
|||
* Abstract GPR access as required
|
||||
* Program Buffer, 2 words plus `impebreak`
|
||||
* Automatic trigger of abstract command (`abstractauto`) on `data0` or Program Buffer access for efficient memory block transfers from the host
|
||||
* (TODO) Some minimum useful trigger unit -- likely just breakpoints, no watchpoints
|
||||
* (Optional) System Bus Access, either through a dedicated AHB-Lite master, or multiplexed with a processor load/store port
|
||||
* (Optional) An instruction address trigger unit (hardware breakpoints)
|
||||
|
||||
=== Debug Topologies
|
||||
|
||||
|
|
|
|||
|
|
@ -4,19 +4,72 @@ Hazard3 is a 3-stage RISC-V processor, providing the following architectural sup
|
|||
|
||||
* `RV32I`: 32-bit base instruction set
|
||||
* `M`: integer multiply/divide/modulo
|
||||
* `A`: atomic memory operations
|
||||
* `A`: atomic memory operations, with AHB5 global exclusives
|
||||
* `C`: compressed instructions
|
||||
* `Zicsr`: CSR access
|
||||
* `Zba`: address generation
|
||||
* `Zbb`: basic bit manipulation
|
||||
* `Zbc`: carry-less multiplication
|
||||
* `Zbs`: single-bit manipulation
|
||||
* M-mode privileged instructions `ECALL`, `EBREAK`, `MRET`
|
||||
* The `WFI` instruction
|
||||
* `Zicsr`: CSR access
|
||||
* The machine-mode (M-mode) privilege state, and standard M-mode CSRs
|
||||
* Debug support, fully compliant with version 0.13.2 of the RISC-V external debug specification
|
||||
* `Zbkb`: basic bit manipulation for scalar cryptography
|
||||
* Debug, Machine and User privilege/execution modes
|
||||
* Privileged instructions `ECALL`, `EBREAK`, `MRET` and `WFI`
|
||||
* External debug support
|
||||
* Instruction address trigger unit (hardware breakpoints)
|
||||
|
||||
The following are planned for future implementation:
|
||||
=== Architectural Overview
|
||||
|
||||
* Trigger unit for debug mode
|
||||
** Likely breakpoints only
|
||||
==== Bus Interfaces
|
||||
|
||||
Hazard3 implements either one or two industry-standard AHB5 bus interfaces. The AHB family is characterised by a fixed 2-phase bus pipeline, ideal for a 3-stage 2-port processor like Hazard3. AHB5 is distinguished from older AHB standards mainly by its additional bus attributes, and its support for global exclusives, which Hazard3 uses to implement multiprocessor support for the RISC-V atomics extension.
|
||||
|
||||
In Hazard3's single-port configuration, a single AHB5 port performs memory accesses for instruction fetch and loads/stores/AMOs. The dual-port configuration adds a dedicated port for instruction fetch. Dual-port yields around 10% higher per-clock performance, as well as a shorter critical address-phase path, but the single-port configuration is simpler to integrate.
|
||||
|
||||
==== Pipe Stages
|
||||
|
||||
In order, the three stages are:
|
||||
|
||||
* `F`: Fetch
|
||||
** Contains the data phase for instruction fetch
|
||||
** Contains the instruction prefetch buffer
|
||||
** Predecodes register numbers `rs1`/`rs2`, for faster register file read and register bypass
|
||||
* `X`: Execute
|
||||
** Decode and execute instructions
|
||||
** Drive the address phase for load/store/AMO
|
||||
** Generate jump/branch addresses
|
||||
* `M`: Memory
|
||||
** Contains the data phase for load/store/AMO
|
||||
** Register writeback is at the end of stage `M`
|
||||
** Generate exception addresses
|
||||
|
||||
The instruction fetch address phase is best thought of as residing in stage `X`, since in general execution the feedback loop between jump/branch decode and address issue in stage `X`, and the fetch data phase in stage `F`, is what defines Hazard3's jump/branch performance.
|
||||
|
||||
==== Multiply/Divide
|
||||
|
||||
For basic M-extension support, Hazard3 instantiates a sequential multiply/divide circuit (restoring divide, repeated-addition multiply), which takes 32 cycles to perform a multiply or divide.
|
||||
|
||||
For modest performance improvement, this circuit can be unrolled, stacking multiple identical arithmetic circuits within one cycle. This simple approach is enough for 2 or 4 bits per clock, depending on area and frequency targets.
|
||||
|
||||
For the best integer multiply performance, a single-cycle multiplier can be instantiated, retiring either to stage 3 (lower timing impact) or stage 2 (no dependency stall). This multiplier can implement either 32-bit `mul` only, which is by far the most common of the four multiply instructions, or can be extended to implement `mulh`/`mulhu`/`mulhsu` as well. If all four multiplies are implemented by the single-cycle multiplier, then multiply support is removed from the sequential multiply/divide circuit.
|
||||
|
||||
=== List of RISC-V Specifications
|
||||
|
||||
These are links to the ratified versions of the base instruction set and extensions implemented by Hazard3.
|
||||
|
||||
[%autowidth.stretch, options="header"]
|
||||
|===
|
||||
| Extension | Specification
|
||||
| `RV32I` v2.1 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
|
||||
| `M` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
|
||||
| `A` v2.1 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
|
||||
| `C` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
|
||||
| `Zicsr` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
|
||||
| `Zifencei` v2.0 | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
|
||||
| `Zba` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
|
||||
| `Zbb` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
|
||||
| `Zbc` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
|
||||
| `Zbs` v1.0.0 | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
|
||||
| `Zbkb` v1.0.1 | https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf[Scalar Cryptography ISA extensions 20220218]
|
||||
| Machine ISA v1.12 | https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf[Privileged Architecture 20211203]
|
||||
| Debug v0.13.2 | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf[RISC-V External Debug Support 20190322]
|
||||
|===
|
||||
|
|
|
|||
Loading…
Reference in New Issue