First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
This commit is contained in:
Luke Wren
parent
4ba3f7ceb9
commit
d62861159f
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@ -77,12 +77,15 @@ parameter CSR_M_TRAP = 1,
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// CSR_COUNTER: Include performance counters and relevant M-mode CSRs
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parameter CSR_COUNTER = 1,
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// U_MODE: support for the U (user, unprivileged) execution mode. If U_MODE is
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// 1, PMP support is recommended.
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// U_MODE: Support the U (user) execution mode. In U mode, the core performs
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// unprivileged bus accesses, and software's access to CSRs is restricted.
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// Additionally, if the PMP is included, the core may restrict U-mode
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// software's access to memory.
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// Requires: CSR_M_TRAP.
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parameter U_MODE = 0,
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// PMP_REGIONS: Number of physical memory protection regions, or 0 for no PMP.
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// PMP is more useful if U mode is supported, but has use on M-only systems.
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// PMP is more useful if U mode is supported, but this is not a requirement.
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parameter PMP_REGIONS = 0,
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// DEBUG_SUPPORT: Support for run/halt and instruction injection from an
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@ -118,7 +118,6 @@ begin
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end
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endfunction
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wire enter_debug_mode;
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wire exit_debug_mode;
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@ -130,30 +129,57 @@ always @ (posedge clk or negedge rst_n) begin
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end
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end
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// ----------------------------------------------------------------------------
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// Trap-handling CSRs
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wire debug_suppresses_trap_update = DEBUG_SUPPORT && (debug_mode || enter_debug_mode);
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// Two-level interrupt enable stack, shuffled on entry/exit:
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reg m_mode;
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reg mstatus_mpie;
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reg mstatus_mie;
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reg mstatus_mpp; // only MSB is implemented
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reg mstatus_mprv;
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wire wen_m_mode = wen && (m_mode || debug_mode);
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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m_mode <= 1'b1;
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mstatus_mpie <= 1'b0;
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mstatus_mie <= 1'b0;
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mstatus_mpp <= 1'b1;
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mstatus_mprv <= 1'b0;
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end else if (CSR_M_TRAP) begin
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if (trap_enter_vld && trap_enter_rdy && !debug_suppresses_trap_update) begin
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if (except == EXCEPT_MRET) begin
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mstatus_mpie <= 1'b1;
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mstatus_mie <= mstatus_mpie;
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if (U_MODE) begin
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m_mode <= mstatus_mpp;
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end
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end else begin
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mstatus_mpie <= mstatus_mie;
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mstatus_mie <= 1'b0;
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if (U_MODE) begin
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m_mode <= 1'b1;
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mstatus_mpp <= m_mode;
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end
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end else if (wen && addr == MSTATUS) begin
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{mstatus_mpie, mstatus_mie} <= {wdata_update[7], wdata_update[3]};
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end
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end else if (wen_m_mode && addr == MSTATUS) begin
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mstatus_mpie <= wdata_update[7];
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mstatus_mie <= wdata_update[3];
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mstatus_mprv <= wdata_update[17];
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// Note only the MSB of MPP is implemented. It reads back as 11 or 00.
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mstatus_mpp <= wdata_update[12];
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end else if (wen && debug_mode && addr == DCSR && U_MODE && DEBUG_SUPPORT) begin
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// Debugger can change/observe core state directly through
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// dcsr.prv (this doesn't affect debugger operation, as all
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// operations have an effective level of M-mode whilst the core
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// is halted for debug.)
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m_mode <= wdata_update[1];
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end
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end
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end
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@ -164,7 +190,7 @@ always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mscratch <= X0;
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end else if (CSR_M_TRAP) begin
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if (wen && addr == MSCRATCH)
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if (wen_m_mode && addr == MSCRATCH)
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mscratch <= wdata_update;
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end
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end
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@ -178,7 +204,7 @@ always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mtvec_reg <= MTVEC_INIT;
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end else if (CSR_M_TRAP) begin
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if (wen && addr == MTVEC)
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if (wen_m_mode && addr == MTVEC)
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mtvec_reg <= update_nonconst(mtvec_reg, MTVEC_WMASK);
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end
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end
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@ -194,7 +220,7 @@ always @ (posedge clk or negedge rst_n) begin
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end else if (CSR_M_TRAP) begin
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if (trap_enter_vld && trap_enter_rdy && except != EXCEPT_MRET && !debug_suppresses_trap_update) begin
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mepc <= mepc_in & MEPC_MASK;
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end else if (wen && addr == MEPC) begin
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end else if (wen_m_mode && addr == MEPC) begin
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mepc <= wdata_update & MEPC_MASK;
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end
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end
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@ -208,7 +234,7 @@ always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mie <= X0;
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end else if (CSR_M_TRAP) begin
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if (wen && addr == MIE)
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if (wen_m_mode && addr == MIE)
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mie <= update_nonconst(mie, MIE_WMASK);
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end
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end
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@ -236,7 +262,7 @@ always @ (posedge clk or negedge rst_n) begin
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if (trap_enter_vld && trap_enter_rdy && except != EXCEPT_MRET && !debug_suppresses_trap_update) begin
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mcause_irq <= mcause_irq_next;
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mcause_code <= mcause_code_next;
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end else if (wen && addr == MCAUSE) begin
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end else if (wen_m_mode && addr == MCAUSE) begin
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{mcause_irq, mcause_code} <= {wdata_update[31], wdata_update[5:0]};
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end
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end
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@ -266,13 +292,13 @@ always @ (posedge clk or negedge rst_n) begin
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meie1 <= X0;
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meie2 <= X0;
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meie3 <= X0;
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end else if (wen && addr == MEIE0) begin
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end else if (wen_m_mode && addr == MEIE0) begin
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meie0 <= update_nonconst(meie0, MEIE0_WMASK);
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end else if (wen && addr == MEIE1) begin
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end else if (wen_m_mode && addr == MEIE1) begin
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meie1 <= update_nonconst(meie1, MEIE1_WMASK);
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end else if (wen && addr == MEIE2) begin
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end else if (wen_m_mode && addr == MEIE2) begin
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meie2 <= update_nonconst(meie2, MEIE2_WMASK);
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end else if (wen && addr == MEIE3) begin
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end else if (wen_m_mode && addr == MEIE3) begin
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meie3 <= update_nonconst(meie3, MEIE3_WMASK);
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end
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end
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@ -313,7 +339,7 @@ always @ (posedge clk or negedge rst_n) begin
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if (!(mcountinhibit_ir || debug_mode) && instr_ret)
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{minstreth, minstret} <= (({minstreth, minstret} + 1'b1) & ~({2*XLEN{1'b1}} << W_COUNTER))
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| ({minstreth, minstret} & ({2*XLEN{1'b1}} << W_COUNTER));
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if (wen) begin
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if (wen_m_mode) begin
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if (addr == MCYCLEH)
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mcycleh <= wdata_update;
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if (addr == MCYCLE)
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@ -329,6 +355,27 @@ always @ (posedge clk or negedge rst_n) begin
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end
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end
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// Note we still implement tm, even though the time/timeh CSRs are
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// unimplemented. The tm bit provides a standard way to configure whether
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// M-mode software permits the trapped access to reach the timer registers.
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// (This is in fact required by the RVM-CSI platform spec.)
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reg mcounteren_cy;
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reg mcounteren_tm;
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reg mcounteren_ir;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mcounteren_cy <= 1'b0;
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mcounteren_tm <= 1'b0;
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mcounteren_ir <= 1'b0;
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end else if (CSR_COUNTER && U_MODE && wen_m_mode && addr == MCOUNTEREN) begin
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// Note this register only exists when U mode is implemented.
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mcounteren_cy <= wdata_update[0];
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mcounteren_tm <= wdata_update[1];
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mcounteren_ir <= wdata_update[2];
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end
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end
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// ----------------------------------------------------------------------------
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// Debug-mode CSRs
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@ -387,6 +434,14 @@ assign dbg_data0_wen = debug_mode && wen && addr == DMDATA0;
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reg decode_match;
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// Address match conditions -- certain CSRs are inaccessible if their
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// conditions are not met:
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wire match_drw = DEBUG_SUPPORT && debug_mode;
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wire match_mrw = m_mode || debug_mode;
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wire match_mro = (m_mode || debug_mode) && !wen_soon;
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wire match_urw = U_MODE && 1'b1;
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wire match_uro = U_MODE && !wen_soon;
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always @ (*) begin
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decode_match = 1'b0;
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rdata = {XLEN{1'b0}};
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@ -397,7 +452,7 @@ always @ (*) begin
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MISA: if (CSR_M_MANDATORY) begin
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// WARL, so it is legal to be tied constant
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = {
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2'h1, // MXL: 32-bit
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{XLEN-28{1'b0}}, // WLRL
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@ -415,30 +470,30 @@ always @ (*) begin
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};
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end
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MVENDORID: if (CSR_M_MANDATORY) begin
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decode_match = !wen_soon; // MRO
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decode_match = match_mro;
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rdata = MVENDORID_VAL;
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end
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MARCHID: if (CSR_M_MANDATORY) begin
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decode_match = !wen_soon; // MRO
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decode_match = match_mro;
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// Hazard3's open source architecture ID
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rdata = 32'd27;
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end
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MIMPID: if (CSR_M_MANDATORY) begin
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decode_match = !wen_soon; // MRO
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decode_match = match_mro;
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rdata = MIMPID_VAL;
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end
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MHARTID: if (CSR_M_MANDATORY) begin
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decode_match = !wen_soon; // MRO
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decode_match = match_mro;
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rdata = MHARTID_VAL;
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end
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MCONFIGPTR: if (CSR_M_MANDATORY) begin
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decode_match = !wen_soon; // MRO
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decode_match = match_mro;
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rdata = MCONFIGPTR_VAL;
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end
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MSTATUS: if (CSR_M_MANDATORY || CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = {
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1'b0, // Never any dirty state besides GPRs
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8'd0, // (WPRI)
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@ -447,14 +502,14 @@ always @ (*) begin
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1'b0, // TVM (trap virtual memory), tied 0 if no S mode.
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1'b0, // MXR (Make eXecutable Readable), tied 0 if not S mode.
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1'b0, // SUM, tied 0, we have no S or U mode
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1'b0, // MPRV (modify privilege), tied 0 if no U mode
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mstatus_mprv, // MPRV (modify privilege)
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4'd0, // XS, FS always "off" (no extension state to clear!)
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2'b11, // MPP (M-mode previous privilege), we are always M-mode
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{2{m_mode}}, // MPP (M-mode previous privilege), only M and U supported
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2'd0, // (WPRI)
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1'b0, // SPP, tied 0 if S mode not supported
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mstatus_mpie,
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mstatus_mpie, // Previous interrupt enable
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3'd0, // No S, U
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mstatus_mie,
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mstatus_mie, // Interrupt enable
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3'd0 // No S, U
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};
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end
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@ -464,7 +519,7 @@ always @ (*) begin
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// unimplemented in this case, but now it must be decoded even if
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// hardwired to 0.
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MSTATUSH: if (CSR_M_MANDATORY || CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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end
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// MEDELEG, MIDELEG should not exist for M-only implementations. Will raise
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@ -476,17 +531,17 @@ always @ (*) begin
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// This is a 32 bit synthesised register with set/clear/write/read, don't
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// turn it on unless we really have to
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MSCRATCH: if (CSR_M_TRAP && CSR_M_MANDATORY) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = mscratch;
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end
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MEPC: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = mepc;
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end
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MCAUSE: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = {
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mcause_irq, // Sign bit is 1 for IRQ, 0 for exception
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{26{1'b0}}, // Padding
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@ -495,23 +550,23 @@ always @ (*) begin
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end
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MTVAL: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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// Hardwired to 0
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end
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MIE: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = mie;
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end
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MIP: if (CSR_M_TRAP) begin
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// Writes are permitted, but ignored.
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = mip;
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end
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MTVEC: if (CSR_M_TRAP) begin
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decode_match = 1'b1;
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decode_match = match_mrw;
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rdata = {
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mtvec[XLEN-1:2], // BASE
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1'b0, // Reserved mode bit gets WARL'd to 0
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@ -523,98 +578,98 @@ always @ (*) begin
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// Counter CSRs
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// Get the tied WARLs out the way first
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MHPMCOUNTER3: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER4: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER5: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER6: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER7: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER8: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER9: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER10: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER11: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER12: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER13: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER14: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER15: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER16: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER17: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER18: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER19: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER20: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER21: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER22: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER23: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER24: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER25: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER26: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER27: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER28: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER29: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER30: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER31: if (CSR_COUNTER) begin decode_match = 1'b1; end
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MHPMCOUNTER3: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER4: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER5: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER6: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER7: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER8: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER9: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER10: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER11: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER12: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER13: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER14: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER15: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER16: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER17: if (CSR_COUNTER) begin decode_match = match_mrw; end
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MHPMCOUNTER18: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER19: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER20: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER21: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER22: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER23: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER24: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER25: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER26: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER27: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER28: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER29: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER30: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER31: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
|
||||
MHPMCOUNTER3H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER4H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER5H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER6H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER7H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER8H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER9H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER10H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER11H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER12H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER13H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER14H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER15H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER16H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER17H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER18H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER19H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER20H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER21H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER22H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER23H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER24H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER25H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER26H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER27H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER28H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER29H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER30H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER31H: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMCOUNTER3H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER4H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER5H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER6H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER7H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER8H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER9H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER10H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER11H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER12H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER13H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER14H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER15H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER16H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER17H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER18H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER19H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER20H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER21H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER22H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER23H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER24H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER25H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER26H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER27H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER28H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER29H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER30H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMCOUNTER31H: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
|
||||
MHPMEVENT3: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT4: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT5: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT6: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT7: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT8: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT9: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT10: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT11: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT12: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT13: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT14: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT15: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT16: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT17: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT18: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT19: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT20: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT21: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT22: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT23: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT24: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT25: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT26: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT27: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT28: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT29: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT30: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT31: if (CSR_COUNTER) begin decode_match = 1'b1; end
|
||||
MHPMEVENT3: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT4: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT5: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT6: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT7: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT8: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT9: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT10: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT11: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT12: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT13: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT14: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT15: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT16: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT17: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT18: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT19: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT20: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT21: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT22: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT23: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT24: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT25: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT26: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT27: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT28: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT29: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT30: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
MHPMEVENT31: if (CSR_COUNTER) begin decode_match = match_mrw; end
|
||||
|
||||
MCOUNTINHIBIT: if (CSR_COUNTER) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = {
|
||||
29'd0,
|
||||
mcountinhibit_ir,
|
||||
|
|
@ -624,20 +679,53 @@ always @ (*) begin
|
|||
end
|
||||
|
||||
MCYCLE: if (CSR_COUNTER) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = mcycle;
|
||||
end
|
||||
MINSTRET: if (CSR_COUNTER) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = minstret;
|
||||
end
|
||||
|
||||
MCYCLEH: if (CSR_COUNTER) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = mcycleh;
|
||||
end
|
||||
MINSTRETH: if (CSR_COUNTER) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = minstreth;
|
||||
end
|
||||
|
||||
MCOUNTEREN: if (CSR_COUNTER && U_MODE) begin
|
||||
decode_match = match_mrw;
|
||||
rdata = {
|
||||
29'd0,
|
||||
mcounteren_ir,
|
||||
mcounteren_tm,
|
||||
mcounteren_cy
|
||||
};
|
||||
end
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
// U-mode CSRs
|
||||
|
||||
// The read-only counters are always visible to M mode, and are visible to
|
||||
// U mode if the corresponding mcounteren bit is set.
|
||||
CYCLE: if (CSR_COUNTER) begin
|
||||
decode_match = mcounteren_cy ? match_uro : match_mro;
|
||||
rdata = mcycle;
|
||||
end
|
||||
CYCLEH: if (CSR_COUNTER && U_MODE) begin
|
||||
decode_match = mcounteren_cy ? match_uro : match_mro;
|
||||
rdata = mcycleh;
|
||||
end
|
||||
|
||||
INSTRET: if (CSR_COUNTER) begin
|
||||
decode_match = mcounteren_ir ? match_uro : match_mro;
|
||||
rdata = minstret;
|
||||
end
|
||||
INSTRETH: if (CSR_COUNTER) begin
|
||||
decode_match = mcounteren_ir ? match_uro : match_mro;
|
||||
rdata = minstreth;
|
||||
end
|
||||
|
||||
|
|
@ -649,14 +737,14 @@ always @ (*) begin
|
|||
// - tselect must raise an exception when written to
|
||||
// Otherwise it returns an error instead of 0 count when enumerating triggers
|
||||
TSELECT: if (DEBUG_SUPPORT) begin
|
||||
decode_match = !wen_soon;
|
||||
decode_match = match_mro;
|
||||
end
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
// Debug CSRs
|
||||
|
||||
DCSR: if (DEBUG_SUPPORT && debug_mode) begin
|
||||
decode_match = 1'b1;
|
||||
DCSR: if (DEBUG_SUPPORT) begin
|
||||
decode_match = match_drw;
|
||||
rdata = {
|
||||
4'h4, // xdebugver = 4, for 0.13.2 debug spec
|
||||
12'd0, // reserved
|
||||
|
|
@ -667,20 +755,20 @@ always @ (*) begin
|
|||
1'b1, // stoptime = 0, no core-local timer increment in debug mode
|
||||
dcsr_cause,
|
||||
1'b0, // reserved
|
||||
1'b0, // mprven = 0, we don't have MPRV support
|
||||
1'b0, // mprven = 0, debugger always acts as M-mode
|
||||
1'b0, // nmip = 0, we have no NMI
|
||||
dcsr_step,
|
||||
2'h3 // prv = 3, we only have M mode
|
||||
{2{m_mode}} // priv = M or U, report the core state directly
|
||||
};
|
||||
end
|
||||
|
||||
DPC: if (DEBUG_SUPPORT && debug_mode) begin
|
||||
decode_match = 1'b1;
|
||||
DPC: if (DEBUG_SUPPORT) begin
|
||||
decode_match = match_drw;
|
||||
rdata = dpc;
|
||||
end
|
||||
|
||||
DMDATA0: if (DEBUG_SUPPORT && debug_mode) begin
|
||||
decode_match = 1'b1;
|
||||
DMDATA0: if (DEBUG_SUPPORT) begin
|
||||
decode_match = match_drw;
|
||||
rdata = dbg_data0_rdata;
|
||||
end
|
||||
|
||||
|
|
@ -688,47 +776,47 @@ always @ (*) begin
|
|||
// Custom CSRs
|
||||
|
||||
MEIE0: if (CSR_M_TRAP && N_IRQ_REG0 > 0) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = meie0;
|
||||
end
|
||||
|
||||
MEIE1: if (CSR_M_TRAP && N_IRQ_REG1 > 0) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = meie1;
|
||||
end
|
||||
|
||||
MEIE2: if (CSR_M_TRAP && N_IRQ_REG2 > 0) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = meie2;
|
||||
end
|
||||
|
||||
MEIE3: if (CSR_M_TRAP && N_IRQ_REG3 > 0) begin
|
||||
decode_match = 1'b1;
|
||||
decode_match = match_mrw;
|
||||
rdata = meie3;
|
||||
end
|
||||
|
||||
MEIP0: if (CSR_M_TRAP && N_IRQ_REG0 > 0) begin
|
||||
decode_match = !wen_soon;
|
||||
decode_match = match_mro;
|
||||
rdata = meip0;
|
||||
end
|
||||
|
||||
MEIP1: if (CSR_M_TRAP && N_IRQ_REG1 > 0) begin
|
||||
decode_match = !wen_soon;
|
||||
decode_match = match_mro;
|
||||
rdata = meip1;
|
||||
end
|
||||
|
||||
MEIP2: if (CSR_M_TRAP && N_IRQ_REG2 > 0) begin
|
||||
decode_match = !wen_soon;
|
||||
decode_match = match_mro;
|
||||
rdata = meip2;
|
||||
end
|
||||
|
||||
MEIP3: if (CSR_M_TRAP && N_IRQ_REG3 > 0) begin
|
||||
decode_match = !wen_soon;
|
||||
decode_match = match_mro;
|
||||
rdata = meip3;
|
||||
end
|
||||
|
||||
MLEI: if (CSR_M_TRAP) begin
|
||||
decode_match = !wen_soon;
|
||||
decode_match = match_mro;
|
||||
rdata = {{XLEN-9{1'b0}}, mlei, 2'b00};
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -161,6 +161,17 @@ localparam MEIP2 = 12'hfe2; // External interrupt pending register 2
|
|||
localparam MEIP3 = 12'hfe3; // External interrupt pending register 3
|
||||
localparam MLEI = 12'hfe4; // Lowest external interrupt number
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// U-mode CSRs
|
||||
|
||||
// Read-only aliases of M-mode counter CSRs:
|
||||
localparam CYCLE = 12'hc00;
|
||||
localparam TIME = 12'hc01;
|
||||
localparam INSTRET = 12'hc02;
|
||||
localparam CYCLEH = 12'hc80;
|
||||
localparam TIMEH = 12'hc81;
|
||||
localparam INSTRETH = 12'hc82;
|
||||
|
||||
// ----------------------------------------------------------------------------
|
||||
// Trigger Module
|
||||
|
||||
|
|
|
|||
|
|
@ -218,7 +218,7 @@ always @ (*) begin: check_i_match
|
|||
i_partial_match = 1'b0;
|
||||
i_l = 1'b0;
|
||||
i_x = 1'b0;
|
||||
for (i = PMP_REGIONS - 1; i >= 0; i = i - 1) begin
|
||||
for (i = PMP_REGIONS - 1; i >= 0; i = i -q 1) begin
|
||||
match_hw0 = |pmpcfg_a[i] && (i_addr & match_mask[i]) == match_addr[i];
|
||||
match_hw1 = |pmpcfg_a[i] && (i_addr_hw1 & match_mask[i]) == match_addr[i];
|
||||
if (match_hw0 || match_hw1) begin
|
||||
|
|
|
|||
Loading…
Reference in New Issue