From d9300ee127551d07ee6839b21b33595955e75aac Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 17 Jul 2021 19:26:45 +0100 Subject: [PATCH] Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry --- hdl/hazard3_cpu_1port.v | 5 ++++- hdl/hazard3_cpu_2port.v | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hdl/hazard3_cpu_1port.v b/hdl/hazard3_cpu_1port.v index a13219b..21e801d 100644 --- a/hdl/hazard3_cpu_1port.v +++ b/hdl/hazard3_cpu_1port.v @@ -231,8 +231,11 @@ assign core_aph_ready_i = ahblm_hready && bus_gnt_i; assign core_dph_ready_i = ahblm_hready && bus_active_dph_i; assign core_dph_err_i = ahblm_hready && bus_active_dph_i && ahblm_hresp; +// D-side errors are reported even when not ready, so that the core can make +// use of the two-phase error response to cleanly squash a second load/store +// chasing the faulting one down the pipeline. assign core_aph_ready_d = ahblm_hready && bus_gnt_d; assign core_dph_ready_d = ahblm_hready && bus_active_dph_d; -assign core_dph_err_d = ahblm_hready && bus_active_dph_d && ahblm_hresp; +assign core_dph_err_d = bus_active_dph_d && ahblm_hresp; endmodule diff --git a/hdl/hazard3_cpu_2port.v b/hdl/hazard3_cpu_2port.v index 247600c..1593cfd 100644 --- a/hdl/hazard3_cpu_2port.v +++ b/hdl/hazard3_cpu_2port.v @@ -199,9 +199,12 @@ always @ (posedge clk or negedge rst_n) else if (d_hready) dphase_active_d <= core_aph_req_d; +// D-side errors are reported even when not ready, so that the core can make +// use of the two-phase error response to cleanly squash a second load/store +// chasing the faulting one down the pipeline. assign core_aph_ready_d = d_hready && core_aph_req_d; assign core_dph_ready_d = d_hready && dphase_active_d; -assign core_dph_err_d = d_hready && dphase_active_d && d_hresp; +assign core_dph_err_d = dphase_active_d && d_hresp; assign core_rdata_d = d_hrdata; assign d_hwdata = core_wdata_d;