From da244f54c3a5fc747f38ea2404f9feda544d8b2e Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Mon, 23 May 2022 16:22:01 +0100 Subject: [PATCH] Remove unused FAKE_DUALPORT option from regfile --- hdl/hazard3_regfile_1w2r.v | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/hdl/hazard3_regfile_1w2r.v b/hdl/hazard3_regfile_1w2r.v index d6c2604..f79915d 100644 --- a/hdl/hazard3_regfile_1w2r.v +++ b/hdl/hazard3_regfile_1w2r.v @@ -6,15 +6,9 @@ // Register file // Single write port, dual read port -// FAKE_DUALPORT: if 1, implement regfile with pair of memories. -// Write ports are ganged together, read ports operate independently. -// This allows BRAM inference on FPGAs with single-read-port BRAMs. -// (Looking at you iCE40) - `default_nettype none module hazard3_regfile_1w2r #( - parameter FAKE_DUALPORT = 0, parameter RESET_REGS = 0, // Unsupported for FAKE_DUALPORT parameter N_REGS = 16, parameter W_DATA = 32, @@ -35,19 +29,7 @@ module hazard3_regfile_1w2r #( ); generate -if (FAKE_DUALPORT) begin: fake_dualport - reg [W_DATA-1:0] mem1 [0:N_REGS-1]; - reg [W_DATA-1:0] mem2 [0:N_REGS-1]; - - always @ (posedge clk) begin - if (wen) begin - mem1[waddr] <= wdata; - mem2[waddr] <= wdata; - end - rdata1 <= mem1[raddr1]; - rdata2 <= mem2[raddr2]; - end -end else if (RESET_REGS) begin: real_dualport_reset +if (RESET_REGS) begin: real_dualport_reset // This will presumably always be implemented with flops reg [W_DATA-1:0] mem [0:N_REGS-1];