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Add note on clang-16 to Readme

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Luke Wren 2024-08-07 13:15:27 -07:00
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@ -77,7 +77,9 @@ You will need:
* A recent Yosys build to process the Verilog (these instructions were last tested with `b1569de5`)
* A `riscv32-unknown-elf-` toolchain to build software for the core
* A native `clang` to build the simulator
* A native `clang-16` to build the simulator
`clang-17` is also known to work fine. `clang-18` does work, but has a serious compile time regression with CXXRTL output, which is why the `tb_cxxrtl` Makefile explicitly selects `clang-16`.
## Yosys